1//===- MipsMCCodeEmitter.h - Convert Mips Code to Machine Code --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the MipsMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H
14#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H
15
16#include "llvm/MC/MCCodeEmitter.h"
17#include <cstdint>
18
19namespace llvm {
20
21class MCContext;
22class MCExpr;
23class MCFixup;
24class MCInst;
25class MCInstrInfo;
26class MCOperand;
27class MCSubtargetInfo;
28class raw_ostream;
29
30class MipsMCCodeEmitter : public MCCodeEmitter {
31  const MCInstrInfo &MCII;
32  MCContext &Ctx;
33  bool IsLittleEndian;
34
35  bool isMicroMips(const MCSubtargetInfo &STI) const;
36  bool isMips32r6(const MCSubtargetInfo &STI) const;
37
38public:
39  MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle)
40      : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {}
41  MipsMCCodeEmitter(const MipsMCCodeEmitter &) = delete;
42  MipsMCCodeEmitter &operator=(const MipsMCCodeEmitter &) = delete;
43  ~MipsMCCodeEmitter() override = default;
44
45  void EmitByte(unsigned char C, raw_ostream &OS) const;
46
47  void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
48                       raw_ostream &OS) const;
49
50  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
51                         SmallVectorImpl<MCFixup> &Fixups,
52                         const MCSubtargetInfo &STI) const override;
53
54  // getBinaryCodeForInstr - TableGen'erated function for getting the
55  // binary encoding for an instruction.
56  uint64_t getBinaryCodeForInstr(const MCInst &MI,
57                                 SmallVectorImpl<MCFixup> &Fixups,
58                                 const MCSubtargetInfo &STI) const;
59
60  // getJumpTargetOpValue - Return binary encoding of the jump
61  // target operand. If the machine operand requires relocation,
62  // record the relocation and return zero.
63  unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
64                                SmallVectorImpl<MCFixup> &Fixups,
65                                const MCSubtargetInfo &STI) const;
66
67  // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump
68  // target operand. If the machine operand requires relocation,
69  // record the relocation and return zero.
70  unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
71                                  SmallVectorImpl<MCFixup> &Fixups,
72                                  const MCSubtargetInfo &STI) const;
73
74  // getUImm5Lsl2Encoding - Return binary encoding of the microMIPS jump
75  // target operand.
76  unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
77                                SmallVectorImpl<MCFixup> &Fixups,
78                                const MCSubtargetInfo &STI) const;
79
80  unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
81                             SmallVectorImpl<MCFixup> &Fixups,
82                             const MCSubtargetInfo &STI) const;
83
84  unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
85                                SmallVectorImpl<MCFixup> &Fixups,
86                                const MCSubtargetInfo &STI) const;
87
88  // getSImm9AddiuspValue - Return binary encoding of the microMIPS addiusp
89  // instruction immediate operand.
90  unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
91                                SmallVectorImpl<MCFixup> &Fixups,
92                                const MCSubtargetInfo &STI) const;
93
94  // getBranchTargetOpValue - Return binary encoding of the branch
95  // target operand. If the machine operand requires relocation,
96  // record the relocation and return zero.
97  unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
98                                  SmallVectorImpl<MCFixup> &Fixups,
99                                  const MCSubtargetInfo &STI) const;
100
101  // getBranchTargetOpValue1SImm16 - Return binary encoding of the branch
102  // target operand. If the machine operand requires relocation,
103  // record the relocation and return zero.
104  unsigned getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
105                                         SmallVectorImpl<MCFixup> &Fixups,
106                                         const MCSubtargetInfo &STI) const;
107
108  // getBranchTargetOpValueMMR6 - Return binary encoding of the branch
109  // target operand. If the machine operand requires relocation,
110  // record the relocation and return zero.
111  unsigned getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
112                                      SmallVectorImpl<MCFixup> &Fixups,
113                                      const MCSubtargetInfo &STI) const;
114
115  // getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch
116  // target operand. If the machine operand requires relocation,
117  // record the relocation and return zero.
118  unsigned getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo,
119                                          SmallVectorImpl<MCFixup> &Fixups,
120                                          const MCSubtargetInfo &STI) const;
121
122  // getBranchTarget7OpValue - Return binary encoding of the microMIPS branch
123  // target operand. If the machine operand requires relocation,
124  // record the relocation and return zero.
125  unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
126                                     SmallVectorImpl<MCFixup> &Fixups,
127                                     const MCSubtargetInfo &STI) const;
128
129  // getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
130  // 10-bit branch target operand. If the machine operand requires relocation,
131  // record the relocation and return zero.
132  unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
133                                        SmallVectorImpl<MCFixup> &Fixups,
134                                        const MCSubtargetInfo &STI) const;
135
136  // getBranchTargetOpValue - Return binary encoding of the microMIPS branch
137  // target operand. If the machine operand requires relocation,
138  // record the relocation and return zero.
139  unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
140                                    SmallVectorImpl<MCFixup> &Fixups,
141                                    const MCSubtargetInfo &STI) const;
142
143  // getBranchTarget21OpValue - Return binary encoding of the branch
144  // offset operand. If the machine operand requires relocation,
145  // record the relocation and return zero.
146  unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
147                                   SmallVectorImpl<MCFixup> &Fixups,
148                                   const MCSubtargetInfo &STI) const;
149
150  // getBranchTarget21OpValueMM - Return binary encoding of the branch
151  // offset operand for microMIPS. If the machine operand requires
152  // relocation,record the relocation and return zero.
153  unsigned getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
154                                      SmallVectorImpl<MCFixup> &Fixups,
155                                      const MCSubtargetInfo &STI) const;
156
157  // getBranchTarget26OpValue - Return binary encoding of the branch
158  // offset operand. If the machine operand requires relocation,
159  // record the relocation and return zero.
160  unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
161                                    SmallVectorImpl<MCFixup> &Fixups,
162                                    const MCSubtargetInfo &STI) const;
163
164  // getBranchTarget26OpValueMM - Return binary encoding of the branch
165  // offset operand. If the machine operand requires relocation,
166  // record the relocation and return zero.
167  unsigned getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo,
168                                      SmallVectorImpl<MCFixup> &Fixups,
169                                      const MCSubtargetInfo &STI) const;
170
171  // getJumpOffset16OpValue - Return binary encoding of the jump
172  // offset operand. If the machine operand requires relocation,
173  // record the relocation and return zero.
174  unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
175                                  SmallVectorImpl<MCFixup> &Fixups,
176                                  const MCSubtargetInfo &STI) const;
177
178  // getMachineOpValue - Return binary encoding of operand. If the machin
179  // operand requires relocation, record the relocation and return zero.
180  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
181                             SmallVectorImpl<MCFixup> &Fixups,
182                             const MCSubtargetInfo &STI) const;
183
184  unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
185                             SmallVectorImpl<MCFixup> &Fixups,
186                             const MCSubtargetInfo &STI) const;
187
188  template <unsigned ShiftAmount = 0>
189  unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
190                          SmallVectorImpl<MCFixup> &Fixups,
191                          const MCSubtargetInfo &STI) const;
192  unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
193                                SmallVectorImpl<MCFixup> &Fixups,
194                                const MCSubtargetInfo &STI) const;
195  unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
196                                    SmallVectorImpl<MCFixup> &Fixups,
197                                    const MCSubtargetInfo &STI) const;
198  unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
199                                    SmallVectorImpl<MCFixup> &Fixups,
200                                    const MCSubtargetInfo &STI) const;
201  unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
202                                      SmallVectorImpl<MCFixup> &Fixups,
203                                      const MCSubtargetInfo &STI) const;
204  unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
205                                      SmallVectorImpl<MCFixup> &Fixups,
206                                      const MCSubtargetInfo &STI) const;
207  unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
208                                SmallVectorImpl<MCFixup> &Fixups,
209                                const MCSubtargetInfo &STI) const;
210  unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
211                                 SmallVectorImpl<MCFixup> &Fixups,
212                                 const MCSubtargetInfo &STI) const;
213  unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
214                                 SmallVectorImpl<MCFixup> &Fixups,
215                                 const MCSubtargetInfo &STI) const;
216  unsigned getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
217                                 SmallVectorImpl<MCFixup> &Fixups,
218                                 const MCSubtargetInfo &STI) const;
219  unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
220                                  SmallVectorImpl<MCFixup> &Fixups,
221                                  const MCSubtargetInfo &STI) const;
222  unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
223                              SmallVectorImpl<MCFixup> &Fixups,
224                              const MCSubtargetInfo &STI) const;
225
226  /// Subtract Offset then encode as a N-bit unsigned integer.
227  template <unsigned Bits, int Offset>
228  unsigned getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo,
229                                     SmallVectorImpl<MCFixup> &Fixups,
230                                     const MCSubtargetInfo &STI) const;
231
232  unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
233                                 SmallVectorImpl<MCFixup> &Fixups,
234                                 const MCSubtargetInfo &STI) const;
235
236  unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
237                                 SmallVectorImpl<MCFixup> &Fixups,
238                                 const MCSubtargetInfo &STI) const;
239
240  unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
241                                SmallVectorImpl<MCFixup> &Fixups,
242                                const MCSubtargetInfo &STI) const;
243  unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo,
244                            SmallVectorImpl<MCFixup> &Fixups,
245                            const MCSubtargetInfo &STI) const;
246
247  unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
248                                  SmallVectorImpl<MCFixup> &Fixups,
249                                  const MCSubtargetInfo &STI) const;
250  unsigned getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
251                                    SmallVectorImpl<MCFixup> &Fixups,
252                                    const MCSubtargetInfo &STI) const;
253
254  unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
255                                 SmallVectorImpl<MCFixup> &Fixups,
256                                 const MCSubtargetInfo &STI) const;
257
258  unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
259                          const MCSubtargetInfo &STI) const;
260
261  unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
262                                  SmallVectorImpl<MCFixup> &Fixups,
263                                  const MCSubtargetInfo &STI) const;
264
265  unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
266                                    SmallVectorImpl<MCFixup> &Fixups,
267                                    const MCSubtargetInfo &STI) const;
268
269private:
270  void LowerCompactBranch(MCInst& Inst) const;
271};
272
273} // end namespace llvm
274
275#endif // LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H
276