1//===- TargetSubtargetInfo.cpp - General Target Information ----------------==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9/// \file This file describes the general parts of a Subtarget. 10// 11//===----------------------------------------------------------------------===// 12 13#include "llvm/CodeGen/TargetSubtargetInfo.h" 14 15using namespace llvm; 16 17TargetSubtargetInfo::TargetSubtargetInfo( 18 const Triple &TT, StringRef CPU, StringRef FS, 19 ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD, 20 const MCWriteProcResEntry *WPR, 21 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, 22 const InstrStage *IS, const unsigned *OC, const unsigned *FP) 23 : MCSubtargetInfo(TT, CPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) { 24} 25 26TargetSubtargetInfo::~TargetSubtargetInfo() = default; 27 28bool TargetSubtargetInfo::enableAtomicExpand() const { 29 return true; 30} 31 32bool TargetSubtargetInfo::enableIndirectBrExpand() const { 33 return false; 34} 35 36bool TargetSubtargetInfo::enableMachineScheduler() const { 37 return false; 38} 39 40bool TargetSubtargetInfo::enableJoinGlobalCopies() const { 41 return enableMachineScheduler(); 42} 43 44bool TargetSubtargetInfo::enableRALocalReassignment( 45 CodeGenOpt::Level OptLevel) const { 46 return true; 47} 48 49bool TargetSubtargetInfo::enableAdvancedRASplitCost() const { 50 return false; 51} 52 53bool TargetSubtargetInfo::enablePostRAScheduler() const { 54 return getSchedModel().PostRAScheduler; 55} 56 57bool TargetSubtargetInfo::enablePostRAMachineScheduler() const { 58 return enableMachineScheduler() && enablePostRAScheduler(); 59} 60 61bool TargetSubtargetInfo::useAA() const { 62 return false; 63} 64 65void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const { } 66