1//===--- ARM.h - Declare ARM target feature support -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares ARM TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H
15
16#include "OSTargets.h"
17#include "clang/Basic/TargetInfo.h"
18#include "clang/Basic/TargetOptions.h"
19#include "llvm/ADT/Triple.h"
20#include "llvm/Support/Compiler.h"
21#include "llvm/Support/TargetParser.h"
22
23namespace clang {
24namespace targets {
25
26class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {
27  // Possible FPU choices.
28  enum FPUMode {
29    VFP2FPU = (1 << 0),
30    VFP3FPU = (1 << 1),
31    VFP4FPU = (1 << 2),
32    NeonFPU = (1 << 3),
33    FPARMV8 = (1 << 4)
34  };
35
36  enum MVEMode {
37      MVE_INT = (1 << 0),
38      MVE_FP  = (1 << 1)
39  };
40
41  // Possible HWDiv features.
42  enum HWDivMode { HWDivThumb = (1 << 0), HWDivARM = (1 << 1) };
43
44  static bool FPUModeIsVFP(FPUMode Mode) {
45    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
46  }
47
48  static const TargetInfo::GCCRegAlias GCCRegAliases[];
49  static const char *const GCCRegNames[];
50
51  std::string ABI, CPU;
52
53  StringRef CPUProfile;
54  StringRef CPUAttr;
55
56  enum { FP_Default, FP_VFP, FP_Neon } FPMath;
57
58  llvm::ARM::ISAKind ArchISA;
59  llvm::ARM::ArchKind ArchKind = llvm::ARM::ArchKind::ARMV4T;
60  llvm::ARM::ProfileKind ArchProfile;
61  unsigned ArchVersion;
62
63  unsigned FPU : 5;
64  unsigned MVE : 2;
65
66  unsigned IsAAPCS : 1;
67  unsigned HWDiv : 2;
68
69  // Initialized via features.
70  unsigned SoftFloat : 1;
71  unsigned SoftFloatABI : 1;
72
73  unsigned CRC : 1;
74  unsigned Crypto : 1;
75  unsigned DSP : 1;
76  unsigned Unaligned : 1;
77  unsigned DotProd : 1;
78
79  enum {
80    LDREX_B = (1 << 0), /// byte (8-bit)
81    LDREX_H = (1 << 1), /// half (16-bit)
82    LDREX_W = (1 << 2), /// word (32-bit)
83    LDREX_D = (1 << 3), /// double (64-bit)
84  };
85
86  uint32_t LDREX;
87
88  // ACLE 6.5.1 Hardware floating point
89  enum {
90    HW_FP_HP = (1 << 1), /// half (16-bit)
91    HW_FP_SP = (1 << 2), /// single (32-bit)
92    HW_FP_DP = (1 << 3), /// double (64-bit)
93  };
94  uint32_t HW_FP;
95
96  static const Builtin::Info BuiltinInfo[];
97
98  void setABIAAPCS();
99  void setABIAPCS(bool IsAAPCS16);
100
101  void setArchInfo();
102  void setArchInfo(llvm::ARM::ArchKind Kind);
103
104  void setAtomic();
105
106  bool isThumb() const;
107  bool supportsThumb() const;
108  bool supportsThumb2() const;
109  bool hasMVE() const;
110  bool hasMVEFloat() const;
111
112  StringRef getCPUAttr() const;
113  StringRef getCPUProfile() const;
114
115public:
116  ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
117
118  StringRef getABI() const override;
119  bool setABI(const std::string &Name) override;
120
121  // FIXME: This should be based on Arch attributes, not CPU names.
122  bool
123  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
124                 StringRef CPU,
125                 const std::vector<std::string> &FeaturesVec) const override;
126
127  bool isValidFeatureName(StringRef Feature) const override {
128    // We pass soft-float-abi in as a -target-feature, but the backend figures
129    // this out through other means.
130    return Feature != "soft-float-abi";
131  }
132
133  bool handleTargetFeatures(std::vector<std::string> &Features,
134                            DiagnosticsEngine &Diags) override;
135
136  bool hasFeature(StringRef Feature) const override;
137
138  bool isValidCPUName(StringRef Name) const override;
139  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
140
141  bool setCPU(const std::string &Name) override;
142
143  bool setFPMath(StringRef Name) override;
144
145  bool useFP16ConversionIntrinsics() const override {
146    return false;
147  }
148
149  void getTargetDefinesARMV81A(const LangOptions &Opts,
150                               MacroBuilder &Builder) const;
151  void getTargetDefinesARMV82A(const LangOptions &Opts,
152                               MacroBuilder &Builder) const;
153  void getTargetDefinesARMV83A(const LangOptions &Opts,
154                                 MacroBuilder &Builder) const;
155  void getTargetDefines(const LangOptions &Opts,
156                        MacroBuilder &Builder) const override;
157
158  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
159
160  bool isCLZForZeroUndef() const override;
161  BuiltinVaListKind getBuiltinVaListKind() const override;
162
163  ArrayRef<const char *> getGCCRegNames() const override;
164  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
165  bool validateAsmConstraint(const char *&Name,
166                             TargetInfo::ConstraintInfo &Info) const override;
167  std::string convertConstraint(const char *&Constraint) const override;
168  bool
169  validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
170                             std::string &SuggestedModifier) const override;
171  const char *getClobbers() const override;
172
173  StringRef getConstraintRegister(StringRef Constraint,
174                                  StringRef Expression) const override {
175    return Expression;
176  }
177
178  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override;
179
180  int getEHDataRegisterNumber(unsigned RegNo) const override;
181
182  bool hasSjLjLowering() const override;
183};
184
185class LLVM_LIBRARY_VISIBILITY ARMleTargetInfo : public ARMTargetInfo {
186public:
187  ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
188  void getTargetDefines(const LangOptions &Opts,
189                        MacroBuilder &Builder) const override;
190};
191
192class LLVM_LIBRARY_VISIBILITY ARMbeTargetInfo : public ARMTargetInfo {
193public:
194  ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
195  void getTargetDefines(const LangOptions &Opts,
196                        MacroBuilder &Builder) const override;
197};
198
199class LLVM_LIBRARY_VISIBILITY WindowsARMTargetInfo
200    : public WindowsTargetInfo<ARMleTargetInfo> {
201  const llvm::Triple Triple;
202
203public:
204  WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
205
206  void getVisualStudioDefines(const LangOptions &Opts,
207                              MacroBuilder &Builder) const;
208
209  BuiltinVaListKind getBuiltinVaListKind() const override;
210
211  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override;
212};
213
214// Windows ARM + Itanium C++ ABI Target
215class LLVM_LIBRARY_VISIBILITY ItaniumWindowsARMleTargetInfo
216    : public WindowsARMTargetInfo {
217public:
218  ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,
219                                const TargetOptions &Opts);
220
221  void getTargetDefines(const LangOptions &Opts,
222                        MacroBuilder &Builder) const override;
223};
224
225// Windows ARM, MS (C++) ABI
226class LLVM_LIBRARY_VISIBILITY MicrosoftARMleTargetInfo
227    : public WindowsARMTargetInfo {
228public:
229  MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
230                           const TargetOptions &Opts);
231
232  void getTargetDefines(const LangOptions &Opts,
233                        MacroBuilder &Builder) const override;
234};
235
236// ARM MinGW target
237class LLVM_LIBRARY_VISIBILITY MinGWARMTargetInfo : public WindowsARMTargetInfo {
238public:
239  MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
240
241  void getTargetDefines(const LangOptions &Opts,
242                        MacroBuilder &Builder) const override;
243};
244
245// ARM Cygwin target
246class LLVM_LIBRARY_VISIBILITY CygwinARMTargetInfo : public ARMleTargetInfo {
247public:
248  CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
249
250  void getTargetDefines(const LangOptions &Opts,
251                        MacroBuilder &Builder) const override;
252};
253
254class LLVM_LIBRARY_VISIBILITY DarwinARMTargetInfo
255    : public DarwinTargetInfo<ARMleTargetInfo> {
256protected:
257  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
258                    MacroBuilder &Builder) const override;
259
260public:
261  DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
262};
263
264// 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes
265class LLVM_LIBRARY_VISIBILITY RenderScript32TargetInfo
266    : public ARMleTargetInfo {
267public:
268  RenderScript32TargetInfo(const llvm::Triple &Triple,
269                           const TargetOptions &Opts);
270
271  void getTargetDefines(const LangOptions &Opts,
272                        MacroBuilder &Builder) const override;
273};
274
275} // namespace targets
276} // namespace clang
277
278#endif // LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H
279