1;; e500 SPE description 2;; Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 3;; Contributed by Aldy Hernandez (aldy@quesejoda.com) 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 2, or (at your 10;; option) any later version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING. If not, write to the 19;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 20;; MA 02110-1301, USA. 21 22(define_constants 23 [(SPE_ACC_REGNO 111) 24 (SPEFSCR_REGNO 112) 25 26 (CMPDFEQ_GPR 1006) 27 (TSTDFEQ_GPR 1007) 28 (CMPDFGT_GPR 1008) 29 (TSTDFGT_GPR 1009) 30 (CMPDFLT_GPR 1010) 31 (TSTDFLT_GPR 1011) 32 (E500_CR_IOR_COMPARE 1012) 33 ]) 34 35;; Modes using a 64-bit register. 36(define_mode_macro SPE64 [DF V4HI V2SF V1DI V2SI]) 37 38(define_insn "*negsf2_gpr" 39 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 40 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] 41 "TARGET_HARD_FLOAT && !TARGET_FPRS" 42 "efsneg %0,%1" 43 [(set_attr "type" "fpsimple")]) 44 45(define_insn "*abssf2_gpr" 46 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 47 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] 48 "TARGET_HARD_FLOAT && !TARGET_FPRS" 49 "efsabs %0,%1" 50 [(set_attr "type" "fpsimple")]) 51 52(define_insn "*nabssf2_gpr" 53 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 54 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))] 55 "TARGET_HARD_FLOAT && !TARGET_FPRS" 56 "efsnabs %0,%1" 57 [(set_attr "type" "fpsimple")]) 58 59(define_insn "*addsf3_gpr" 60 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 61 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r") 62 (match_operand:SF 2 "gpc_reg_operand" "r")))] 63 "TARGET_HARD_FLOAT && !TARGET_FPRS" 64 "efsadd %0,%1,%2" 65 [(set_attr "type" "fp")]) 66 67(define_insn "*subsf3_gpr" 68 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 69 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r") 70 (match_operand:SF 2 "gpc_reg_operand" "r")))] 71 "TARGET_HARD_FLOAT && !TARGET_FPRS" 72 "efssub %0,%1,%2" 73 [(set_attr "type" "fp")]) 74 75(define_insn "*mulsf3_gpr" 76 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 77 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r") 78 (match_operand:SF 2 "gpc_reg_operand" "r")))] 79 "TARGET_HARD_FLOAT && !TARGET_FPRS" 80 "efsmul %0,%1,%2" 81 [(set_attr "type" "fp")]) 82 83(define_insn "*divsf3_gpr" 84 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 85 (div:SF (match_operand:SF 1 "gpc_reg_operand" "r") 86 (match_operand:SF 2 "gpc_reg_operand" "r")))] 87 "TARGET_HARD_FLOAT && !TARGET_FPRS" 88 "efsdiv %0,%1,%2" 89 [(set_attr "type" "vecfdiv")]) 90 91;; Floating point conversion instructions. 92 93(define_insn "fixuns_truncdfsi2" 94 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 95 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))] 96 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 97 "efdctuiz %0,%1" 98 [(set_attr "type" "fp")]) 99 100(define_insn "spe_extendsfdf2" 101 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") 102 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))] 103 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 104 "efdcfs %0,%1" 105 [(set_attr "type" "fp")]) 106 107(define_insn "spe_fixuns_truncsfsi2" 108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 109 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))] 110 "TARGET_HARD_FLOAT && !TARGET_FPRS" 111 "efsctuiz %0,%1" 112 [(set_attr "type" "fp")]) 113 114(define_insn "spe_fix_truncsfsi2" 115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 116 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))] 117 "TARGET_HARD_FLOAT && !TARGET_FPRS" 118 "efsctsiz %0,%1" 119 [(set_attr "type" "fp")]) 120 121(define_insn "spe_fix_truncdfsi2" 122 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 123 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))] 124 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 125 "efdctsiz %0,%1" 126 [(set_attr "type" "fp")]) 127 128(define_insn "spe_floatunssisf2" 129 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 130 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] 131 "TARGET_HARD_FLOAT && !TARGET_FPRS" 132 "efscfui %0,%1" 133 [(set_attr "type" "fp")]) 134 135(define_insn "spe_floatunssidf2" 136 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") 137 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] 138 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 139 "efdcfui %0,%1" 140 [(set_attr "type" "fp")]) 141 142(define_insn "spe_floatsisf2" 143 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 144 (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] 145 "TARGET_HARD_FLOAT && !TARGET_FPRS" 146 "efscfsi %0,%1" 147 [(set_attr "type" "fp")]) 148 149(define_insn "spe_floatsidf2" 150 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") 151 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] 152 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 153 "efdcfsi %0,%1" 154 [(set_attr "type" "fp")]) 155 156;; SPE SIMD instructions 157 158(define_insn "spe_evabs" 159 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 160 (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] 161 "TARGET_SPE" 162 "evabs %0,%1" 163 [(set_attr "type" "vecsimple") 164 (set_attr "length" "4")]) 165 166(define_insn "spe_evandc" 167 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 168 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 169 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] 170 "TARGET_SPE" 171 "evandc %0,%1,%2" 172 [(set_attr "type" "vecsimple") 173 (set_attr "length" "4")]) 174 175(define_insn "spe_evand" 176 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 177 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 178 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] 179 "TARGET_SPE" 180 "evand %0,%1,%2" 181 [(set_attr "type" "vecsimple") 182 (set_attr "length" "4")]) 183 184;; Vector compare instructions 185 186(define_insn "spe_evcmpeq" 187 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 188 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") 189 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))] 190 "TARGET_SPE" 191 "evcmpeq %0,%1,%2" 192 [(set_attr "type" "veccmp") 193 (set_attr "length" "4")]) 194 195(define_insn "spe_evcmpgts" 196 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 197 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") 198 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))] 199 "TARGET_SPE" 200 "evcmpgts %0,%1,%2" 201 [(set_attr "type" "veccmp") 202 (set_attr "length" "4")]) 203 204(define_insn "spe_evcmpgtu" 205 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 206 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") 207 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))] 208 "TARGET_SPE" 209 "evcmpgtu %0,%1,%2" 210 [(set_attr "type" "veccmp") 211 (set_attr "length" "4")]) 212 213(define_insn "spe_evcmplts" 214 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 215 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") 216 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))] 217 "TARGET_SPE" 218 "evcmplts %0,%1,%2" 219 [(set_attr "type" "veccmp") 220 (set_attr "length" "4")]) 221 222(define_insn "spe_evcmpltu" 223 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 224 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") 225 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))] 226 "TARGET_SPE" 227 "evcmpltu %0,%1,%2" 228 [(set_attr "type" "veccmp") 229 (set_attr "length" "4")]) 230 231;; Floating point vector compare instructions 232 233(define_insn "spe_evfscmpeq" 234 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 235 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") 236 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538)) 237 (clobber (reg:SI SPEFSCR_REGNO))] 238 "TARGET_SPE" 239 "evfscmpeq %0,%1,%2" 240 [(set_attr "type" "veccmp") 241 (set_attr "length" "4")]) 242 243(define_insn "spe_evfscmpgt" 244 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 245 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") 246 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539)) 247 (clobber (reg:SI SPEFSCR_REGNO))] 248 "TARGET_SPE" 249 "evfscmpgt %0,%1,%2" 250 [(set_attr "type" "veccmp") 251 (set_attr "length" "4")]) 252 253(define_insn "spe_evfscmplt" 254 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 255 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") 256 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540)) 257 (clobber (reg:SI SPEFSCR_REGNO))] 258 "TARGET_SPE" 259 "evfscmplt %0,%1,%2" 260 [(set_attr "type" "veccmp") 261 (set_attr "length" "4")]) 262 263(define_insn "spe_evfststeq" 264 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 265 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") 266 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))] 267 "TARGET_SPE" 268 "evfststeq %0,%1,%2" 269 [(set_attr "type" "veccmp") 270 (set_attr "length" "4")]) 271 272(define_insn "spe_evfststgt" 273 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 274 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") 275 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))] 276 "TARGET_SPE" 277 "evfststgt %0,%1,%2" 278 [(set_attr "type" "veccmp") 279 (set_attr "length" "4")]) 280 281(define_insn "spe_evfststlt" 282 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 283 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") 284 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))] 285 "TARGET_SPE" 286 "evfststlt %0,%1,%2" 287 [(set_attr "type" "veccmp") 288 (set_attr "length" "4")]) 289 290;; End of vector compare instructions 291 292(define_insn "spe_evcntlsw" 293 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 294 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))] 295 "TARGET_SPE" 296 "evcntlsw %0,%1" 297 [(set_attr "type" "vecsimple") 298 (set_attr "length" "4")]) 299 300(define_insn "spe_evcntlzw" 301 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 302 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))] 303 "TARGET_SPE" 304 "evcntlzw %0,%1" 305 [(set_attr "type" "vecsimple") 306 (set_attr "length" "4")]) 307 308(define_insn "spe_eveqv" 309 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 310 (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 311 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] 312 "TARGET_SPE" 313 "eveqv %0,%1,%2" 314 [(set_attr "type" "vecsimple") 315 (set_attr "length" "4")]) 316 317(define_insn "spe_evextsb" 318 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 319 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))] 320 "TARGET_SPE" 321 "evextsb %0,%1" 322 [(set_attr "type" "vecsimple") 323 (set_attr "length" "4")]) 324 325(define_insn "spe_evextsh" 326 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 327 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))] 328 "TARGET_SPE" 329 "evextsh %0,%1" 330 [(set_attr "type" "vecsimple") 331 (set_attr "length" "4")]) 332 333(define_insn "spe_evlhhesplat" 334 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 335 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 336 (match_operand:QI 2 "immediate_operand" "i")))) 337 (unspec [(const_int 0)] 509)] 338 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" 339 "evlhhesplat %0,%2*2(%1)" 340 [(set_attr "type" "vecload") 341 (set_attr "length" "4")]) 342 343(define_insn "spe_evlhhesplatx" 344 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 345 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 346 (match_operand:SI 2 "gpc_reg_operand" "r")))) 347 (unspec [(const_int 0)] 510)] 348 "TARGET_SPE" 349 "evlhhesplatx %0,%1,%2" 350 [(set_attr "type" "vecload") 351 (set_attr "length" "4")]) 352 353(define_insn "spe_evlhhossplat" 354 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 355 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 356 (match_operand:QI 2 "immediate_operand" "i")))) 357 (unspec [(const_int 0)] 511)] 358 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" 359 "evlhhossplat %0,%2*2(%1)" 360 [(set_attr "type" "vecload") 361 (set_attr "length" "4")]) 362 363(define_insn "spe_evlhhossplatx" 364 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 365 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 366 (match_operand:SI 2 "gpc_reg_operand" "r")))) 367 (unspec [(const_int 0)] 512)] 368 "TARGET_SPE" 369 "evlhhossplatx %0,%1,%2" 370 [(set_attr "type" "vecload") 371 (set_attr "length" "4")]) 372 373(define_insn "spe_evlhhousplat" 374 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 375 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 376 (match_operand:QI 2 "immediate_operand" "i")))) 377 (unspec [(const_int 0)] 513)] 378 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" 379 "evlhhousplat %0,%2*2(%1)" 380 [(set_attr "type" "vecload") 381 (set_attr "length" "4")]) 382 383(define_insn "spe_evlhhousplatx" 384 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 385 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 386 (match_operand:SI 2 "gpc_reg_operand" "r")))) 387 (unspec [(const_int 0)] 514)] 388 "TARGET_SPE" 389 "evlhhousplatx %0,%1,%2" 390 [(set_attr "type" "vecload") 391 (set_attr "length" "4")]) 392 393(define_insn "spe_evlwhsplat" 394 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 395 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 396 (match_operand:QI 2 "immediate_operand" "i")))) 397 (unspec [(const_int 0)] 515)] 398 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" 399 "evlwhsplat %0,%2*4(%1)" 400 [(set_attr "type" "vecload") 401 (set_attr "length" "4")]) 402 403(define_insn "spe_evlwhsplatx" 404 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 405 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 406 (match_operand:SI 2 "gpc_reg_operand" "r")))) 407 (unspec [(const_int 0)] 516)] 408 "TARGET_SPE" 409 "evlwhsplatx %0,%1,%2" 410 [(set_attr "type" "vecload") 411 (set_attr "length" "4")]) 412 413(define_insn "spe_evlwwsplat" 414 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 415 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 416 (match_operand:QI 2 "immediate_operand" "i")))) 417 (unspec [(const_int 0)] 517)] 418 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" 419 "evlwwsplat %0,%2*4(%1)" 420 [(set_attr "type" "vecload") 421 (set_attr "length" "4")]) 422 423(define_insn "spe_evlwwsplatx" 424 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 425 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 426 (match_operand:SI 2 "gpc_reg_operand" "r")))) 427 (unspec [(const_int 0)] 518)] 428 "TARGET_SPE" 429 "evlwwsplatx %0,%1,%2" 430 [(set_attr "type" "vecload") 431 (set_attr "length" "4")]) 432 433(define_insn "spe_evmergehi" 434 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 435 (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 436 (vec_select:V2SI 437 (match_operand:V2SI 2 "gpc_reg_operand" "r") 438 (parallel [(const_int 1) 439 (const_int 0)])) 440 (const_int 2)))] 441 "TARGET_SPE" 442 "evmergehi %0,%1,%2" 443 [(set_attr "type" "vecsimple") 444 (set_attr "length" "4")]) 445 446(define_insn "spe_evmergehilo" 447 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 448 (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 449 (match_operand:V2SI 2 "gpc_reg_operand" "r") 450 (const_int 2)))] 451 "TARGET_SPE" 452 "evmergehilo %0,%1,%2" 453 [(set_attr "type" "vecsimple") 454 (set_attr "length" "4")]) 455 456(define_insn "spe_evmergelo" 457 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 458 (vec_merge:V2SI (vec_select:V2SI 459 (match_operand:V2SI 1 "gpc_reg_operand" "r") 460 (parallel [(const_int 1) 461 (const_int 0)])) 462 (match_operand:V2SI 2 "gpc_reg_operand" "r") 463 (const_int 2)))] 464 "TARGET_SPE" 465 "evmergelo %0,%1,%2" 466 [(set_attr "type" "vecsimple") 467 (set_attr "length" "4")]) 468 469(define_insn "spe_evmergelohi" 470 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 471 (vec_merge:V2SI (vec_select:V2SI 472 (match_operand:V2SI 1 "gpc_reg_operand" "r") 473 (parallel [(const_int 1) 474 (const_int 0)])) 475 (vec_select:V2SI 476 (match_operand:V2SI 2 "gpc_reg_operand" "r") 477 (parallel [(const_int 1) 478 (const_int 0)])) 479 (const_int 2)))] 480 "TARGET_SPE" 481 "evmergelohi %0,%1,%2" 482 [(set_attr "type" "vecsimple") 483 (set_attr "length" "4")]) 484 485(define_insn "spe_evnand" 486 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 487 (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 488 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] 489 "TARGET_SPE" 490 "evnand %0,%1,%2" 491 [(set_attr "type" "vecsimple") 492 (set_attr "length" "4")]) 493 494(define_insn "negv2si2" 495 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 496 (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] 497 "TARGET_SPE" 498 "evneg %0,%1" 499 [(set_attr "type" "vecsimple") 500 (set_attr "length" "4")]) 501 502(define_insn "spe_evnor" 503 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 504 (not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 505 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] 506 "TARGET_SPE" 507 "evnor %0,%1,%2" 508 [(set_attr "type" "vecsimple") 509 (set_attr "length" "4")]) 510 511(define_insn "spe_evorc" 512 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 513 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 514 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] 515 "TARGET_SPE" 516 "evorc %0,%1,%2" 517 [(set_attr "type" "vecsimple") 518 (set_attr "length" "4")]) 519 520(define_insn "spe_evor" 521 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 522 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 523 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] 524 "TARGET_SPE" 525 "evor %0,%1,%2" 526 [(set_attr "type" "vecsimple") 527 (set_attr "length" "4")]) 528 529(define_insn "spe_evrlwi" 530 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 531 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 532 (match_operand:QI 2 "immediate_operand" "i")] 519))] 533 "TARGET_SPE" 534 "evrlwi %0,%1,%2" 535 [(set_attr "type" "vecsimple") 536 (set_attr "length" "4")]) 537 538(define_insn "spe_evrlw" 539 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 540 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 541 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))] 542 "TARGET_SPE" 543 "evrlw %0,%1,%2" 544 [(set_attr "type" "veccomplex") 545 (set_attr "length" "4")]) 546 547(define_insn "spe_evrndw" 548 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 549 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))] 550 "TARGET_SPE" 551 "evrndw %0,%1" 552 [(set_attr "type" "vecsimple") 553 (set_attr "length" "4")]) 554 555(define_insn "spe_evsel" 556 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 557 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 558 (match_operand:V2SI 2 "gpc_reg_operand" "r") 559 (match_operand:CC 3 "cc_reg_operand" "y")] 522))] 560 "TARGET_SPE" 561 "evsel %0,%1,%2,%3" 562 [(set_attr "type" "veccmp") 563 (set_attr "length" "4")]) 564 565(define_insn "spe_evsel_fs" 566 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 567 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r") 568 (match_operand:V2SF 2 "gpc_reg_operand" "r") 569 (match_operand:CC 3 "cc_reg_operand" "y")] 725))] 570 "TARGET_SPE" 571 "evsel %0,%1,%2,%3" 572 [(set_attr "type" "veccmp") 573 (set_attr "length" "4")]) 574 575(define_insn "spe_evslwi" 576 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 577 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 578 (match_operand:QI 2 "immediate_operand" "i")] 579 523))] 580 "TARGET_SPE" 581 "evslwi %0,%1,%2" 582 [(set_attr "type" "vecsimple") 583 (set_attr "length" "4")]) 584 585(define_insn "spe_evslw" 586 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 587 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 588 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))] 589 "TARGET_SPE" 590 "evslw %0,%1,%2" 591 [(set_attr "type" "vecsimple") 592 (set_attr "length" "4")]) 593 594(define_insn "spe_evsrwis" 595 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 596 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 597 (match_operand:QI 2 "immediate_operand" "i")] 598 525))] 599 "TARGET_SPE" 600 "evsrwis %0,%1,%2" 601 [(set_attr "type" "vecsimple") 602 (set_attr "length" "4")]) 603 604(define_insn "spe_evsrwiu" 605 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 606 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 607 (match_operand:QI 2 "immediate_operand" "i")] 608 526))] 609 "TARGET_SPE" 610 "evsrwiu %0,%1,%2" 611 [(set_attr "type" "vecsimple") 612 (set_attr "length" "4")]) 613 614(define_insn "spe_evsrws" 615 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 616 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 617 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))] 618 "TARGET_SPE" 619 "evsrws %0,%1,%2" 620 [(set_attr "type" "vecsimple") 621 (set_attr "length" "4")]) 622 623(define_insn "spe_evsrwu" 624 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 625 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 626 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))] 627 "TARGET_SPE" 628 "evsrwu %0,%1,%2" 629 [(set_attr "type" "vecsimple") 630 (set_attr "length" "4")]) 631 632;; vector xors 633 634(define_insn "xorv2si3" 635 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 636 (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 637 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] 638 "TARGET_SPE" 639 "evxor %0,%1,%2" 640 [(set_attr "type" "vecsimple") 641 (set_attr "length" "4")]) 642 643(define_insn "xorv4hi3" 644 [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r") 645 (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r") 646 (match_operand:V4HI 2 "gpc_reg_operand" "r")))] 647 "TARGET_SPE" 648 "evxor %0,%1,%2" 649 [(set_attr "type" "vecsimple") 650 (set_attr "length" "4")]) 651 652(define_insn "xorv1di3" 653 [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r") 654 (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r") 655 (match_operand:V1DI 2 "gpc_reg_operand" "r")))] 656 "TARGET_SPE" 657 "evxor %0,%1,%2" 658 [(set_attr "type" "vecsimple") 659 (set_attr "length" "4")]) 660 661;; end of vector xors 662 663(define_insn "spe_evfsabs" 664 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 665 (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] 666 "TARGET_SPE" 667 "evfsabs %0,%1" 668 [(set_attr "type" "vecsimple") 669 (set_attr "length" "4")]) 670 671(define_insn "spe_evfsadd" 672 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 673 (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") 674 (match_operand:V2SF 2 "gpc_reg_operand" "r"))) 675 (clobber (reg:SI SPEFSCR_REGNO))] 676 "TARGET_SPE" 677 "evfsadd %0,%1,%2" 678 [(set_attr "type" "vecfloat") 679 (set_attr "length" "4")]) 680 681(define_insn "spe_evfscfsf" 682 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 683 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))] 684 "TARGET_SPE" 685 "evfscfsf %0,%1" 686 [(set_attr "type" "vecfloat") 687 (set_attr "length" "4")]) 688 689(define_insn "spe_evfscfsi" 690 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 691 (float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))] 692 "TARGET_SPE" 693 "evfscfsi %0,%1" 694 [(set_attr "type" "vecfloat") 695 (set_attr "length" "4")]) 696 697(define_insn "spe_evfscfuf" 698 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 699 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))] 700 "TARGET_SPE" 701 "evfscfuf %0,%1" 702 [(set_attr "type" "vecfloat") 703 (set_attr "length" "4")]) 704 705(define_insn "spe_evfscfui" 706 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 707 (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))] 708 "TARGET_SPE" 709 "evfscfui %0,%1" 710 [(set_attr "type" "vecfloat") 711 (set_attr "length" "4")]) 712 713(define_insn "spe_evfsctsf" 714 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 715 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))] 716 "TARGET_SPE" 717 "evfsctsf %0,%1" 718 [(set_attr "type" "vecfloat") 719 (set_attr "length" "4")]) 720 721(define_insn "spe_evfsctsi" 722 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 723 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))] 724 "TARGET_SPE" 725 "evfsctsi %0,%1" 726 [(set_attr "type" "vecfloat") 727 (set_attr "length" "4")]) 728 729(define_insn "spe_evfsctsiz" 730 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 731 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))] 732 "TARGET_SPE" 733 "evfsctsiz %0,%1" 734 [(set_attr "type" "vecfloat") 735 (set_attr "length" "4")]) 736 737(define_insn "spe_evfsctuf" 738 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 739 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))] 740 "TARGET_SPE" 741 "evfsctuf %0,%1" 742 [(set_attr "type" "vecfloat") 743 (set_attr "length" "4")]) 744 745(define_insn "spe_evfsctui" 746 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 747 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))] 748 "TARGET_SPE" 749 "evfsctui %0,%1" 750 [(set_attr "type" "vecfloat") 751 (set_attr "length" "4")]) 752 753(define_insn "spe_evfsctuiz" 754 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 755 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))] 756 "TARGET_SPE" 757 "evfsctuiz %0,%1" 758 [(set_attr "type" "vecfloat") 759 (set_attr "length" "4")]) 760 761(define_insn "spe_evfsdiv" 762 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 763 (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") 764 (match_operand:V2SF 2 "gpc_reg_operand" "r"))) 765 (clobber (reg:SI SPEFSCR_REGNO))] 766 "TARGET_SPE" 767 "evfsdiv %0,%1,%2" 768 [(set_attr "type" "vecfdiv") 769 (set_attr "length" "4")]) 770 771(define_insn "spe_evfsmul" 772 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 773 (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") 774 (match_operand:V2SF 2 "gpc_reg_operand" "r"))) 775 (clobber (reg:SI SPEFSCR_REGNO))] 776 "TARGET_SPE" 777 "evfsmul %0,%1,%2" 778 [(set_attr "type" "vecfloat") 779 (set_attr "length" "4")]) 780 781(define_insn "spe_evfsnabs" 782 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 783 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))] 784 "TARGET_SPE" 785 "evfsnabs %0,%1" 786 [(set_attr "type" "vecsimple") 787 (set_attr "length" "4")]) 788 789(define_insn "spe_evfsneg" 790 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 791 (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] 792 "TARGET_SPE" 793 "evfsneg %0,%1" 794 [(set_attr "type" "vecsimple") 795 (set_attr "length" "4")]) 796 797(define_insn "spe_evfssub" 798 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 799 (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") 800 (match_operand:V2SF 2 "gpc_reg_operand" "r"))) 801 (clobber (reg:SI SPEFSCR_REGNO))] 802 "TARGET_SPE" 803 "evfssub %0,%1,%2" 804 [(set_attr "type" "vecfloat") 805 (set_attr "length" "4")]) 806 807;; SPE SIMD load instructions. 808 809;; Only the hardware engineer who designed the SPE understands the 810;; plethora of load and store instructions ;-). We have no way of 811;; differentiating between them with RTL so use an unspec of const_int 0 812;; to avoid identical RTL. 813 814(define_insn "spe_evldd" 815 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 816 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 817 (match_operand:QI 2 "immediate_operand" "i")))) 818 (unspec [(const_int 0)] 544)] 819 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" 820 "evldd %0,%2*8(%1)" 821 [(set_attr "type" "vecload") 822 (set_attr "length" "4")]) 823 824(define_insn "spe_evlddx" 825 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 826 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 827 (match_operand:SI 2 "gpc_reg_operand" "r")))) 828 (unspec [(const_int 0)] 545)] 829 "TARGET_SPE" 830 "evlddx %0,%1,%2" 831 [(set_attr "type" "vecload") 832 (set_attr "length" "4")]) 833 834(define_insn "spe_evldh" 835 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 836 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 837 (match_operand:QI 2 "immediate_operand" "i")))) 838 (unspec [(const_int 0)] 546)] 839 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" 840 "evldh %0,%2*8(%1)" 841 [(set_attr "type" "vecload") 842 (set_attr "length" "4")]) 843 844(define_insn "spe_evldhx" 845 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 846 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 847 (match_operand:SI 2 "gpc_reg_operand" "r")))) 848 (unspec [(const_int 0)] 547)] 849 "TARGET_SPE" 850 "evldhx %0,%1,%2" 851 [(set_attr "type" "vecload") 852 (set_attr "length" "4")]) 853 854(define_insn "spe_evldw" 855 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 856 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 857 (match_operand:QI 2 "immediate_operand" "i")))) 858 (unspec [(const_int 0)] 548)] 859 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" 860 "evldw %0,%2*8(%1)" 861 [(set_attr "type" "vecload") 862 (set_attr "length" "4")]) 863 864(define_insn "spe_evldwx" 865 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 866 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 867 (match_operand:SI 2 "gpc_reg_operand" "r")))) 868 (unspec [(const_int 0)] 549)] 869 "TARGET_SPE" 870 "evldwx %0,%1,%2" 871 [(set_attr "type" "vecload") 872 (set_attr "length" "4")]) 873 874(define_insn "spe_evlwhe" 875 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 876 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 877 (match_operand:QI 2 "immediate_operand" "i")))) 878 (unspec [(const_int 0)] 550)] 879 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" 880 "evlwhe %0,%2*4(%1)" 881 [(set_attr "type" "vecload") 882 (set_attr "length" "4")]) 883 884(define_insn "spe_evlwhex" 885 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 886 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 887 (match_operand:SI 2 "gpc_reg_operand" "r")))) 888 (unspec [(const_int 0)] 551)] 889 "TARGET_SPE" 890 "evlwhex %0,%1,%2" 891 [(set_attr "type" "vecload") 892 (set_attr "length" "4")]) 893 894(define_insn "spe_evlwhos" 895 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 896 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 897 (match_operand:QI 2 "immediate_operand" "i")))) 898 (unspec [(const_int 0)] 552)] 899 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" 900 "evlwhos %0,%2*4(%1)" 901 [(set_attr "type" "vecload") 902 (set_attr "length" "4")]) 903 904(define_insn "spe_evlwhosx" 905 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 906 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 907 (match_operand:SI 2 "gpc_reg_operand" "r")))) 908 (unspec [(const_int 0)] 553)] 909 "TARGET_SPE" 910 "evlwhosx %0,%1,%2" 911 [(set_attr "type" "vecload") 912 (set_attr "length" "4")]) 913 914(define_insn "spe_evlwhou" 915 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 916 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 917 (match_operand:QI 2 "immediate_operand" "i")))) 918 (unspec [(const_int 0)] 554)] 919 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" 920 "evlwhou %0,%2*4(%1)" 921 [(set_attr "type" "vecload") 922 (set_attr "length" "4")]) 923 924(define_insn "spe_evlwhoux" 925 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 926 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 927 (match_operand:SI 2 "gpc_reg_operand" "r")))) 928 (unspec [(const_int 0)] 555)] 929 "TARGET_SPE" 930 "evlwhoux %0,%1,%2" 931 [(set_attr "type" "vecload") 932 (set_attr "length" "4")]) 933 934(define_insn "spe_brinc" 935 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 936 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r") 937 (match_operand:SI 2 "gpc_reg_operand" "r")] 556))] 938 "TARGET_SPE" 939 "brinc %0,%1,%2" 940 [(set_attr "type" "brinc") 941 (set_attr "length" "4")]) 942 943(define_insn "spe_evmhegsmfaa" 944 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 945 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 946 (match_operand:V2SI 2 "gpc_reg_operand" "r") 947 (reg:V2SI SPE_ACC_REGNO)] 557)) 948 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 949 "TARGET_SPE" 950 "evmhegsmfaa %0,%1,%2" 951 [(set_attr "type" "veccomplex") 952 (set_attr "length" "4")]) 953 954(define_insn "spe_evmhegsmfan" 955 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 956 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 957 (match_operand:V2SI 2 "gpc_reg_operand" "r") 958 (reg:V2SI SPE_ACC_REGNO)] 558)) 959 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 960 "TARGET_SPE" 961 "evmhegsmfan %0,%1,%2" 962 [(set_attr "type" "veccomplex") 963 (set_attr "length" "4")]) 964 965(define_insn "spe_evmhegsmiaa" 966 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 967 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 968 (match_operand:V2SI 2 "gpc_reg_operand" "r") 969 (reg:V2SI SPE_ACC_REGNO)] 559)) 970 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 971 "TARGET_SPE" 972 "evmhegsmiaa %0,%1,%2" 973 [(set_attr "type" "veccomplex") 974 (set_attr "length" "4")]) 975 976(define_insn "spe_evmhegsmian" 977 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 978 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 979 (match_operand:V2SI 2 "gpc_reg_operand" "r") 980 (reg:V2SI SPE_ACC_REGNO)] 560)) 981 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 982 "TARGET_SPE" 983 "evmhegsmian %0,%1,%2" 984 [(set_attr "type" "veccomplex") 985 (set_attr "length" "4")]) 986 987(define_insn "spe_evmhegumiaa" 988 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 989 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 990 (match_operand:V2SI 2 "gpc_reg_operand" "r") 991 (reg:V2SI SPE_ACC_REGNO)] 561)) 992 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 993 "TARGET_SPE" 994 "evmhegumiaa %0,%1,%2" 995 [(set_attr "type" "veccomplex") 996 (set_attr "length" "4")]) 997 998(define_insn "spe_evmhegumian" 999 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1000 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1001 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1002 (reg:V2SI SPE_ACC_REGNO)] 562)) 1003 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1004 "TARGET_SPE" 1005 "evmhegumian %0,%1,%2" 1006 [(set_attr "type" "veccomplex") 1007 (set_attr "length" "4")]) 1008 1009(define_insn "spe_evmhesmfaaw" 1010 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1011 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1012 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1013 (reg:V2SI SPE_ACC_REGNO)] 563)) 1014 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1015 "TARGET_SPE" 1016 "evmhesmfaaw %0,%1,%2" 1017 [(set_attr "type" "veccomplex") 1018 (set_attr "length" "4")]) 1019 1020(define_insn "spe_evmhesmfanw" 1021 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1022 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1023 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1024 (reg:V2SI SPE_ACC_REGNO)] 564)) 1025 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1026 "TARGET_SPE" 1027 "evmhesmfanw %0,%1,%2" 1028 [(set_attr "type" "veccomplex") 1029 (set_attr "length" "4")]) 1030 1031(define_insn "spe_evmhesmfa" 1032 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1033 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1034 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565)) 1035 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1036 "TARGET_SPE" 1037 "evmhesmfa %0,%1,%2" 1038 [(set_attr "type" "veccomplex") 1039 (set_attr "length" "4")]) 1040 1041(define_insn "spe_evmhesmf" 1042 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1043 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1044 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))] 1045 "TARGET_SPE" 1046 "evmhesmf %0,%1,%2" 1047 [(set_attr "type" "veccomplex") 1048 (set_attr "length" "4")]) 1049 1050(define_insn "spe_evmhesmiaaw" 1051 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1052 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1053 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1054 (reg:V2SI SPE_ACC_REGNO)] 567)) 1055 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1056 "TARGET_SPE" 1057 "evmhesmiaaw %0,%1,%2" 1058 [(set_attr "type" "veccomplex") 1059 (set_attr "length" "4")]) 1060 1061(define_insn "spe_evmhesmianw" 1062 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1063 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1064 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1065 (reg:V2SI SPE_ACC_REGNO)] 568)) 1066 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1067 "TARGET_SPE" 1068 "evmhesmianw %0,%1,%2" 1069 [(set_attr "type" "veccomplex") 1070 (set_attr "length" "4")]) 1071 1072(define_insn "spe_evmhesmia" 1073 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1074 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1075 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569)) 1076 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1077 "TARGET_SPE" 1078 "evmhesmia %0,%1,%2" 1079 [(set_attr "type" "veccomplex") 1080 (set_attr "length" "4")]) 1081 1082(define_insn "spe_evmhesmi" 1083 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1084 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1085 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))] 1086 "TARGET_SPE" 1087 "evmhesmi %0,%1,%2" 1088 [(set_attr "type" "veccomplex") 1089 (set_attr "length" "4")]) 1090 1091(define_insn "spe_evmhessfaaw" 1092 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1093 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1094 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1095 (reg:V2SI SPE_ACC_REGNO)] 571)) 1096 (clobber (reg:SI SPEFSCR_REGNO)) 1097 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1098 "TARGET_SPE" 1099 "evmhessfaaw %0,%1,%2" 1100 [(set_attr "type" "veccomplex") 1101 (set_attr "length" "4")]) 1102 1103(define_insn "spe_evmhessfanw" 1104 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1105 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1106 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1107 (reg:V2SI SPE_ACC_REGNO)] 572)) 1108 (clobber (reg:SI SPEFSCR_REGNO)) 1109 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1110 "TARGET_SPE" 1111 "evmhessfanw %0,%1,%2" 1112 [(set_attr "type" "veccomplex") 1113 (set_attr "length" "4")]) 1114 1115(define_insn "spe_evmhessfa" 1116 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1117 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1118 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573)) 1119 (clobber (reg:SI SPEFSCR_REGNO)) 1120 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1121 "TARGET_SPE" 1122 "evmhessfa %0,%1,%2" 1123 [(set_attr "type" "veccomplex") 1124 (set_attr "length" "4")]) 1125 1126(define_insn "spe_evmhessf" 1127 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1128 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1129 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574)) 1130 (clobber (reg:SI SPEFSCR_REGNO))] 1131 "TARGET_SPE" 1132 "evmhessf %0,%1,%2" 1133 [(set_attr "type" "veccomplex") 1134 (set_attr "length" "4")]) 1135 1136(define_insn "spe_evmhessiaaw" 1137 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1138 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1139 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1140 (reg:V2SI SPE_ACC_REGNO)] 575)) 1141 (clobber (reg:SI SPEFSCR_REGNO)) 1142 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1143 "TARGET_SPE" 1144 "evmhessiaaw %0,%1,%2" 1145 [(set_attr "type" "veccomplex") 1146 (set_attr "length" "4")]) 1147 1148(define_insn "spe_evmhessianw" 1149 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1150 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1151 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1152 (reg:V2SI SPE_ACC_REGNO)] 576)) 1153 (clobber (reg:SI SPEFSCR_REGNO)) 1154 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1155 "TARGET_SPE" 1156 "evmhessianw %0,%1,%2" 1157 [(set_attr "type" "veccomplex") 1158 (set_attr "length" "4")]) 1159 1160(define_insn "spe_evmheumiaaw" 1161 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1162 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1163 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1164 (reg:V2SI SPE_ACC_REGNO)] 577)) 1165 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1166 "TARGET_SPE" 1167 "evmheumiaaw %0,%1,%2" 1168 [(set_attr "type" "veccomplex") 1169 (set_attr "length" "4")]) 1170 1171(define_insn "spe_evmheumianw" 1172 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1173 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1174 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1175 (reg:V2SI SPE_ACC_REGNO)] 578)) 1176 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1177 "TARGET_SPE" 1178 "evmheumianw %0,%1,%2" 1179 [(set_attr "type" "veccomplex") 1180 (set_attr "length" "4")]) 1181 1182(define_insn "spe_evmheumia" 1183 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1184 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1185 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579)) 1186 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1187 "TARGET_SPE" 1188 "evmheumia %0,%1,%2" 1189 [(set_attr "type" "veccomplex") 1190 (set_attr "length" "4")]) 1191 1192(define_insn "spe_evmheumi" 1193 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1194 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1195 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))] 1196 "TARGET_SPE" 1197 "evmheumi %0,%1,%2" 1198 [(set_attr "type" "veccomplex") 1199 (set_attr "length" "4")]) 1200 1201(define_insn "spe_evmheusiaaw" 1202 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1203 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1204 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1205 (reg:V2SI SPE_ACC_REGNO)] 581)) 1206 (clobber (reg:SI SPEFSCR_REGNO)) 1207 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1208 "TARGET_SPE" 1209 "evmheusiaaw %0,%1,%2" 1210 [(set_attr "type" "veccomplex") 1211 (set_attr "length" "4")]) 1212 1213(define_insn "spe_evmheusianw" 1214 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1215 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1216 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1217 (reg:V2SI SPE_ACC_REGNO)] 582)) 1218 (clobber (reg:SI SPEFSCR_REGNO)) 1219 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1220 "TARGET_SPE" 1221 "evmheusianw %0,%1,%2" 1222 [(set_attr "type" "veccomplex") 1223 (set_attr "length" "4")]) 1224 1225(define_insn "spe_evmhogsmfaa" 1226 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1227 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1228 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1229 (reg:V2SI SPE_ACC_REGNO)] 583)) 1230 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1231 "TARGET_SPE" 1232 "evmhogsmfaa %0,%1,%2" 1233 [(set_attr "type" "veccomplex") 1234 (set_attr "length" "4")]) 1235 1236(define_insn "spe_evmhogsmfan" 1237 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1238 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1239 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1240 (reg:V2SI SPE_ACC_REGNO)] 584)) 1241 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1242 "TARGET_SPE" 1243 "evmhogsmfan %0,%1,%2" 1244 [(set_attr "type" "veccomplex") 1245 (set_attr "length" "4")]) 1246 1247(define_insn "spe_evmhogsmiaa" 1248 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1249 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1250 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1251 (reg:V2SI SPE_ACC_REGNO)] 585)) 1252 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1253 "TARGET_SPE" 1254 "evmhogsmiaa %0,%1,%2" 1255 [(set_attr "type" "veccomplex") 1256 (set_attr "length" "4")]) 1257 1258(define_insn "spe_evmhogsmian" 1259 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1260 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1261 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1262 (reg:V2SI SPE_ACC_REGNO)] 586)) 1263 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1264 "TARGET_SPE" 1265 "evmhogsmian %0,%1,%2" 1266 [(set_attr "type" "veccomplex") 1267 (set_attr "length" "4")]) 1268 1269(define_insn "spe_evmhogumiaa" 1270 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1271 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1272 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1273 (reg:V2SI SPE_ACC_REGNO)] 587)) 1274 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1275 "TARGET_SPE" 1276 "evmhogumiaa %0,%1,%2" 1277 [(set_attr "type" "veccomplex") 1278 (set_attr "length" "4")]) 1279 1280(define_insn "spe_evmhogumian" 1281 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1282 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1283 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1284 (reg:V2SI SPE_ACC_REGNO)] 588)) 1285 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1286 "TARGET_SPE" 1287 "evmhogumian %0,%1,%2" 1288 [(set_attr "type" "veccomplex") 1289 (set_attr "length" "4")]) 1290 1291(define_insn "spe_evmhosmfaaw" 1292 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1293 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1294 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1295 (reg:V2SI SPE_ACC_REGNO)] 589)) 1296 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1297 "TARGET_SPE" 1298 "evmhosmfaaw %0,%1,%2" 1299 [(set_attr "type" "veccomplex") 1300 (set_attr "length" "4")]) 1301 1302(define_insn "spe_evmhosmfanw" 1303 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1304 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1305 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1306 (reg:V2SI SPE_ACC_REGNO)] 590)) 1307 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1308 "TARGET_SPE" 1309 "evmhosmfanw %0,%1,%2" 1310 [(set_attr "type" "veccomplex") 1311 (set_attr "length" "4")]) 1312 1313(define_insn "spe_evmhosmfa" 1314 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1315 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1316 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))] 1317 "TARGET_SPE" 1318 "evmhosmfa %0,%1,%2" 1319 [(set_attr "type" "veccomplex") 1320 (set_attr "length" "4")]) 1321 1322(define_insn "spe_evmhosmf" 1323 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1324 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1325 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592)) 1326 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1327 "TARGET_SPE" 1328 "evmhosmf %0,%1,%2" 1329 [(set_attr "type" "veccomplex") 1330 (set_attr "length" "4")]) 1331 1332(define_insn "spe_evmhosmiaaw" 1333 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1334 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1335 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1336 (reg:V2SI SPE_ACC_REGNO)] 593)) 1337 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1338 "TARGET_SPE" 1339 "evmhosmiaaw %0,%1,%2" 1340 [(set_attr "type" "veccomplex") 1341 (set_attr "length" "4")]) 1342 1343(define_insn "spe_evmhosmianw" 1344 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1345 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1346 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1347 (reg:V2SI SPE_ACC_REGNO)] 594)) 1348 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1349 "TARGET_SPE" 1350 "evmhosmianw %0,%1,%2" 1351 [(set_attr "type" "veccomplex") 1352 (set_attr "length" "4")]) 1353 1354(define_insn "spe_evmhosmia" 1355 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1356 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1357 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595)) 1358 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1359 "TARGET_SPE" 1360 "evmhosmia %0,%1,%2" 1361 [(set_attr "type" "veccomplex") 1362 (set_attr "length" "4")]) 1363 1364(define_insn "spe_evmhosmi" 1365 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1366 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1367 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))] 1368 "TARGET_SPE" 1369 "evmhosmi %0,%1,%2" 1370 [(set_attr "type" "veccomplex") 1371 (set_attr "length" "4")]) 1372 1373(define_insn "spe_evmhossfaaw" 1374 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1375 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1376 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1377 (reg:V2SI SPE_ACC_REGNO)] 597)) 1378 (clobber (reg:SI SPEFSCR_REGNO)) 1379 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1380 "TARGET_SPE" 1381 "evmhossfaaw %0,%1,%2" 1382 [(set_attr "type" "veccomplex") 1383 (set_attr "length" "4")]) 1384 1385(define_insn "spe_evmhossfanw" 1386 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1387 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1388 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1389 (reg:V2SI SPE_ACC_REGNO)] 598)) 1390 (clobber (reg:SI SPEFSCR_REGNO)) 1391 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1392 "TARGET_SPE" 1393 "evmhossfanw %0,%1,%2" 1394 [(set_attr "type" "veccomplex") 1395 (set_attr "length" "4")]) 1396 1397(define_insn "spe_evmhossfa" 1398 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1399 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1400 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1401 (reg:V2SI SPE_ACC_REGNO)] 599)) 1402 (clobber (reg:SI SPEFSCR_REGNO)) 1403 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1404 "TARGET_SPE" 1405 "evmhossfa %0,%1,%2" 1406 [(set_attr "type" "veccomplex") 1407 (set_attr "length" "4")]) 1408 1409(define_insn "spe_evmhossf" 1410 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1411 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1412 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600)) 1413 (clobber (reg:SI SPEFSCR_REGNO))] 1414 "TARGET_SPE" 1415 "evmhossf %0,%1,%2" 1416 [(set_attr "type" "veccomplex") 1417 (set_attr "length" "4")]) 1418 1419(define_insn "spe_evmhossiaaw" 1420 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1421 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1422 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1423 (reg:V2SI SPE_ACC_REGNO)] 601)) 1424 (clobber (reg:SI SPEFSCR_REGNO)) 1425 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1426 "TARGET_SPE" 1427 "evmhossiaaw %0,%1,%2" 1428 [(set_attr "type" "veccomplex") 1429 (set_attr "length" "4")]) 1430 1431(define_insn "spe_evmhossianw" 1432 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1433 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1434 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1435 (reg:V2SI SPE_ACC_REGNO)] 602)) 1436 (clobber (reg:SI SPEFSCR_REGNO)) 1437 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1438 "TARGET_SPE" 1439 "evmhossianw %0,%1,%2" 1440 [(set_attr "type" "veccomplex") 1441 (set_attr "length" "4")]) 1442 1443(define_insn "spe_evmhoumiaaw" 1444 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1445 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1446 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1447 (reg:V2SI SPE_ACC_REGNO)] 603)) 1448 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1449 "TARGET_SPE" 1450 "evmhoumiaaw %0,%1,%2" 1451 [(set_attr "type" "veccomplex") 1452 (set_attr "length" "4")]) 1453 1454(define_insn "spe_evmhoumianw" 1455 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1456 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1457 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1458 (reg:V2SI SPE_ACC_REGNO)] 604)) 1459 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1460 "TARGET_SPE" 1461 "evmhoumianw %0,%1,%2" 1462 [(set_attr "type" "veccomplex") 1463 (set_attr "length" "4")]) 1464 1465(define_insn "spe_evmhoumia" 1466 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1467 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1468 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605)) 1469 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1470 "TARGET_SPE" 1471 "evmhoumia %0,%1,%2" 1472 [(set_attr "type" "veccomplex") 1473 (set_attr "length" "4")]) 1474 1475(define_insn "spe_evmhoumi" 1476 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1477 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1478 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))] 1479 "TARGET_SPE" 1480 "evmhoumi %0,%1,%2" 1481 [(set_attr "type" "veccomplex") 1482 (set_attr "length" "4")]) 1483 1484(define_insn "spe_evmhousiaaw" 1485 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1486 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1487 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1488 (reg:V2SI SPE_ACC_REGNO)] 607)) 1489 (clobber (reg:SI SPEFSCR_REGNO)) 1490 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1491 "TARGET_SPE" 1492 "evmhousiaaw %0,%1,%2" 1493 [(set_attr "type" "veccomplex") 1494 (set_attr "length" "4")]) 1495 1496(define_insn "spe_evmhousianw" 1497 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1498 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1499 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1500 (reg:V2SI SPE_ACC_REGNO)] 608)) 1501 (clobber (reg:SI SPEFSCR_REGNO)) 1502 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1503 "TARGET_SPE" 1504 "evmhousianw %0,%1,%2" 1505 [(set_attr "type" "veccomplex") 1506 (set_attr "length" "4")]) 1507 1508(define_insn "spe_evmmlssfa" 1509 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1510 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1511 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))] 1512 "TARGET_SPE" 1513 "evmmlssfa %0,%1,%2" 1514 [(set_attr "type" "veccomplex") 1515 (set_attr "length" "4")]) 1516 1517(define_insn "spe_evmmlssf" 1518 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1519 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1520 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))] 1521 "TARGET_SPE" 1522 "evmmlssf %0,%1,%2" 1523 [(set_attr "type" "veccomplex") 1524 (set_attr "length" "4")]) 1525 1526(define_insn "spe_evmwhsmfa" 1527 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1528 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1529 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611)) 1530 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1531 "TARGET_SPE" 1532 "evmwhsmfa %0,%1,%2" 1533 [(set_attr "type" "veccomplex") 1534 (set_attr "length" "4")]) 1535 1536(define_insn "spe_evmwhsmf" 1537 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1538 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1539 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))] 1540 "TARGET_SPE" 1541 "evmwhsmf %0,%1,%2" 1542 [(set_attr "type" "veccomplex") 1543 (set_attr "length" "4")]) 1544 1545(define_insn "spe_evmwhsmia" 1546 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1547 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1548 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613)) 1549 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1550 "TARGET_SPE" 1551 "evmwhsmia %0,%1,%2" 1552 [(set_attr "type" "veccomplex") 1553 (set_attr "length" "4")]) 1554 1555(define_insn "spe_evmwhsmi" 1556 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1557 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1558 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))] 1559 "TARGET_SPE" 1560 "evmwhsmi %0,%1,%2" 1561 [(set_attr "type" "veccomplex") 1562 (set_attr "length" "4")]) 1563 1564(define_insn "spe_evmwhssfa" 1565 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1566 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1567 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615)) 1568 (clobber (reg:SI SPEFSCR_REGNO)) 1569 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1570 "TARGET_SPE" 1571 "evmwhssfa %0,%1,%2" 1572 [(set_attr "type" "veccomplex") 1573 (set_attr "length" "4")]) 1574 1575(define_insn "spe_evmwhusian" 1576 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1577 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1578 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))] 1579 "TARGET_SPE" 1580 "evmwhusian %0,%1,%2" 1581 [(set_attr "type" "veccomplex") 1582 (set_attr "length" "4")]) 1583 1584(define_insn "spe_evmwhssf" 1585 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1586 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1587 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628)) 1588 (clobber (reg:SI SPEFSCR_REGNO))] 1589 "TARGET_SPE" 1590 "evmwhssf %0,%1,%2" 1591 [(set_attr "type" "veccomplex") 1592 (set_attr "length" "4")]) 1593 1594(define_insn "spe_evmwhumia" 1595 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1596 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1597 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629)) 1598 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1599 "TARGET_SPE" 1600 "evmwhumia %0,%1,%2" 1601 [(set_attr "type" "veccomplex") 1602 (set_attr "length" "4")]) 1603 1604(define_insn "spe_evmwhumi" 1605 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1606 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1607 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))] 1608 "TARGET_SPE" 1609 "evmwhumi %0,%1,%2" 1610 [(set_attr "type" "veccomplex") 1611 (set_attr "length" "4")]) 1612 1613(define_insn "spe_evmwlsmiaaw" 1614 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1615 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1616 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1617 (reg:V2SI SPE_ACC_REGNO)] 635)) 1618 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1619 "TARGET_SPE" 1620 "evmwlsmiaaw %0,%1,%2" 1621 [(set_attr "type" "veccomplex") 1622 (set_attr "length" "4")]) 1623 1624(define_insn "spe_evmwlsmianw" 1625 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1626 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1627 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1628 (reg:V2SI SPE_ACC_REGNO)] 636)) 1629 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1630 "TARGET_SPE" 1631 "evmwlsmianw %0,%1,%2" 1632 [(set_attr "type" "veccomplex") 1633 (set_attr "length" "4")]) 1634 1635(define_insn "spe_evmwlssiaaw" 1636 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1637 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1638 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1639 (reg:V2SI SPE_ACC_REGNO)] 641)) 1640 (clobber (reg:SI SPEFSCR_REGNO)) 1641 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1642 "TARGET_SPE" 1643 "evmwlssiaaw %0,%1,%2" 1644 [(set_attr "type" "veccomplex") 1645 (set_attr "length" "4")]) 1646 1647(define_insn "spe_evmwlssianw" 1648 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1649 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1650 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1651 (reg:V2SI SPE_ACC_REGNO)] 642)) 1652 (clobber (reg:SI SPEFSCR_REGNO)) 1653 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1654 "TARGET_SPE" 1655 "evmwlssianw %0,%1,%2" 1656 [(set_attr "type" "veccomplex") 1657 (set_attr "length" "4")]) 1658 1659(define_insn "spe_evmwlumiaaw" 1660 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1661 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1662 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1663 (reg:V2SI SPE_ACC_REGNO)] 643)) 1664 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1665 "TARGET_SPE" 1666 "evmwlumiaaw %0,%1,%2" 1667 [(set_attr "type" "veccomplex") 1668 (set_attr "length" "4")]) 1669 1670(define_insn "spe_evmwlumianw" 1671 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1672 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1673 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1674 (reg:V2SI SPE_ACC_REGNO)] 644)) 1675 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1676 "TARGET_SPE" 1677 "evmwlumianw %0,%1,%2" 1678 [(set_attr "type" "veccomplex") 1679 (set_attr "length" "4")]) 1680 1681(define_insn "spe_evmwlumia" 1682 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1683 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1684 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645)) 1685 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1686 "TARGET_SPE" 1687 "evmwlumia %0,%1,%2" 1688 [(set_attr "type" "veccomplex") 1689 (set_attr "length" "4")]) 1690 1691(define_insn "spe_evmwlumi" 1692 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1693 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1694 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))] 1695 "TARGET_SPE" 1696 "evmwlumi %0,%1,%2" 1697 [(set_attr "type" "veccomplex") 1698 (set_attr "length" "4")]) 1699 1700(define_insn "spe_evmwlusiaaw" 1701 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1702 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1703 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1704 (reg:V2SI SPE_ACC_REGNO)] 647)) 1705 (clobber (reg:SI SPEFSCR_REGNO)) 1706 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1707 "TARGET_SPE" 1708 "evmwlusiaaw %0,%1,%2" 1709 [(set_attr "type" "veccomplex") 1710 (set_attr "length" "4")]) 1711 1712(define_insn "spe_evmwlusianw" 1713 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1714 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1715 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1716 (reg:V2SI SPE_ACC_REGNO)] 648)) 1717 (clobber (reg:SI SPEFSCR_REGNO)) 1718 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1719 "TARGET_SPE" 1720 "evmwlusianw %0,%1,%2" 1721 [(set_attr "type" "veccomplex") 1722 (set_attr "length" "4")]) 1723 1724(define_insn "spe_evmwsmfaa" 1725 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1726 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1727 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1728 (reg:V2SI SPE_ACC_REGNO)] 649)) 1729 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1730 "TARGET_SPE" 1731 "evmwsmfaa %0,%1,%2" 1732 [(set_attr "type" "veccomplex") 1733 (set_attr "length" "4")]) 1734 1735(define_insn "spe_evmwsmfan" 1736 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1737 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1738 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1739 (reg:V2SI SPE_ACC_REGNO)] 650)) 1740 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1741 "TARGET_SPE" 1742 "evmwsmfan %0,%1,%2" 1743 [(set_attr "type" "veccomplex") 1744 (set_attr "length" "4")]) 1745 1746(define_insn "spe_evmwsmfa" 1747 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1748 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1749 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651)) 1750 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1751 "TARGET_SPE" 1752 "evmwsmfa %0,%1,%2" 1753 [(set_attr "type" "veccomplex") 1754 (set_attr "length" "4")]) 1755 1756(define_insn "spe_evmwsmf" 1757 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1758 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1759 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))] 1760 "TARGET_SPE" 1761 "evmwsmf %0,%1,%2" 1762 [(set_attr "type" "veccomplex") 1763 (set_attr "length" "4")]) 1764 1765(define_insn "spe_evmwsmiaa" 1766 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1767 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1768 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1769 (reg:V2SI SPE_ACC_REGNO)] 653)) 1770 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1771 "TARGET_SPE" 1772 "evmwsmiaa %0,%1,%2" 1773 [(set_attr "type" "veccomplex") 1774 (set_attr "length" "4")]) 1775 1776(define_insn "spe_evmwsmian" 1777 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1778 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1779 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1780 (reg:V2SI SPE_ACC_REGNO)] 654)) 1781 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1782 "TARGET_SPE" 1783 "evmwsmian %0,%1,%2" 1784 [(set_attr "type" "veccomplex") 1785 (set_attr "length" "4")]) 1786 1787(define_insn "spe_evmwsmia" 1788 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1789 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1790 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655)) 1791 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1792 "TARGET_SPE" 1793 "evmwsmia %0,%1,%2" 1794 [(set_attr "type" "veccomplex") 1795 (set_attr "length" "4")]) 1796 1797(define_insn "spe_evmwsmi" 1798 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1799 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1800 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))] 1801 "TARGET_SPE" 1802 "evmwsmi %0,%1,%2" 1803 [(set_attr "type" "veccomplex") 1804 (set_attr "length" "4")]) 1805 1806(define_insn "spe_evmwssfaa" 1807 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1808 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1809 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1810 (reg:V2SI SPE_ACC_REGNO)] 657)) 1811 (clobber (reg:SI SPEFSCR_REGNO)) 1812 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1813 "TARGET_SPE" 1814 "evmwssfaa %0,%1,%2" 1815 [(set_attr "type" "veccomplex") 1816 (set_attr "length" "4")]) 1817 1818(define_insn "spe_evmwssfan" 1819 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1820 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1821 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1822 (reg:V2SI SPE_ACC_REGNO)] 658)) 1823 (clobber (reg:SI SPEFSCR_REGNO)) 1824 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1825 "TARGET_SPE" 1826 "evmwssfan %0,%1,%2" 1827 [(set_attr "type" "veccomplex") 1828 (set_attr "length" "4")]) 1829 1830(define_insn "spe_evmwssfa" 1831 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1832 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1833 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659)) 1834 (clobber (reg:SI SPEFSCR_REGNO)) 1835 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1836 "TARGET_SPE" 1837 "evmwssfa %0,%1,%2" 1838 [(set_attr "type" "veccomplex") 1839 (set_attr "length" "4")]) 1840 1841(define_insn "spe_evmwssf" 1842 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1843 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1844 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660)) 1845 (clobber (reg:SI SPEFSCR_REGNO))] 1846 "TARGET_SPE" 1847 "evmwssf %0,%1,%2" 1848 [(set_attr "type" "veccomplex") 1849 (set_attr "length" "4")]) 1850 1851(define_insn "spe_evmwumiaa" 1852 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1853 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1854 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1855 (reg:V2SI SPE_ACC_REGNO)] 661)) 1856 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1857 "TARGET_SPE" 1858 "evmwumiaa %0,%1,%2" 1859 [(set_attr "type" "veccomplex") 1860 (set_attr "length" "4")]) 1861 1862(define_insn "spe_evmwumian" 1863 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1864 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1865 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1866 (reg:V2SI SPE_ACC_REGNO)] 662)) 1867 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1868 "TARGET_SPE" 1869 "evmwumian %0,%1,%2" 1870 [(set_attr "type" "veccomplex") 1871 (set_attr "length" "4")]) 1872 1873(define_insn "spe_evmwumia" 1874 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1875 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1876 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663)) 1877 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1878 "TARGET_SPE" 1879 "evmwumia %0,%1,%2" 1880 [(set_attr "type" "veccomplex") 1881 (set_attr "length" "4")]) 1882 1883(define_insn "spe_evmwumi" 1884 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1885 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1886 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))] 1887 "TARGET_SPE" 1888 "evmwumi %0,%1,%2" 1889 [(set_attr "type" "veccomplex") 1890 (set_attr "length" "4")]) 1891 1892(define_insn "spe_evaddw" 1893 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1894 (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 1895 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] 1896 "TARGET_SPE" 1897 "evaddw %0,%1,%2" 1898 [(set_attr "type" "vecsimple") 1899 (set_attr "length" "4")]) 1900 1901(define_insn "spe_evaddusiaaw" 1902 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1903 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1904 (reg:V2SI SPE_ACC_REGNO)] 673)) 1905 (clobber (reg:SI SPEFSCR_REGNO)) 1906 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1907 "TARGET_SPE" 1908 "evaddusiaaw %0,%1" 1909 [(set_attr "type" "veccomplex") 1910 (set_attr "length" "4")]) 1911 1912(define_insn "spe_evaddumiaaw" 1913 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1914 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1915 (reg:V2SI SPE_ACC_REGNO)] 674)) 1916 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1917 "TARGET_SPE" 1918 "evaddumiaaw %0,%1" 1919 [(set_attr "type" "veccomplex") 1920 (set_attr "length" "4")]) 1921 1922(define_insn "spe_evaddssiaaw" 1923 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1924 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1925 (reg:V2SI SPE_ACC_REGNO)] 675)) 1926 (clobber (reg:SI SPEFSCR_REGNO)) 1927 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1928 "TARGET_SPE" 1929 "evaddssiaaw %0,%1" 1930 [(set_attr "type" "veccomplex") 1931 (set_attr "length" "4")]) 1932 1933(define_insn "spe_evaddsmiaaw" 1934 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1935 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1936 (reg:V2SI SPE_ACC_REGNO)] 676)) 1937 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1938 "TARGET_SPE" 1939 "evaddsmiaaw %0,%1" 1940 [(set_attr "type" "veccomplex") 1941 (set_attr "length" "4")]) 1942 1943(define_insn "spe_evaddiw" 1944 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1945 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1946 (match_operand:QI 2 "immediate_operand" "i")] 677))] 1947 "TARGET_SPE" 1948 "evaddiw %0,%1,%2" 1949 [(set_attr "type" "vecsimple") 1950 (set_attr "length" "4")]) 1951 1952(define_insn "spe_evsubifw" 1953 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1954 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1955 (match_operand:QI 2 "immediate_operand" "i")] 678))] 1956 "TARGET_SPE" 1957 "evsubifw %0,%2,%1" 1958 [(set_attr "type" "veccomplex") 1959 (set_attr "length" "4")]) 1960 1961(define_insn "spe_evsubfw" 1962 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1963 (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 1964 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] 1965 "TARGET_SPE" 1966 "evsubfw %0,%2,%1" 1967 [(set_attr "type" "veccomplex") 1968 (set_attr "length" "4")]) 1969 1970(define_insn "spe_evsubfusiaaw" 1971 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1972 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1973 (reg:V2SI SPE_ACC_REGNO)] 679)) 1974 (clobber (reg:SI SPEFSCR_REGNO)) 1975 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1976 "TARGET_SPE" 1977 "evsubfusiaaw %0,%1" 1978 [(set_attr "type" "veccomplex") 1979 (set_attr "length" "4")]) 1980 1981(define_insn "spe_evsubfumiaaw" 1982 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1983 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1984 (reg:V2SI SPE_ACC_REGNO)] 680)) 1985 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1986 "TARGET_SPE" 1987 "evsubfumiaaw %0,%1" 1988 [(set_attr "type" "veccomplex") 1989 (set_attr "length" "4")]) 1990 1991(define_insn "spe_evsubfssiaaw" 1992 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1993 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1994 (reg:V2SI SPE_ACC_REGNO)] 681)) 1995 (clobber (reg:SI SPEFSCR_REGNO)) 1996 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 1997 "TARGET_SPE" 1998 "evsubfssiaaw %0,%1" 1999 [(set_attr "type" "veccomplex") 2000 (set_attr "length" "4")]) 2001 2002(define_insn "spe_evsubfsmiaaw" 2003 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2004 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2005 (reg:V2SI SPE_ACC_REGNO)] 682)) 2006 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2007 "TARGET_SPE" 2008 "evsubfsmiaaw %0,%1" 2009 [(set_attr "type" "veccomplex") 2010 (set_attr "length" "4")]) 2011 2012(define_insn "spe_evmra" 2013 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2014 (match_operand:V2SI 1 "gpc_reg_operand" "r")) 2015 (set (reg:V2SI SPE_ACC_REGNO) 2016 (unspec:V2SI [(match_dup 1)] 726))] 2017 "TARGET_SPE" 2018 "evmra %0,%1" 2019 [(set_attr "type" "veccomplex") 2020 (set_attr "length" "4")]) 2021 2022(define_insn "spe_evdivws" 2023 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2024 (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 2025 (match_operand:V2SI 2 "gpc_reg_operand" "r"))) 2026 (clobber (reg:SI SPEFSCR_REGNO))] 2027 "TARGET_SPE" 2028 "evdivws %0,%1,%2" 2029 [(set_attr "type" "vecdiv") 2030 (set_attr "length" "4")]) 2031 2032(define_insn "spe_evdivwu" 2033 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2034 (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 2035 (match_operand:V2SI 2 "gpc_reg_operand" "r"))) 2036 (clobber (reg:SI SPEFSCR_REGNO))] 2037 "TARGET_SPE" 2038 "evdivwu %0,%1,%2" 2039 [(set_attr "type" "vecdiv") 2040 (set_attr "length" "4")]) 2041 2042(define_insn "spe_evsplatfi" 2043 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2044 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))] 2045 "TARGET_SPE" 2046 "evsplatfi %0,%1" 2047 [(set_attr "type" "vecperm") 2048 (set_attr "length" "4")]) 2049 2050(define_insn "spe_evsplati" 2051 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2052 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))] 2053 "TARGET_SPE" 2054 "evsplati %0,%1" 2055 [(set_attr "type" "vecperm") 2056 (set_attr "length" "4")]) 2057 2058(define_insn "spe_evstdd" 2059 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2060 (match_operand:QI 1 "immediate_operand" "i"))) 2061 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2062 (unspec [(const_int 0)] 686)] 2063 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" 2064 "evstdd %2,%1*8(%0)" 2065 [(set_attr "type" "vecstore") 2066 (set_attr "length" "4")]) 2067 2068(define_insn "spe_evstddx" 2069 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2070 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2071 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2072 (unspec [(const_int 0)] 687)] 2073 "TARGET_SPE" 2074 "evstddx %2,%0,%1" 2075 [(set_attr "type" "vecstore") 2076 (set_attr "length" "4")]) 2077 2078(define_insn "spe_evstdh" 2079 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2080 (match_operand:QI 1 "immediate_operand" "i"))) 2081 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2082 (unspec [(const_int 0)] 688)] 2083 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" 2084 "evstdh %2,%1*8(%0)" 2085 [(set_attr "type" "vecstore") 2086 (set_attr "length" "4")]) 2087 2088(define_insn "spe_evstdhx" 2089 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2090 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2091 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2092 (unspec [(const_int 0)] 689)] 2093 "TARGET_SPE" 2094 "evstdhx %2,%0,%1" 2095 [(set_attr "type" "vecstore") 2096 (set_attr "length" "4")]) 2097 2098(define_insn "spe_evstdw" 2099 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2100 (match_operand:QI 1 "immediate_operand" "i"))) 2101 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2102 (unspec [(const_int 0)] 690)] 2103 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" 2104 "evstdw %2,%1*8(%0)" 2105 [(set_attr "type" "vecstore") 2106 (set_attr "length" "4")]) 2107 2108(define_insn "spe_evstdwx" 2109 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2110 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2111 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2112 (unspec [(const_int 0)] 691)] 2113 "TARGET_SPE" 2114 "evstdwx %2,%0,%1" 2115 [(set_attr "type" "vecstore") 2116 (set_attr "length" "4")]) 2117 2118(define_insn "spe_evstwhe" 2119 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2120 (match_operand:QI 1 "immediate_operand" "i"))) 2121 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2122 (unspec [(const_int 0)] 692)] 2123 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" 2124 "evstwhe %2,%1*4(%0)" 2125 [(set_attr "type" "vecstore") 2126 (set_attr "length" "4")]) 2127 2128(define_insn "spe_evstwhex" 2129 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2130 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2131 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2132 (unspec [(const_int 0)] 693)] 2133 "TARGET_SPE" 2134 "evstwhex %2,%0,%1" 2135 [(set_attr "type" "vecstore") 2136 (set_attr "length" "4")]) 2137 2138(define_insn "spe_evstwho" 2139 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2140 (match_operand:QI 1 "immediate_operand" "i"))) 2141 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2142 (unspec [(const_int 0)] 694)] 2143 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" 2144 "evstwho %2,%1*4(%0)" 2145 [(set_attr "type" "vecstore") 2146 (set_attr "length" "4")]) 2147 2148(define_insn "spe_evstwhox" 2149 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2150 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2151 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2152 (unspec [(const_int 0)] 695)] 2153 "TARGET_SPE" 2154 "evstwhox %2,%0,%1" 2155 [(set_attr "type" "vecstore") 2156 (set_attr "length" "4")]) 2157 2158(define_insn "spe_evstwwe" 2159 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2160 (match_operand:QI 1 "immediate_operand" "i"))) 2161 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2162 (unspec [(const_int 0)] 696)] 2163 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" 2164 "evstwwe %2,%1*4(%0)" 2165 [(set_attr "type" "vecstore") 2166 (set_attr "length" "4")]) 2167 2168(define_insn "spe_evstwwex" 2169 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2170 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2171 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2172 (unspec [(const_int 0)] 697)] 2173 "TARGET_SPE" 2174 "evstwwex %2,%0,%1" 2175 [(set_attr "type" "vecstore") 2176 (set_attr "length" "4")]) 2177 2178(define_insn "spe_evstwwo" 2179 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2180 (match_operand:QI 1 "immediate_operand" "i"))) 2181 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2182 (unspec [(const_int 0)] 698)] 2183 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" 2184 "evstwwo %2,%1*4(%0)" 2185 [(set_attr "type" "vecstore") 2186 (set_attr "length" "4")]) 2187 2188(define_insn "spe_evstwwox" 2189 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2190 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2191 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2192 (unspec [(const_int 0)] 699)] 2193 "TARGET_SPE" 2194 "evstwwox %2,%0,%1" 2195 [(set_attr "type" "vecstore") 2196 (set_attr "length" "4")]) 2197 2198;; Double-precision floating point instructions. 2199 2200;; FIXME: Add o=r option. 2201(define_insn "*frob_df_di" 2202 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r") 2203 (subreg:DF (match_operand:DI 1 "input_operand" "r,m") 0))] 2204 "TARGET_E500_DOUBLE" 2205 "@ 2206 evmergelo %0,%1,%L1 2207 evldd%X1 %0,%y1") 2208 2209(define_insn "*frob_di_df" 2210 [(set (match_operand:DI 0 "nonimmediate_operand" "=&r") 2211 (subreg:DI (match_operand:DF 1 "input_operand" "r") 0))] 2212 "TARGET_E500_DOUBLE" 2213 "evmergehi %0,%1,%1\;mr %L0,%1" 2214 [(set_attr "length" "8")]) 2215 2216(define_insn "*frob_di_df_2" 2217 [(set (subreg:DF (match_operand:DI 0 "register_operand" "=&r,r") 0) 2218 (match_operand:DF 1 "input_operand" "r,m"))] 2219 "TARGET_E500_DOUBLE" 2220 "* 2221{ 2222 switch (which_alternative) 2223 { 2224 default: 2225 gcc_unreachable (); 2226 case 0: 2227 return \"evmergehi %0,%1,%1\;mr %L0,%1\"; 2228 case 1: 2229 /* If the address is not offsettable we need to load the whole 2230 doubleword into a 64-bit register and then copy the high word 2231 to form the correct output layout. */ 2232 if (!offsettable_nonstrict_memref_p (operands[1])) 2233 return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\"; 2234 /* If the low-address word is used in the address, we must load 2235 it last. Otherwise, load it first. Note that we cannot have 2236 auto-increment in that case since the address register is 2237 known to be dead. */ 2238 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 2239 operands[1], 0)) 2240 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 2241 else 2242 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\"; 2243 } 2244}" 2245 [(set_attr "length" "8,8")]) 2246 2247(define_insn "*mov_si<mode>_e500_subreg0" 2248 [(set (subreg:SI (match_operand:SPE64 0 "register_operand" "+r,&r") 0) 2249 (match_operand:SI 1 "input_operand" "r,m"))] 2250 "(TARGET_E500_DOUBLE && <MODE>mode == DFmode) || (TARGET_SPE && <MODE>mode != DFmode)" 2251 "@ 2252 evmergelo %0,%1,%0 2253 evmergelohi %0,%0,%0\;{l%U1%X1|lwz%U1%X1} %0,%1\;evmergelohi %0,%0,%0") 2254 2255;; ??? Could use evstwwe for memory stores in some cases, depending on 2256;; the offset. 2257(define_insn "*mov_si<mode>_e500_subreg0_2" 2258 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") 2259 (subreg:SI (match_operand:SPE64 1 "register_operand" "+r,&r") 0))] 2260 "(TARGET_E500_DOUBLE && <MODE>mode == DFmode) || (TARGET_SPE && <MODE>mode != DFmode)" 2261 "@ 2262 evmergehi %0,%0,%1 2263 evmergelohi %1,%1,%1\;{st%U0%X0|stw%U0%X0} %1,%0") 2264 2265(define_insn "*mov_si<mode>_e500_subreg4" 2266 [(set (subreg:SI (match_operand:SPE64 0 "register_operand" "+r,r") 4) 2267 (match_operand:SI 1 "input_operand" "r,m"))] 2268 "(TARGET_E500_DOUBLE && <MODE>mode == DFmode) || (TARGET_SPE && <MODE>mode != DFmode)" 2269 "@ 2270 mr %0,%1 2271 {l%U1%X1|lwz%U1%X1} %0,%1") 2272 2273(define_insn "*mov_si<mode>_e500_subreg4_2" 2274 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") 2275 (subreg:SI (match_operand:SPE64 1 "register_operand" "r,r") 4))] 2276 "(TARGET_E500_DOUBLE && <MODE>mode == DFmode) || (TARGET_SPE && <MODE>mode != DFmode)" 2277 "@ 2278 mr %0,%1 2279 {st%U0%X0|stw%U0%X0} %1,%0") 2280 2281;; FIXME: Allow r=CONST0. 2282(define_insn "*movdf_e500_double" 2283 [(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m") 2284 (match_operand:DF 1 "input_operand" "r,m,r"))] 2285 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE 2286 && (gpc_reg_operand (operands[0], DFmode) 2287 || gpc_reg_operand (operands[1], DFmode))" 2288 "* 2289 { 2290 switch (which_alternative) 2291 { 2292 case 0: 2293 return \"evor %0,%1,%1\"; 2294 case 1: 2295 return \"evldd%X1 %0,%y1\"; 2296 case 2: 2297 return \"evstdd%X0 %1,%y0\"; 2298 default: 2299 gcc_unreachable (); 2300 } 2301 }" 2302 [(set_attr "type" "*,vecload,vecstore") 2303 (set_attr "length" "*,*,*")]) 2304 2305(define_insn "spe_truncdfsf2" 2306 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 2307 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))] 2308 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 2309 "efscfd %0,%1") 2310 2311(define_insn "spe_absdf2" 2312 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") 2313 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))] 2314 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 2315 "efdabs %0,%1") 2316 2317(define_insn "spe_nabsdf2" 2318 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") 2319 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))] 2320 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 2321 "efdnabs %0,%1") 2322 2323(define_insn "spe_negdf2" 2324 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") 2325 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))] 2326 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 2327 "efdneg %0,%1") 2328 2329(define_insn "spe_adddf3" 2330 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") 2331 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "r") 2332 (match_operand:DF 2 "gpc_reg_operand" "r")))] 2333 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 2334 "efdadd %0,%1,%2") 2335 2336(define_insn "spe_subdf3" 2337 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") 2338 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "r") 2339 (match_operand:DF 2 "gpc_reg_operand" "r")))] 2340 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 2341 "efdsub %0,%1,%2") 2342 2343(define_insn "spe_muldf3" 2344 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") 2345 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "r") 2346 (match_operand:DF 2 "gpc_reg_operand" "r")))] 2347 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 2348 "efdmul %0,%1,%2") 2349 2350(define_insn "spe_divdf3" 2351 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") 2352 (div:DF (match_operand:DF 1 "gpc_reg_operand" "r") 2353 (match_operand:DF 2 "gpc_reg_operand" "r")))] 2354 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 2355 "efddiv %0,%1,%2") 2356 2357;; Vector move instructions. 2358 2359(define_expand "movv2si" 2360 [(set (match_operand:V2SI 0 "nonimmediate_operand" "") 2361 (match_operand:V2SI 1 "any_operand" ""))] 2362 "TARGET_SPE" 2363 "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }") 2364 2365(define_insn "*movv2si_internal" 2366 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r") 2367 (match_operand:V2SI 1 "input_operand" "r,m,r,W"))] 2368 "TARGET_SPE 2369 && (gpc_reg_operand (operands[0], V2SImode) 2370 || gpc_reg_operand (operands[1], V2SImode))" 2371 "* 2372{ 2373 switch (which_alternative) 2374 { 2375 case 0: return \"evstdd%X0 %1,%y0\"; 2376 case 1: return \"evldd%X1 %0,%y1\"; 2377 case 2: return \"evor %0,%1,%1\"; 2378 case 3: return output_vec_const_move (operands); 2379 default: gcc_unreachable (); 2380 } 2381}" 2382 [(set_attr "type" "vecload,vecstore,*,*") 2383 (set_attr "length" "*,*,*,12")]) 2384 2385(define_split 2386 [(set (match_operand:V2SI 0 "register_operand" "") 2387 (match_operand:V2SI 1 "zero_constant" ""))] 2388 "TARGET_SPE && reload_completed" 2389 [(set (match_dup 0) 2390 (xor:V2SI (match_dup 0) (match_dup 0)))] 2391 "") 2392 2393(define_expand "movv1di" 2394 [(set (match_operand:V1DI 0 "nonimmediate_operand" "") 2395 (match_operand:V1DI 1 "any_operand" ""))] 2396 "TARGET_SPE" 2397 "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }") 2398 2399(define_insn "*movv1di_internal" 2400 [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r") 2401 (match_operand:V1DI 1 "input_operand" "r,m,r,W"))] 2402 "TARGET_SPE 2403 && (gpc_reg_operand (operands[0], V1DImode) 2404 || gpc_reg_operand (operands[1], V1DImode))" 2405 "@ 2406 evstdd%X0 %1,%y0 2407 evldd%X1 %0,%y1 2408 evor %0,%1,%1 2409 evxor %0,%0,%0" 2410 [(set_attr "type" "vecload,vecstore,*,*") 2411 (set_attr "length" "*,*,*,*")]) 2412 2413(define_expand "movv4hi" 2414 [(set (match_operand:V4HI 0 "nonimmediate_operand" "") 2415 (match_operand:V4HI 1 "any_operand" ""))] 2416 "TARGET_SPE" 2417 "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }") 2418 2419(define_insn "*movv4hi_internal" 2420 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r,r") 2421 (match_operand:V4HI 1 "input_operand" "r,m,r,W"))] 2422 "TARGET_SPE 2423 && (gpc_reg_operand (operands[0], V4HImode) 2424 || gpc_reg_operand (operands[1], V4HImode))" 2425 "@ 2426 evstdd%X0 %1,%y0 2427 evldd%X1 %0,%y1 2428 evor %0,%1,%1 2429 evxor %0,%0,%0" 2430 [(set_attr "type" "vecload")]) 2431 2432(define_expand "movv2sf" 2433 [(set (match_operand:V2SF 0 "nonimmediate_operand" "") 2434 (match_operand:V2SF 1 "any_operand" ""))] 2435 "TARGET_SPE" 2436 "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }") 2437 2438(define_insn "*movv2sf_internal" 2439 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r") 2440 (match_operand:V2SF 1 "input_operand" "r,m,r,W"))] 2441 "TARGET_SPE 2442 && (gpc_reg_operand (operands[0], V2SFmode) 2443 || gpc_reg_operand (operands[1], V2SFmode))" 2444 "@ 2445 evstdd%X0 %1,%y0 2446 evldd%X1 %0,%y1 2447 evor %0,%1,%1 2448 evxor %0,%0,%0" 2449 [(set_attr "type" "vecload,vecstore,*,*") 2450 (set_attr "length" "*,*,*,*")]) 2451 2452;; End of vector move instructions. 2453 2454(define_insn "spe_evmwhssfaa" 2455 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2456 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2457 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702)) 2458 (clobber (reg:SI SPEFSCR_REGNO)) 2459 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2460 "TARGET_SPE" 2461 "evmwhssfaa %0,%1,%2" 2462 [(set_attr "type" "veccomplex") 2463 (set_attr "length" "4")]) 2464 2465(define_insn "spe_evmwhssmaa" 2466 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2467 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2468 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703)) 2469 (clobber (reg:SI SPEFSCR_REGNO)) 2470 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2471 "TARGET_SPE" 2472 "evmwhssmaa %0,%1,%2" 2473 [(set_attr "type" "veccomplex") 2474 (set_attr "length" "4")]) 2475 2476(define_insn "spe_evmwhsmfaa" 2477 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2478 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2479 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704)) 2480 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2481 "TARGET_SPE" 2482 "evmwhsmfaa %0,%1,%2" 2483 [(set_attr "type" "veccomplex") 2484 (set_attr "length" "4")]) 2485 2486(define_insn "spe_evmwhsmiaa" 2487 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2488 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2489 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705)) 2490 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2491 "TARGET_SPE" 2492 "evmwhsmiaa %0,%1,%2" 2493 [(set_attr "type" "veccomplex") 2494 (set_attr "length" "4")]) 2495 2496(define_insn "spe_evmwhusiaa" 2497 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2498 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2499 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706)) 2500 (clobber (reg:SI SPEFSCR_REGNO)) 2501 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2502 "TARGET_SPE" 2503 "evmwhusiaa %0,%1,%2" 2504 [(set_attr "type" "veccomplex") 2505 (set_attr "length" "4")]) 2506 2507(define_insn "spe_evmwhumiaa" 2508 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2509 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2510 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707)) 2511 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2512 "TARGET_SPE" 2513 "evmwhumiaa %0,%1,%2" 2514 [(set_attr "type" "veccomplex") 2515 (set_attr "length" "4")]) 2516 2517(define_insn "spe_evmwhssfan" 2518 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2519 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2520 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708)) 2521 (clobber (reg:SI SPEFSCR_REGNO)) 2522 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2523 "TARGET_SPE" 2524 "evmwhssfan %0,%1,%2" 2525 [(set_attr "type" "veccomplex") 2526 (set_attr "length" "4")]) 2527 2528(define_insn "spe_evmwhssian" 2529 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2530 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2531 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709)) 2532 (clobber (reg:SI SPEFSCR_REGNO)) 2533 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2534 "TARGET_SPE" 2535 "evmwhssian %0,%1,%2" 2536 [(set_attr "type" "veccomplex") 2537 (set_attr "length" "4")]) 2538 2539(define_insn "spe_evmwhsmfan" 2540 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2541 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2542 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710)) 2543 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2544 "TARGET_SPE" 2545 "evmwhsmfan %0,%1,%2" 2546 [(set_attr "type" "veccomplex") 2547 (set_attr "length" "4")]) 2548 2549(define_insn "spe_evmwhsmian" 2550 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2551 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2552 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711)) 2553 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2554 "TARGET_SPE" 2555 "evmwhsmian %0,%1,%2" 2556 [(set_attr "type" "veccomplex") 2557 (set_attr "length" "4")]) 2558 2559(define_insn "spe_evmwhumian" 2560 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2561 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2562 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713)) 2563 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2564 "TARGET_SPE" 2565 "evmwhumian %0,%1,%2" 2566 [(set_attr "type" "veccomplex") 2567 (set_attr "length" "4")]) 2568 2569(define_insn "spe_evmwhgssfaa" 2570 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2571 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2572 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714)) 2573 (clobber (reg:SI SPEFSCR_REGNO)) 2574 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2575 "TARGET_SPE" 2576 "evmwhgssfaa %0,%1,%2" 2577 [(set_attr "type" "veccomplex") 2578 (set_attr "length" "4")]) 2579 2580(define_insn "spe_evmwhgsmfaa" 2581 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2582 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2583 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715)) 2584 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2585 "TARGET_SPE" 2586 "evmwhgsmfaa %0,%1,%2" 2587 [(set_attr "type" "veccomplex") 2588 (set_attr "length" "4")]) 2589 2590(define_insn "spe_evmwhgsmiaa" 2591 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2592 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2593 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716)) 2594 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2595 "TARGET_SPE" 2596 "evmwhgsmiaa %0,%1,%2" 2597 [(set_attr "type" "veccomplex") 2598 (set_attr "length" "4")]) 2599 2600(define_insn "spe_evmwhgumiaa" 2601 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2602 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2603 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717)) 2604 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2605 "TARGET_SPE" 2606 "evmwhgumiaa %0,%1,%2" 2607 [(set_attr "type" "veccomplex") 2608 (set_attr "length" "4")]) 2609 2610(define_insn "spe_evmwhgssfan" 2611 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2612 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2613 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718)) 2614 (clobber (reg:SI SPEFSCR_REGNO)) 2615 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2616 "TARGET_SPE" 2617 "evmwhgssfan %0,%1,%2" 2618 [(set_attr "type" "veccomplex") 2619 (set_attr "length" "4")]) 2620 2621(define_insn "spe_evmwhgsmfan" 2622 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2623 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2624 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719)) 2625 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2626 "TARGET_SPE" 2627 "evmwhgsmfan %0,%1,%2" 2628 [(set_attr "type" "veccomplex") 2629 (set_attr "length" "4")]) 2630 2631(define_insn "spe_evmwhgsmian" 2632 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2633 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2634 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720)) 2635 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2636 "TARGET_SPE" 2637 "evmwhgsmian %0,%1,%2" 2638 [(set_attr "type" "veccomplex") 2639 (set_attr "length" "4")]) 2640 2641(define_insn "spe_evmwhgumian" 2642 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2643 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2644 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721)) 2645 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] 2646 "TARGET_SPE" 2647 "evmwhgumian %0,%1,%2" 2648 [(set_attr "type" "veccomplex") 2649 (set_attr "length" "4")]) 2650 2651(define_insn "spe_mtspefscr" 2652 [(set (reg:SI SPEFSCR_REGNO) 2653 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] 2654 722))] 2655 "TARGET_SPE" 2656 "mtspefscr %0" 2657 [(set_attr "type" "vecsimple")]) 2658 2659(define_insn "spe_mfspefscr" 2660 [(set (match_operand:SI 0 "register_operand" "=r") 2661 (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))] 2662 "TARGET_SPE" 2663 "mfspefscr %0" 2664 [(set_attr "type" "vecsimple")]) 2665 2666;; FP comparison stuff. 2667 2668;; Flip the GT bit. 2669(define_insn "e500_flip_gt_bit" 2670 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2671 (unspec:CCFP 2672 [(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))] 2673 "!TARGET_FPRS && TARGET_HARD_FLOAT" 2674 "* 2675{ 2676 return output_e500_flip_gt_bit (operands[0], operands[1]); 2677}" 2678 [(set_attr "type" "cr_logical")]) 2679 2680;; MPC8540 single-precision FP instructions on GPRs. 2681;; We have 2 variants for each. One for IEEE compliant math and one 2682;; for non IEEE compliant math. 2683 2684(define_insn "cmpsfeq_gpr" 2685 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2686 (unspec:CCFP 2687 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") 2688 (match_operand:SF 2 "gpc_reg_operand" "r"))] 2689 1000))] 2690 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations" 2691 "efscmpeq %0,%1,%2" 2692 [(set_attr "type" "veccmp")]) 2693 2694(define_insn "tstsfeq_gpr" 2695 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2696 (unspec:CCFP 2697 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") 2698 (match_operand:SF 2 "gpc_reg_operand" "r"))] 2699 1001))] 2700 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations" 2701 "efststeq %0,%1,%2" 2702 [(set_attr "type" "veccmpsimple")]) 2703 2704(define_insn "cmpsfgt_gpr" 2705 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2706 (unspec:CCFP 2707 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") 2708 (match_operand:SF 2 "gpc_reg_operand" "r"))] 2709 1002))] 2710 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations" 2711 "efscmpgt %0,%1,%2" 2712 [(set_attr "type" "veccmp")]) 2713 2714(define_insn "tstsfgt_gpr" 2715 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2716 (unspec:CCFP 2717 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") 2718 (match_operand:SF 2 "gpc_reg_operand" "r"))] 2719 1003))] 2720 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations" 2721 "efststgt %0,%1,%2" 2722 [(set_attr "type" "veccmpsimple")]) 2723 2724(define_insn "cmpsflt_gpr" 2725 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2726 (unspec:CCFP 2727 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") 2728 (match_operand:SF 2 "gpc_reg_operand" "r"))] 2729 1004))] 2730 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations" 2731 "efscmplt %0,%1,%2" 2732 [(set_attr "type" "veccmp")]) 2733 2734(define_insn "tstsflt_gpr" 2735 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2736 (unspec:CCFP 2737 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") 2738 (match_operand:SF 2 "gpc_reg_operand" "r"))] 2739 1005))] 2740 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations" 2741 "efststlt %0,%1,%2" 2742 [(set_attr "type" "veccmpsimple")]) 2743 2744;; Same thing, but for double-precision. 2745 2746(define_insn "cmpdfeq_gpr" 2747 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2748 (unspec:CCFP 2749 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") 2750 (match_operand:DF 2 "gpc_reg_operand" "r"))] 2751 CMPDFEQ_GPR))] 2752 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations" 2753 "efdcmpeq %0,%1,%2" 2754 [(set_attr "type" "veccmp")]) 2755 2756(define_insn "tstdfeq_gpr" 2757 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2758 (unspec:CCFP 2759 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") 2760 (match_operand:DF 2 "gpc_reg_operand" "r"))] 2761 TSTDFEQ_GPR))] 2762 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations" 2763 "efdtsteq %0,%1,%2" 2764 [(set_attr "type" "veccmpsimple")]) 2765 2766(define_insn "cmpdfgt_gpr" 2767 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2768 (unspec:CCFP 2769 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") 2770 (match_operand:DF 2 "gpc_reg_operand" "r"))] 2771 CMPDFGT_GPR))] 2772 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations" 2773 "efdcmpgt %0,%1,%2" 2774 [(set_attr "type" "veccmp")]) 2775 2776(define_insn "tstdfgt_gpr" 2777 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2778 (unspec:CCFP 2779 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") 2780 (match_operand:DF 2 "gpc_reg_operand" "r"))] 2781 TSTDFGT_GPR))] 2782 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations" 2783 "efdtstgt %0,%1,%2" 2784 [(set_attr "type" "veccmpsimple")]) 2785 2786(define_insn "cmpdflt_gpr" 2787 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2788 (unspec:CCFP 2789 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") 2790 (match_operand:DF 2 "gpc_reg_operand" "r"))] 2791 CMPDFLT_GPR))] 2792 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations" 2793 "efdcmplt %0,%1,%2" 2794 [(set_attr "type" "veccmp")]) 2795 2796(define_insn "tstdflt_gpr" 2797 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2798 (unspec:CCFP 2799 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") 2800 (match_operand:DF 2 "gpc_reg_operand" "r"))] 2801 TSTDFLT_GPR))] 2802 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations" 2803 "efdtstlt %0,%1,%2" 2804 [(set_attr "type" "veccmpsimple")]) 2805 2806;; Like cceq_ior_compare, but compare the GT bits. 2807(define_insn "e500_cr_ior_compare" 2808 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2809 (unspec:CCFP [(match_operand 1 "cc_reg_operand" "y") 2810 (match_operand 2 "cc_reg_operand" "y")] 2811 E500_CR_IOR_COMPARE))] 2812 "TARGET_E500" 2813 "cror 4*%0+gt,4*%1+gt,4*%2+gt" 2814 [(set_attr "type" "cr_logical")]) 2815