1;; Scheduling description for IBM PowerPC 440 processor.
2;;   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify
7;; it under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 2, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful,
12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14;; GNU General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING.  If not, write to
18;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19;; Boston, MA 02110-1301, USA.
20
21;; PPC440 Embedded PowerPC controller
22;; dual issue
23;; i_pipe - complex integer / compare / branch
24;; j_pipe - simple integer arithmetic
25;; l_pipe - load-store
26;; f_pipe - floating point arithmetic
27
28(define_automaton "ppc440_core,ppc440_apu")
29(define_cpu_unit "ppc440_i_pipe,ppc440_j_pipe,ppc440_l_pipe" "ppc440_core")
30(define_cpu_unit "ppc440_f_pipe" "ppc440_apu")
31(define_cpu_unit "ppc440_issue_0,ppc440_issue_1" "ppc440_core")
32
33(define_reservation "ppc440_issue" "ppc440_issue_0|ppc440_issue_1")
34
35
36(define_insn_reservation "ppc440-load" 3
37  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
38			load_l,store_c,sync")
39       (eq_attr "cpu" "ppc440"))
40  "ppc440_issue,ppc440_l_pipe")
41
42(define_insn_reservation "ppc440-store" 3
43  (and (eq_attr "type" "store,store_ux,store_u")
44       (eq_attr "cpu" "ppc440"))
45  "ppc440_issue,ppc440_l_pipe")
46
47(define_insn_reservation "ppc440-fpload" 4
48  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
49       (eq_attr "cpu" "ppc440"))
50  "ppc440_issue,ppc440_l_pipe")
51
52(define_insn_reservation "ppc440-fpstore" 3
53  (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
54       (eq_attr "cpu" "ppc440"))
55  "ppc440_issue,ppc440_l_pipe")
56
57(define_insn_reservation "ppc440-integer" 1
58  (and (eq_attr "type" "integer,insert_word")
59       (eq_attr "cpu" "ppc440"))
60  "ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
61
62(define_insn_reservation "ppc440-two" 1
63  (and (eq_attr "type" "two")
64       (eq_attr "cpu" "ppc440"))
65  "ppc440_issue_0+ppc440_issue_1,\
66   ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
67
68(define_insn_reservation "ppc440-three" 1
69  (and (eq_attr "type" "three")
70       (eq_attr "cpu" "ppc440"))
71  "ppc440_issue_0+ppc440_issue_1,ppc440_i_pipe|ppc440_j_pipe,\
72   ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
73
74(define_insn_reservation "ppc440-imul" 3
75  (and (eq_attr "type" "imul,imul_compare")
76       (eq_attr "cpu" "ppc440"))
77  "ppc440_issue,ppc440_i_pipe")
78
79(define_insn_reservation "ppc440-imul2" 2
80  (and (eq_attr "type" "imul2,imul3")
81       (eq_attr "cpu" "ppc440"))
82  "ppc440_issue,ppc440_i_pipe")
83
84(define_insn_reservation "ppc440-idiv" 34
85  (and (eq_attr "type" "idiv")
86       (eq_attr "cpu" "ppc440"))
87  "ppc440_issue,ppc440_i_pipe*33")
88
89(define_insn_reservation "ppc440-branch" 1
90  (and (eq_attr "type" "branch,jmpreg,isync")
91       (eq_attr "cpu" "ppc440"))
92  "ppc440_issue,ppc440_i_pipe")
93
94(define_insn_reservation "ppc440-compare" 2
95  (and (eq_attr "type" "cmp,fast_compare,compare,cr_logical,delayed_cr,mfcr")
96       (eq_attr "cpu" "ppc440"))
97  "ppc440_issue,ppc440_i_pipe")
98
99(define_insn_reservation "ppc440-fpcompare" 3 ; 2
100  (and (eq_attr "type" "fpcompare")
101       (eq_attr "cpu" "ppc440"))
102  "ppc440_issue,ppc440_f_pipe+ppc440_i_pipe")
103
104(define_insn_reservation "ppc440-fp" 5
105  (and (eq_attr "type" "fp,dmul")
106       (eq_attr "cpu" "ppc440"))
107  "ppc440_issue,ppc440_f_pipe")
108
109(define_insn_reservation "ppc440-sdiv" 19
110  (and (eq_attr "type" "sdiv")
111       (eq_attr "cpu" "ppc440"))
112  "ppc440_issue,ppc440_f_pipe*15")
113
114(define_insn_reservation "ppc440-ddiv" 33
115  (and (eq_attr "type" "ddiv")
116       (eq_attr "cpu" "ppc440"))
117  "ppc440_issue,ppc440_f_pipe*29")
118
119(define_insn_reservation "ppc440-mtcr" 3
120  (and (eq_attr "type" "mtcr")
121       (eq_attr "cpu" "ppc440"))
122  "ppc440_issue,ppc440_i_pipe")
123
124(define_insn_reservation "ppc440-mtjmpr" 4
125  (and (eq_attr "type" "mtjmpr")
126       (eq_attr "cpu" "ppc440"))
127  "ppc440_issue,ppc440_i_pipe")
128
129(define_insn_reservation "ppc440-mfjmpr" 2
130  (and (eq_attr "type" "mfjmpr")
131       (eq_attr "cpu" "ppc440"))
132  "ppc440_issue,ppc440_i_pipe")
133
134