1256056Sgrehan/*- 2256056Sgrehan * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3256056Sgrehan * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 4256056Sgrehan * All rights reserved. 5256056Sgrehan * 6256056Sgrehan * Redistribution and use in source and binary forms, with or without 7256056Sgrehan * modification, are permitted provided that the following conditions 8256056Sgrehan * are met: 9256056Sgrehan * 1. Redistributions of source code must retain the above copyright 10256056Sgrehan * notice, this list of conditions and the following disclaimer, 11256056Sgrehan * without modification, immediately at the beginning of the file. 12256056Sgrehan * 2. Redistributions in binary form must reproduce the above copyright 13256056Sgrehan * notice, this list of conditions and the following disclaimer in the 14256056Sgrehan * documentation and/or other materials provided with the distribution. 15256056Sgrehan * 16256056Sgrehan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17256056Sgrehan * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18256056Sgrehan * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19256056Sgrehan * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20256056Sgrehan * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21256056Sgrehan * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22256056Sgrehan * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23256056Sgrehan * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24256056Sgrehan * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25256056Sgrehan * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26256056Sgrehan * 27256056Sgrehan * $FreeBSD: releng/11.0/usr.sbin/bhyve/ahci.h 279965 2015-03-13 20:14:35Z mav $ 28256056Sgrehan */ 29256056Sgrehan 30256056Sgrehan#ifndef _AHCI_H_ 31256056Sgrehan#define _AHCI_H_ 32256056Sgrehan 33256056Sgrehan/* ATA register defines */ 34256056Sgrehan#define ATA_DATA 0 /* (RW) data */ 35256056Sgrehan 36256056Sgrehan#define ATA_FEATURE 1 /* (W) feature */ 37256056Sgrehan#define ATA_F_DMA 0x01 /* enable DMA */ 38256056Sgrehan#define ATA_F_OVL 0x02 /* enable overlap */ 39256056Sgrehan 40256056Sgrehan#define ATA_COUNT 2 /* (W) sector count */ 41256056Sgrehan 42256056Sgrehan#define ATA_SECTOR 3 /* (RW) sector # */ 43256056Sgrehan#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 44256056Sgrehan#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 45256056Sgrehan#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 46256056Sgrehan#define ATA_D_LBA 0x40 /* use LBA addressing */ 47256056Sgrehan#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 48256056Sgrehan 49256056Sgrehan#define ATA_COMMAND 7 /* (W) command */ 50256056Sgrehan 51256056Sgrehan#define ATA_ERROR 8 /* (R) error */ 52256056Sgrehan#define ATA_E_ILI 0x01 /* illegal length */ 53256056Sgrehan#define ATA_E_NM 0x02 /* no media */ 54256056Sgrehan#define ATA_E_ABORT 0x04 /* command aborted */ 55256056Sgrehan#define ATA_E_MCR 0x08 /* media change request */ 56256056Sgrehan#define ATA_E_IDNF 0x10 /* ID not found */ 57256056Sgrehan#define ATA_E_MC 0x20 /* media changed */ 58256056Sgrehan#define ATA_E_UNC 0x40 /* uncorrectable data */ 59256056Sgrehan#define ATA_E_ICRC 0x80 /* UDMA crc error */ 60256056Sgrehan#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 61256056Sgrehan 62256056Sgrehan#define ATA_IREASON 9 /* (R) interrupt reason */ 63256056Sgrehan#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 64256056Sgrehan#define ATA_I_IN 0x02 /* read (1) | write (0) */ 65256056Sgrehan#define ATA_I_RELEASE 0x04 /* released bus (1) */ 66256056Sgrehan#define ATA_I_TAGMASK 0xf8 /* tag mask */ 67256056Sgrehan 68256056Sgrehan#define ATA_STATUS 10 /* (R) status */ 69256056Sgrehan#define ATA_ALTSTAT 11 /* (R) alternate status */ 70256056Sgrehan#define ATA_S_ERROR 0x01 /* error */ 71256056Sgrehan#define ATA_S_INDEX 0x02 /* index */ 72256056Sgrehan#define ATA_S_CORR 0x04 /* data corrected */ 73256056Sgrehan#define ATA_S_DRQ 0x08 /* data request */ 74256056Sgrehan#define ATA_S_DSC 0x10 /* drive seek completed */ 75256056Sgrehan#define ATA_S_SERVICE 0x10 /* drive needs service */ 76256056Sgrehan#define ATA_S_DWF 0x20 /* drive write fault */ 77256056Sgrehan#define ATA_S_DMA 0x20 /* DMA ready */ 78256056Sgrehan#define ATA_S_READY 0x40 /* drive ready */ 79256056Sgrehan#define ATA_S_BUSY 0x80 /* busy */ 80256056Sgrehan 81256056Sgrehan#define ATA_CONTROL 12 /* (W) control */ 82256056Sgrehan#define ATA_A_IDS 0x02 /* disable interrupts */ 83256056Sgrehan#define ATA_A_RESET 0x04 /* RESET controller */ 84256056Sgrehan#define ATA_A_4BIT 0x08 /* 4 head bits */ 85256056Sgrehan#define ATA_A_HOB 0x80 /* High Order Byte enable */ 86256056Sgrehan 87256056Sgrehan/* SATA register defines */ 88256056Sgrehan#define ATA_SSTATUS 13 89256056Sgrehan#define ATA_SS_DET_MASK 0x0000000f 90256056Sgrehan#define ATA_SS_DET_NO_DEVICE 0x00000000 91256056Sgrehan#define ATA_SS_DET_DEV_PRESENT 0x00000001 92256056Sgrehan#define ATA_SS_DET_PHY_ONLINE 0x00000003 93256056Sgrehan#define ATA_SS_DET_PHY_OFFLINE 0x00000004 94256056Sgrehan 95256056Sgrehan#define ATA_SS_SPD_MASK 0x000000f0 96256056Sgrehan#define ATA_SS_SPD_NO_SPEED 0x00000000 97256056Sgrehan#define ATA_SS_SPD_GEN1 0x00000010 98256056Sgrehan#define ATA_SS_SPD_GEN2 0x00000020 99279965Smav#define ATA_SS_SPD_GEN3 0x00000030 100256056Sgrehan 101256056Sgrehan#define ATA_SS_IPM_MASK 0x00000f00 102256056Sgrehan#define ATA_SS_IPM_NO_DEVICE 0x00000000 103256056Sgrehan#define ATA_SS_IPM_ACTIVE 0x00000100 104256056Sgrehan#define ATA_SS_IPM_PARTIAL 0x00000200 105256056Sgrehan#define ATA_SS_IPM_SLUMBER 0x00000600 106279965Smav#define ATA_SS_IPM_DEVSLEEP 0x00000800 107256056Sgrehan 108256056Sgrehan#define ATA_SERROR 14 109256056Sgrehan#define ATA_SE_DATA_CORRECTED 0x00000001 110256056Sgrehan#define ATA_SE_COMM_CORRECTED 0x00000002 111256056Sgrehan#define ATA_SE_DATA_ERR 0x00000100 112256056Sgrehan#define ATA_SE_COMM_ERR 0x00000200 113256056Sgrehan#define ATA_SE_PROT_ERR 0x00000400 114256056Sgrehan#define ATA_SE_HOST_ERR 0x00000800 115256056Sgrehan#define ATA_SE_PHY_CHANGED 0x00010000 116256056Sgrehan#define ATA_SE_PHY_IERROR 0x00020000 117256056Sgrehan#define ATA_SE_COMM_WAKE 0x00040000 118256056Sgrehan#define ATA_SE_DECODE_ERR 0x00080000 119256056Sgrehan#define ATA_SE_PARITY_ERR 0x00100000 120256056Sgrehan#define ATA_SE_CRC_ERR 0x00200000 121256056Sgrehan#define ATA_SE_HANDSHAKE_ERR 0x00400000 122256056Sgrehan#define ATA_SE_LINKSEQ_ERR 0x00800000 123256056Sgrehan#define ATA_SE_TRANSPORT_ERR 0x01000000 124256056Sgrehan#define ATA_SE_UNKNOWN_FIS 0x02000000 125256056Sgrehan#define ATA_SE_EXCHANGED 0x04000000 126256056Sgrehan 127256056Sgrehan#define ATA_SCONTROL 15 128256056Sgrehan#define ATA_SC_DET_MASK 0x0000000f 129256056Sgrehan#define ATA_SC_DET_IDLE 0x00000000 130256056Sgrehan#define ATA_SC_DET_RESET 0x00000001 131256056Sgrehan#define ATA_SC_DET_DISABLE 0x00000004 132256056Sgrehan 133256056Sgrehan#define ATA_SC_SPD_MASK 0x000000f0 134256056Sgrehan#define ATA_SC_SPD_NO_SPEED 0x00000000 135256056Sgrehan#define ATA_SC_SPD_SPEED_GEN1 0x00000010 136256056Sgrehan#define ATA_SC_SPD_SPEED_GEN2 0x00000020 137279965Smav#define ATA_SC_SPD_SPEED_GEN3 0x00000030 138256056Sgrehan 139256056Sgrehan#define ATA_SC_IPM_MASK 0x00000f00 140256056Sgrehan#define ATA_SC_IPM_NONE 0x00000000 141256056Sgrehan#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 142256056Sgrehan#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 143279965Smav#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400 144256056Sgrehan 145256056Sgrehan#define ATA_SACTIVE 16 146256056Sgrehan 147256056Sgrehan#define AHCI_MAX_PORTS 32 148256056Sgrehan#define AHCI_MAX_SLOTS 32 149279965Smav#define AHCI_MAX_IRQS 16 150256056Sgrehan 151256056Sgrehan/* SATA AHCI v1.0 register defines */ 152256056Sgrehan#define AHCI_CAP 0x00 153256056Sgrehan#define AHCI_CAP_NPMASK 0x0000001f 154256056Sgrehan#define AHCI_CAP_SXS 0x00000020 155256056Sgrehan#define AHCI_CAP_EMS 0x00000040 156256056Sgrehan#define AHCI_CAP_CCCS 0x00000080 157256056Sgrehan#define AHCI_CAP_NCS 0x00001F00 158256056Sgrehan#define AHCI_CAP_NCS_SHIFT 8 159256056Sgrehan#define AHCI_CAP_PSC 0x00002000 160256056Sgrehan#define AHCI_CAP_SSC 0x00004000 161256056Sgrehan#define AHCI_CAP_PMD 0x00008000 162256056Sgrehan#define AHCI_CAP_FBSS 0x00010000 163256056Sgrehan#define AHCI_CAP_SPM 0x00020000 164256056Sgrehan#define AHCI_CAP_SAM 0x00080000 165256056Sgrehan#define AHCI_CAP_ISS 0x00F00000 166256056Sgrehan#define AHCI_CAP_ISS_SHIFT 20 167256056Sgrehan#define AHCI_CAP_SCLO 0x01000000 168256056Sgrehan#define AHCI_CAP_SAL 0x02000000 169256056Sgrehan#define AHCI_CAP_SALP 0x04000000 170256056Sgrehan#define AHCI_CAP_SSS 0x08000000 171256056Sgrehan#define AHCI_CAP_SMPS 0x10000000 172256056Sgrehan#define AHCI_CAP_SSNTF 0x20000000 173256056Sgrehan#define AHCI_CAP_SNCQ 0x40000000 174256056Sgrehan#define AHCI_CAP_64BIT 0x80000000 175256056Sgrehan 176256056Sgrehan#define AHCI_GHC 0x04 177256056Sgrehan#define AHCI_GHC_AE 0x80000000 178256056Sgrehan#define AHCI_GHC_MRSM 0x00000004 179256056Sgrehan#define AHCI_GHC_IE 0x00000002 180256056Sgrehan#define AHCI_GHC_HR 0x00000001 181256056Sgrehan 182256056Sgrehan#define AHCI_IS 0x08 183256056Sgrehan#define AHCI_PI 0x0c 184256056Sgrehan#define AHCI_VS 0x10 185256056Sgrehan 186256056Sgrehan#define AHCI_CCCC 0x14 187256056Sgrehan#define AHCI_CCCC_TV_MASK 0xffff0000 188256056Sgrehan#define AHCI_CCCC_TV_SHIFT 16 189256056Sgrehan#define AHCI_CCCC_CC_MASK 0x0000ff00 190256056Sgrehan#define AHCI_CCCC_CC_SHIFT 8 191256056Sgrehan#define AHCI_CCCC_INT_MASK 0x000000f8 192256056Sgrehan#define AHCI_CCCC_INT_SHIFT 3 193256056Sgrehan#define AHCI_CCCC_EN 0x00000001 194256056Sgrehan#define AHCI_CCCP 0x18 195256056Sgrehan 196256056Sgrehan#define AHCI_EM_LOC 0x1C 197256056Sgrehan#define AHCI_EM_CTL 0x20 198256056Sgrehan#define AHCI_EM_MR 0x00000001 199256056Sgrehan#define AHCI_EM_TM 0x00000100 200256056Sgrehan#define AHCI_EM_RST 0x00000200 201256056Sgrehan#define AHCI_EM_LED 0x00010000 202256056Sgrehan#define AHCI_EM_SAFTE 0x00020000 203256056Sgrehan#define AHCI_EM_SES2 0x00040000 204256056Sgrehan#define AHCI_EM_SGPIO 0x00080000 205256056Sgrehan#define AHCI_EM_SMB 0x01000000 206256056Sgrehan#define AHCI_EM_XMT 0x02000000 207256056Sgrehan#define AHCI_EM_ALHD 0x04000000 208256056Sgrehan#define AHCI_EM_PM 0x08000000 209256056Sgrehan 210256056Sgrehan#define AHCI_CAP2 0x24 211256056Sgrehan#define AHCI_CAP2_BOH 0x00000001 212256056Sgrehan#define AHCI_CAP2_NVMP 0x00000002 213256056Sgrehan#define AHCI_CAP2_APST 0x00000004 214279965Smav#define AHCI_CAP2_SDS 0x00000008 215279965Smav#define AHCI_CAP2_SADM 0x00000010 216279965Smav#define AHCI_CAP2_DESO 0x00000020 217256056Sgrehan 218256056Sgrehan#define AHCI_OFFSET 0x100 219256056Sgrehan#define AHCI_STEP 0x80 220256056Sgrehan 221256056Sgrehan#define AHCI_P_CLB 0x00 222256056Sgrehan#define AHCI_P_CLBU 0x04 223256056Sgrehan#define AHCI_P_FB 0x08 224256056Sgrehan#define AHCI_P_FBU 0x0c 225256056Sgrehan#define AHCI_P_IS 0x10 226256056Sgrehan#define AHCI_P_IE 0x14 227256056Sgrehan#define AHCI_P_IX_DHR 0x00000001 228256056Sgrehan#define AHCI_P_IX_PS 0x00000002 229256056Sgrehan#define AHCI_P_IX_DS 0x00000004 230256056Sgrehan#define AHCI_P_IX_SDB 0x00000008 231256056Sgrehan#define AHCI_P_IX_UF 0x00000010 232256056Sgrehan#define AHCI_P_IX_DP 0x00000020 233256056Sgrehan#define AHCI_P_IX_PC 0x00000040 234256056Sgrehan#define AHCI_P_IX_MP 0x00000080 235256056Sgrehan 236256056Sgrehan#define AHCI_P_IX_PRC 0x00400000 237256056Sgrehan#define AHCI_P_IX_IPM 0x00800000 238256056Sgrehan#define AHCI_P_IX_OF 0x01000000 239256056Sgrehan#define AHCI_P_IX_INF 0x04000000 240256056Sgrehan#define AHCI_P_IX_IF 0x08000000 241256056Sgrehan#define AHCI_P_IX_HBD 0x10000000 242256056Sgrehan#define AHCI_P_IX_HBF 0x20000000 243256056Sgrehan#define AHCI_P_IX_TFE 0x40000000 244256056Sgrehan#define AHCI_P_IX_CPD 0x80000000 245256056Sgrehan 246256056Sgrehan#define AHCI_P_CMD 0x18 247256056Sgrehan#define AHCI_P_CMD_ST 0x00000001 248256056Sgrehan#define AHCI_P_CMD_SUD 0x00000002 249256056Sgrehan#define AHCI_P_CMD_POD 0x00000004 250256056Sgrehan#define AHCI_P_CMD_CLO 0x00000008 251256056Sgrehan#define AHCI_P_CMD_FRE 0x00000010 252256056Sgrehan#define AHCI_P_CMD_CCS_MASK 0x00001f00 253256056Sgrehan#define AHCI_P_CMD_CCS_SHIFT 8 254256056Sgrehan#define AHCI_P_CMD_ISS 0x00002000 255256056Sgrehan#define AHCI_P_CMD_FR 0x00004000 256256056Sgrehan#define AHCI_P_CMD_CR 0x00008000 257256056Sgrehan#define AHCI_P_CMD_CPS 0x00010000 258256056Sgrehan#define AHCI_P_CMD_PMA 0x00020000 259256056Sgrehan#define AHCI_P_CMD_HPCP 0x00040000 260256056Sgrehan#define AHCI_P_CMD_MPSP 0x00080000 261256056Sgrehan#define AHCI_P_CMD_CPD 0x00100000 262256056Sgrehan#define AHCI_P_CMD_ESP 0x00200000 263256056Sgrehan#define AHCI_P_CMD_FBSCP 0x00400000 264256056Sgrehan#define AHCI_P_CMD_APSTE 0x00800000 265256056Sgrehan#define AHCI_P_CMD_ATAPI 0x01000000 266256056Sgrehan#define AHCI_P_CMD_DLAE 0x02000000 267256056Sgrehan#define AHCI_P_CMD_ALPE 0x04000000 268256056Sgrehan#define AHCI_P_CMD_ASP 0x08000000 269256056Sgrehan#define AHCI_P_CMD_ICC_MASK 0xf0000000 270256056Sgrehan#define AHCI_P_CMD_NOOP 0x00000000 271256056Sgrehan#define AHCI_P_CMD_ACTIVE 0x10000000 272256056Sgrehan#define AHCI_P_CMD_PARTIAL 0x20000000 273256056Sgrehan#define AHCI_P_CMD_SLUMBER 0x60000000 274279965Smav#define AHCI_P_CMD_DEVSLEEP 0x80000000 275256056Sgrehan 276256056Sgrehan#define AHCI_P_TFD 0x20 277256056Sgrehan#define AHCI_P_SIG 0x24 278256056Sgrehan#define AHCI_P_SSTS 0x28 279256056Sgrehan#define AHCI_P_SCTL 0x2c 280256056Sgrehan#define AHCI_P_SERR 0x30 281256056Sgrehan#define AHCI_P_SACT 0x34 282256056Sgrehan#define AHCI_P_CI 0x38 283256056Sgrehan#define AHCI_P_SNTF 0x3C 284256056Sgrehan#define AHCI_P_FBS 0x40 285256056Sgrehan#define AHCI_P_FBS_EN 0x00000001 286256056Sgrehan#define AHCI_P_FBS_DEC 0x00000002 287256056Sgrehan#define AHCI_P_FBS_SDE 0x00000004 288256056Sgrehan#define AHCI_P_FBS_DEV 0x00000f00 289256056Sgrehan#define AHCI_P_FBS_DEV_SHIFT 8 290256056Sgrehan#define AHCI_P_FBS_ADO 0x0000f000 291256056Sgrehan#define AHCI_P_FBS_ADO_SHIFT 12 292256056Sgrehan#define AHCI_P_FBS_DWE 0x000f0000 293256056Sgrehan#define AHCI_P_FBS_DWE_SHIFT 16 294279965Smav#define AHCI_P_DEVSLP 0x44 295279965Smav#define AHCI_P_DEVSLP_ADSE 0x00000001 296279965Smav#define AHCI_P_DEVSLP_DSP 0x00000002 297279965Smav#define AHCI_P_DEVSLP_DETO 0x000003fc 298279965Smav#define AHCI_P_DEVSLP_DETO_SHIFT 2 299279965Smav#define AHCI_P_DEVSLP_MDAT 0x00007c00 300279965Smav#define AHCI_P_DEVSLP_MDAT_SHIFT 10 301279965Smav#define AHCI_P_DEVSLP_DITO 0x01ff8000 302279965Smav#define AHCI_P_DEVSLP_DITO_SHIFT 15 303279965Smav#define AHCI_P_DEVSLP_DM 0x0e000000 304279965Smav#define AHCI_P_DEVSLP_DM_SHIFT 25 305256056Sgrehan 306256056Sgrehan/* Just to be sure, if building as module. */ 307256056Sgrehan#if MAXPHYS < 512 * 1024 308256056Sgrehan#undef MAXPHYS 309256056Sgrehan#define MAXPHYS 512 * 1024 310256056Sgrehan#endif 311256056Sgrehan/* Pessimistic prognosis on number of required S/G entries */ 312256056Sgrehan#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8)) 313256056Sgrehan/* Command list. 32 commands. First, 1Kbyte aligned. */ 314256056Sgrehan#define AHCI_CL_OFFSET 0 315256056Sgrehan#define AHCI_CL_SIZE 32 316256056Sgrehan/* Command tables. Up to 32 commands, Each, 128byte aligned. */ 317256056Sgrehan#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS) 318256056Sgrehan#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16) 319256056Sgrehan/* Total main work area. */ 320256056Sgrehan#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) 321256056Sgrehan 322256056Sgrehan#endif /* _AHCI_H_ */ 323