psycho.c revision 271192
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 271192 2014-09-06 15:23:28Z jhb $"); 35 36/* 37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 39 */ 40 41#include "opt_ofw_pci.h" 42#include "opt_psycho.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/endian.h> 48#include <sys/kdb.h> 49#include <sys/kernel.h> 50#include <sys/lock.h> 51#include <sys/malloc.h> 52#include <sys/module.h> 53#include <sys/mutex.h> 54#include <sys/pcpu.h> 55#include <sys/reboot.h> 56#include <sys/rman.h> 57#include <sys/sysctl.h> 58 59#include <dev/ofw/ofw_bus.h> 60#include <dev/ofw/ofw_pci.h> 61#include <dev/ofw/openfirm.h> 62 63#include <machine/bus.h> 64#include <machine/bus_common.h> 65#include <machine/bus_private.h> 66#include <machine/iommureg.h> 67#include <machine/iommuvar.h> 68#include <machine/resource.h> 69#include <machine/ver.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sparc64/pci/ofw_pci.h> 75#include <sparc64/pci/psychoreg.h> 76#include <sparc64/pci/psychovar.h> 77 78#include "pcib_if.h" 79 80static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 81 const char *); 82static const struct psycho_desc *psycho_get_desc(device_t); 83static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t, 84 driver_filter_t, driver_intr_t); 85static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *, 86 bus_addr_t *, u_long *); 87static void sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 88 bus_dmasync_op_t op); 89static void psycho_intr_enable(void *); 90static void psycho_intr_disable(void *); 91static void psycho_intr_assign(void *); 92static void psycho_intr_clear(void *); 93 94/* Interrupt handlers */ 95static driver_filter_t psycho_ue; 96static driver_filter_t psycho_ce; 97static driver_filter_t psycho_pci_bus; 98static driver_filter_t psycho_powerdebug; 99static driver_intr_t psycho_powerdown; 100static driver_intr_t psycho_overtemp; 101#ifdef PSYCHO_MAP_WAKEUP 102static driver_filter_t psycho_wakeup; 103#endif 104 105/* IOMMU support */ 106static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 107 108/* 109 * Methods 110 */ 111static device_probe_t psycho_probe; 112static device_attach_t psycho_attach; 113static bus_read_ivar_t psycho_read_ivar; 114static bus_setup_intr_t psycho_setup_intr; 115static bus_alloc_resource_t psycho_alloc_resource; 116static bus_activate_resource_t psycho_activate_resource; 117static bus_adjust_resource_t psycho_adjust_resource; 118static bus_get_dma_tag_t psycho_get_dma_tag; 119static pcib_maxslots_t psycho_maxslots; 120static pcib_read_config_t psycho_read_config; 121static pcib_write_config_t psycho_write_config; 122static pcib_route_interrupt_t psycho_route_interrupt; 123static ofw_bus_get_node_t psycho_get_node; 124static ofw_pci_setup_device_t psycho_setup_device; 125 126static device_method_t psycho_methods[] = { 127 /* Device interface */ 128 DEVMETHOD(device_probe, psycho_probe), 129 DEVMETHOD(device_attach, psycho_attach), 130 DEVMETHOD(device_shutdown, bus_generic_shutdown), 131 DEVMETHOD(device_suspend, bus_generic_suspend), 132 DEVMETHOD(device_resume, bus_generic_resume), 133 134 /* Bus interface */ 135 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 136 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 137 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 138 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 139 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 140 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 141 DEVMETHOD(bus_adjust_resource, psycho_adjust_resource), 142 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 143 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag), 144 145 /* pcib interface */ 146 DEVMETHOD(pcib_maxslots, psycho_maxslots), 147 DEVMETHOD(pcib_read_config, psycho_read_config), 148 DEVMETHOD(pcib_write_config, psycho_write_config), 149 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 150 151 /* ofw_bus interface */ 152 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 153 154 /* ofw_pci interface */ 155 DEVMETHOD(ofw_pci_setup_device, psycho_setup_device), 156 157 DEVMETHOD_END 158}; 159 160static devclass_t psycho_devclass; 161 162DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods, 163 sizeof(struct psycho_softc)); 164EARLY_DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, NULL, NULL, 165 BUS_PASS_BUS); 166 167static SYSCTL_NODE(_hw, OID_AUTO, psycho, CTLFLAG_RD, 0, "psycho parameters"); 168 169static u_int psycho_powerfail = 1; 170SYSCTL_UINT(_hw_psycho, OID_AUTO, powerfail, CTLFLAG_RDTUN, &psycho_powerfail, 171 0, "powerfail action (0: none, 1: shutdown (default), 2: debugger)"); 172 173static SLIST_HEAD(, psycho_softc) psycho_softcs = 174 SLIST_HEAD_INITIALIZER(psycho_softcs); 175 176static const struct intr_controller psycho_ic = { 177 psycho_intr_enable, 178 psycho_intr_disable, 179 psycho_intr_assign, 180 psycho_intr_clear 181}; 182 183struct psycho_icarg { 184 struct psycho_softc *pica_sc; 185 bus_addr_t pica_map; 186 bus_addr_t pica_clr; 187}; 188 189#define PSYCHO_READ8(sc, off) \ 190 bus_read_8((sc)->sc_mem_res, (off)) 191#define PSYCHO_WRITE8(sc, off, v) \ 192 bus_write_8((sc)->sc_mem_res, (off), (v)) 193#define PCICTL_READ8(sc, off) \ 194 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 195#define PCICTL_WRITE8(sc, off, v) \ 196 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 197 198/* 199 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 200 * single PCI bus and does not have a streaming buffer. It often has an APB 201 * (advanced PCI bridge) connected to it, which was designed specifically for 202 * the IIi. The APB lets the IIi handle two independent PCI buses, and 203 * appears as two "Simba"'s underneath the Sabre. 204 * 205 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 206 * basically the same as Sabre but without an APB underneath it. 207 * 208 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA 209 * bus and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 210 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 211 * will usually find a "Psycho+" since I don't think the original "Psycho" 212 * ever shipped, and if it did it would be in the U30. 213 * 214 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 215 * both part of the same IC, they only have a single register space. As such, 216 * they need to be configured together, even though the autoconfiguration will 217 * attach them separately. 218 * 219 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 220 * as pci1 and pci2, although they have been implemented with other PCI bus 221 * numbers on some machines. 222 * 223 * On UltraII machines, there can be any number of "Psycho+" ICs, each 224 * providing two PCI buses. 225 */ 226 227struct psycho_desc { 228 const char *pd_string; 229 int pd_mode; 230 const char *pd_name; 231}; 232 233static const struct psycho_desc psycho_compats[] = { 234 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 235 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 236 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 237 { NULL, 0, NULL } 238}; 239 240static const struct psycho_desc psycho_models[] = { 241 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 242 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 243 { NULL, 0, NULL } 244}; 245 246static const struct psycho_desc * 247psycho_find_desc(const struct psycho_desc *table, const char *string) 248{ 249 const struct psycho_desc *desc; 250 251 if (string == NULL) 252 return (NULL); 253 for (desc = table; desc->pd_string != NULL; desc++) 254 if (strcmp(desc->pd_string, string) == 0) 255 return (desc); 256 return (NULL); 257} 258 259static const struct psycho_desc * 260psycho_get_desc(device_t dev) 261{ 262 const struct psycho_desc *rv; 263 264 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev)); 265 if (rv == NULL) 266 rv = psycho_find_desc(psycho_compats, 267 ofw_bus_get_compat(dev)); 268 return (rv); 269} 270 271static int 272psycho_probe(device_t dev) 273{ 274 const char *dtype; 275 276 dtype = ofw_bus_get_type(dev); 277 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 278 psycho_get_desc(dev) != NULL) { 279 device_set_desc(dev, "U2P UPA-PCI bridge"); 280 return (0); 281 } 282 return (ENXIO); 283} 284 285static int 286psycho_attach(device_t dev) 287{ 288 struct psycho_icarg *pica; 289 struct psycho_softc *asc, *sc, *osc; 290 struct ofw_pci_ranges *range; 291 const struct psycho_desc *desc; 292 bus_addr_t intrclr, intrmap; 293 uint64_t csr, dr; 294 phandle_t node; 295 uint32_t dvmabase, prop, prop_array[2]; 296 u_int rerun, ver; 297 int i, j; 298 299 node = ofw_bus_get_node(dev); 300 sc = device_get_softc(dev); 301 desc = psycho_get_desc(dev); 302 303 sc->sc_node = node; 304 sc->sc_dev = dev; 305 sc->sc_mode = desc->pd_mode; 306 307 /* 308 * The Psycho gets three register banks: 309 * (0) per-PBM configuration and status registers 310 * (1) per-PBM PCI configuration space, containing only the 311 * PBM 256-byte PCI header 312 * (2) the shared Psycho configuration registers 313 */ 314 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 315 i = 2; 316 sc->sc_pcictl = 317 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) - 318 bus_get_resource_start(dev, SYS_RES_MEMORY, 2); 319 switch (sc->sc_pcictl) { 320 case PSR_PCICTL0: 321 sc->sc_half = 0; 322 break; 323 case PSR_PCICTL1: 324 sc->sc_half = 1; 325 break; 326 default: 327 panic("%s: bogus PCI control register location", 328 __func__); 329 /* NOTREACHED */ 330 } 331 } else { 332 i = 0; 333 sc->sc_pcictl = PSR_PCICTL0; 334 sc->sc_half = 0; 335 } 336 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, 337 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) | 338 RF_ACTIVE); 339 if (sc->sc_mem_res == NULL) 340 panic("%s: could not allocate registers", __func__); 341 342 /* 343 * Match other Psychos that are already configured against 344 * the base physical address. This will be the same for a 345 * pair of devices that share register space. 346 */ 347 osc = NULL; 348 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 349 if (rman_get_start(asc->sc_mem_res) == 350 rman_get_start(sc->sc_mem_res)) { 351 /* Found partner. */ 352 osc = asc; 353 break; 354 } 355 } 356 if (osc == NULL) { 357 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 358 M_NOWAIT | M_ZERO); 359 if (sc->sc_mtx == NULL) 360 panic("%s: could not malloc mutex", __func__); 361 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 362 } else { 363 if (sc->sc_mode != PSYCHO_MODE_PSYCHO) 364 panic("%s: no partner expected", __func__); 365 if (mtx_initialized(osc->sc_mtx) == 0) 366 panic("%s: mutex not initialized", __func__); 367 sc->sc_mtx = osc->sc_mtx; 368 } 369 370 csr = PSYCHO_READ8(sc, PSR_CS); 371 ver = PSYCHO_GCSR_VERS(csr); 372 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */ 373 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 374 sc->sc_ign = PSYCHO_GCSR_IGN(csr); 375 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 376 prop = 33000000; 377 378 device_printf(dev, 379 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n", 380 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, 381 'A' + sc->sc_half, prop / 1000 / 1000); 382 383 /* Set up the PCI control and PCI diagnostic registers. */ 384 385 csr = PCICTL_READ8(sc, PCR_CS); 386 csr &= ~PCICTL_ARB_PARK; 387 if (OF_getproplen(node, "no-bus-parking") < 0) 388 csr |= PCICTL_ARB_PARK; 389 390 /* Workarounds for version specific bugs. */ 391 dr = PCICTL_READ8(sc, PCR_DIAG); 392 switch (ver) { 393 case 0: 394 dr |= DIAG_RTRY_DIS; 395 dr &= ~DIAG_DWSYNC_DIS; 396 rerun = 0; 397 break; 398 case 1: 399 csr &= ~PCICTL_ARB_PARK; 400 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS; 401 rerun = 0; 402 break; 403 default: 404 dr |= DIAG_DWSYNC_DIS; 405 dr &= ~DIAG_RTRY_DIS; 406 rerun = 1; 407 break; 408 } 409 410 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4; 411 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); 412#ifdef PSYCHO_DEBUG 413 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 414 (unsigned long long)PCICTL_READ8(sc, PCR_CS), 415 (unsigned long long)csr); 416#endif 417 PCICTL_WRITE8(sc, PCR_CS, csr); 418 419 dr &= ~DIAG_ISYNC_DIS; 420#ifdef PSYCHO_DEBUG 421 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 422 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG), 423 (unsigned long long)dr); 424#endif 425 PCICTL_WRITE8(sc, PCR_DIAG, dr); 426 427 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 428 /* Use the PROM preset for now. */ 429 csr = PCICTL_READ8(sc, PCR_TAS); 430 if (csr == 0) 431 panic("%s: Hummingbird/Sabre TAS not initialized.", 432 __func__); 433 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 434 } else 435 dvmabase = -1; 436 437 /* Initialize memory and I/O rmans. */ 438 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 439 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 440 if (rman_init(&sc->sc_pci_io_rman) != 0 || 441 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 442 panic("%s: failed to set up I/O rman", __func__); 443 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 444 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 445 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 446 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 447 panic("%s: failed to set up memory rman", __func__); 448 449 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 450 /* 451 * Find the addresses of the various bus spaces. 452 * There should not be multiple ones of one kind. 453 * The physical start addresses of the ranges are the configuration, 454 * memory and I/O handles. 455 */ 456 for (; i >= 0; i--) { 457 j = OFW_PCI_RANGE_CS(&range[i]); 458 if (sc->sc_pci_bh[j] != 0) 459 panic("%s: duplicate range for space %d", 460 __func__, j); 461 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 462 } 463 464 /* 465 * Make sure that the expected ranges are present. The 466 * OFW_PCI_CS_MEM64 one is not currently used. 467 */ 468 if (sc->sc_pci_bh[OFW_PCI_CS_CONFIG] == 0) 469 panic("%s: missing CONFIG range", __func__); 470 if (sc->sc_pci_bh[OFW_PCI_CS_IO] == 0) 471 panic("%s: missing IO range", __func__); 472 if (sc->sc_pci_bh[OFW_PCI_CS_MEM32] == 0) 473 panic("%s: missing MEM32 range", __func__); 474 475 free(range, M_OFWPROP); 476 477 /* Register the softc, this is needed for paired Psychos. */ 478 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 479 480 /* 481 * If we're a Hummingbird/Sabre or the first of a pair of Psychos 482 * to arrive here, do the interrupt setup and start up the IOMMU. 483 */ 484 if (osc == NULL) { 485 /* 486 * Hunt through all the interrupt mapping regs and register 487 * our interrupt controller for the corresponding interrupt 488 * vectors. We do this early in order to be able to catch 489 * stray interrupts. 490 */ 491 for (i = 0; i <= PSYCHO_MAX_INO; i++) { 492 if (psycho_find_intrmap(sc, i, &intrmap, &intrclr, 493 NULL) == 0) 494 continue; 495 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT); 496 if (pica == NULL) 497 panic("%s: could not allocate interrupt " 498 "controller argument", __func__); 499 pica->pica_sc = sc; 500 pica->pica_map = intrmap; 501 pica->pica_clr = intrclr; 502#ifdef PSYCHO_DEBUG 503 /* 504 * Enable all interrupts and clear all interrupt 505 * states. This aids the debugging of interrupt 506 * routing problems. 507 */ 508 device_printf(dev, 509 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n", 510 i, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO", 511 (u_long)intrmap, (u_long)PSYCHO_READ8(sc, 512 intrmap), (u_long)intrclr); 513 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, i)); 514 PSYCHO_WRITE8(sc, intrclr, INTCLR_IDLE); 515 PSYCHO_WRITE8(sc, intrmap, 516 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, i), 517 PCPU_GET(mid))); 518#endif 519 j = intr_controller_register(INTMAP_VEC(sc->sc_ign, 520 i), &psycho_ic, pica); 521 if (j != 0) 522 device_printf(dev, "could not register " 523 "interrupt controller for INO %d (%d)\n", 524 i, j); 525 } 526 527 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 528 sparc64_counter_init(device_get_nameunit(dev), 529 rman_get_bustag(sc->sc_mem_res), 530 rman_get_bushandle(sc->sc_mem_res), PSR_TC0); 531 532 /* 533 * Set up IOMMU and PCI configuration if we're the first 534 * of a pair of Psychos to arrive here or a Hummingbird 535 * or Sabre. 536 * 537 * We should calculate a TSB size based on amount of RAM 538 * and number of bus controllers and number and type of 539 * child devices. 540 * 541 * For the moment, 32KB should be more than enough. 542 */ 543 sc->sc_is = malloc(sizeof(*sc->sc_is), M_DEVBUF, M_NOWAIT | 544 M_ZERO); 545 if (sc->sc_is == NULL) 546 panic("%s: could not malloc IOMMU state", __func__); 547 sc->sc_is->is_flags = IOMMU_PRESERVE_PROM; 548 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 549 sc->sc_dma_methods = 550 malloc(sizeof(*sc->sc_dma_methods), M_DEVBUF, 551 M_NOWAIT); 552 if (sc->sc_dma_methods == NULL) 553 panic("%s: could not malloc DMA methods", 554 __func__); 555 memcpy(sc->sc_dma_methods, &iommu_dma_methods, 556 sizeof(*sc->sc_dma_methods)); 557 sc->sc_dma_methods->dm_dmamap_sync = 558 sabre_dmamap_sync; 559 sc->sc_is->is_pmaxaddr = 560 IOMMU_MAXADDR(SABRE_IOMMU_BITS); 561 } else { 562 sc->sc_dma_methods = &iommu_dma_methods; 563 sc->sc_is->is_pmaxaddr = 564 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS); 565 } 566 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0; 567 if (OF_getproplen(node, "no-streaming-cache") < 0) 568 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 569 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0; 570 psycho_iommu_init(sc, 3, dvmabase); 571 } else { 572 /* Just copy IOMMU state, config tag and address. */ 573 sc->sc_dma_methods = &iommu_dma_methods; 574 sc->sc_is = osc->sc_is; 575 if (OF_getproplen(node, "no-streaming-cache") < 0) 576 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 577 iommu_reset(sc->sc_is); 578 } 579 580 /* Allocate our tags. */ 581 sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, PCI_IO_BUS_SPACE); 582 if (sc->sc_pci_iot == NULL) 583 panic("%s: could not allocate PCI I/O tag", __func__); 584 sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, PCI_CONFIG_BUS_SPACE); 585 if (sc->sc_pci_cfgt == NULL) 586 panic("%s: could not allocate PCI configuration space tag", 587 __func__); 588 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 589 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr, 590 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 591 panic("%s: could not create PCI DMA tag", __func__); 592 /* Customize the tag. */ 593 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 594 sc->sc_pci_dmat->dt_mt = sc->sc_dma_methods; 595 596 i = OF_getprop(node, "bus-range", (void *)prop_array, 597 sizeof(prop_array)); 598 if (i == -1) 599 panic("%s: could not get bus-range", __func__); 600 if (i != sizeof(prop_array)) 601 panic("%s: broken bus-range (%d)", __func__, i); 602 sc->sc_pci_secbus = prop_array[0]; 603 sc->sc_pci_subbus = prop_array[1]; 604 if (bootverbose) 605 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 606 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 607 608 /* Clear any pending PCI error bits. */ 609 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 610 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 611 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2); 612 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS)); 613 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS)); 614 615 if (osc == NULL) { 616 /* 617 * Establish handlers for interesting interrupts... 618 * 619 * XXX We need to remember these and remove this to support 620 * hotplug on the UPA/FHC bus. 621 * 622 * XXX Not all controllers have these, but installing them 623 * is better than trying to sort through this mess. 624 */ 625 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); 626 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); 627 switch (psycho_powerfail) { 628 case 0: 629 break; 630 case 2: 631 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, 632 psycho_powerdebug, NULL); 633 break; 634 default: 635 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, 636 psycho_powerdown); 637 break; 638 } 639 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 640 /* 641 * Hummingbirds/Sabres do not have the following two 642 * interrupts. 643 */ 644 645 /* 646 * The spare hardware interrupt is used for the 647 * over-temperature interrupt. 648 */ 649 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, NULL, 650 psycho_overtemp); 651#ifdef PSYCHO_MAP_WAKEUP 652 /* 653 * psycho_wakeup() doesn't do anything useful right 654 * now. 655 */ 656 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, 657 psycho_wakeup, NULL); 658#endif /* PSYCHO_MAP_WAKEUP */ 659 } 660 } 661 /* 662 * Register a PCI bus error interrupt handler according to which 663 * half this is. Hummingbird/Sabre don't have a PCI bus B error 664 * interrupt but they are also only used for PCI bus A. 665 */ 666 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 667 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); 668 669 /* 670 * Set the latency timer register as this isn't always done by the 671 * firmware. 672 */ 673 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 674 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 675 676 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t)) 677 le16enc(&sc->sc_pci_hpbcfg[i], bus_space_read_2( 678 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG], 679 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE, 680 PCS_FUNC, i))); 681 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t)) 682 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_pci_cfgt, 683 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF( 684 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i)); 685 686 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 687 /* 688 * On E250 the interrupt map entry for the EBus bridge is wrong, 689 * causing incorrect interrupts to be assigned to some devices on 690 * the EBus. Work around it by changing our copy of the interrupt 691 * map mask to perform a full comparison of the INO. That way 692 * the interrupt map entry for the EBus bridge won't match at all 693 * and the INOs specified in the "interrupts" properties of the 694 * EBus devices will be used directly instead. 695 */ 696 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 697 sc->sc_pci_iinfo.opi_imapmsk != NULL) 698 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 699 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 700 701 device_add_child(dev, "pci", -1); 702 return (bus_generic_attach(dev)); 703} 704 705static void 706psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap, 707 driver_filter_t filt, driver_intr_t intr) 708{ 709 u_long vec; 710 int rid; 711 712 rid = index; 713 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 714 SYS_RES_IRQ, &rid, RF_ACTIVE); 715 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) { 716 /* 717 * These interrupts aren't mandatory and not available 718 * with all controllers (not even Psychos). 719 */ 720 return; 721 } 722 if (sc->sc_irq_res[index] == NULL || 723 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != 724 sc->sc_ign || 725 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec || 726 intr_vectors[vec].iv_ic != &psycho_ic || 727 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 728 INTR_TYPE_MISC | INTR_BRIDGE, filt, intr, sc, 729 &sc->sc_ihand[index]) != 0) 730 panic("%s: failed to set up interrupt %d", __func__, index); 731} 732 733static int 734psycho_find_intrmap(struct psycho_softc *sc, u_int ino, 735 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 736{ 737 bus_addr_t intrclr, intrmap; 738 uint64_t diag; 739 int found; 740 741 /* 742 * XXX we only compare INOs rather than INRs since the firmware may 743 * not provide the IGN and the IGN is constant for all devices on 744 * that PCI controller. 745 * This could cause problems for the FFB/external interrupt which 746 * has a full vector that can be set arbitrarily. 747 */ 748 749 if (ino > PSYCHO_MAX_INO) { 750 device_printf(sc->sc_dev, "out of range INO %d requested\n", 751 ino); 752 return (0); 753 } 754 755 found = 0; 756 /* Hunt through OBIO first. */ 757 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 758 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 759 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8, 760 diag >>= 2) { 761 if (sc->sc_mode == PSYCHO_MODE_SABRE && 762 (intrmap == PSR_TIMER0_INT_MAP || 763 intrmap == PSR_TIMER1_INT_MAP || 764 intrmap == PSR_PCIBERR_INT_MAP || 765 intrmap == PSR_PWRMGT_INT_MAP)) 766 continue; 767 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) { 768 diag &= 2; 769 found = 1; 770 break; 771 } 772 } 773 774 if (!found) { 775 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 776 /* Now do PCI interrupts. */ 777 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 778 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 779 diag >>= 8) { 780 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 781 (intrmap == PSR_PCIA2_INT_MAP || 782 intrmap == PSR_PCIA3_INT_MAP)) 783 continue; 784 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) { 785 intrclr += 8 * (ino & 3); 786 diag = (diag >> ((ino & 3) * 2)) & 2; 787 found = 1; 788 break; 789 } 790 } 791 } 792 if (intrmapptr != NULL) 793 *intrmapptr = intrmap; 794 if (intrclrptr != NULL) 795 *intrclrptr = intrclr; 796 if (intrdiagptr != NULL) 797 *intrdiagptr = diag; 798 return (found); 799} 800 801/* 802 * Interrupt handlers 803 */ 804static int 805psycho_ue(void *arg) 806{ 807 struct psycho_softc *sc = arg; 808 uint64_t afar, afsr; 809 810 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 811 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 812 /* 813 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 814 * the AFAR to be set to the physical address of the TTE entry that 815 * was invalid/write protected. Call into the IOMMU code to have 816 * them decoded to virtual I/O addresses. 817 */ 818 if ((afsr & UEAFSR_P_DTE) != 0) 819 iommu_decode_fault(sc->sc_is, afar); 820 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 821 device_get_nameunit(sc->sc_dev), (u_long)afar, (u_long)afsr); 822 return (FILTER_HANDLED); 823} 824 825static int 826psycho_ce(void *arg) 827{ 828 struct psycho_softc *sc = arg; 829 uint64_t afar, afsr; 830 831 mtx_lock_spin(sc->sc_mtx); 832 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 833 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 834 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 835 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 836 /* Clear the error bits that we caught. */ 837 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr); 838 mtx_unlock_spin(sc->sc_mtx); 839 return (FILTER_HANDLED); 840} 841 842static int 843psycho_pci_bus(void *arg) 844{ 845 struct psycho_softc *sc = arg; 846 uint64_t afar, afsr; 847 848 afar = PCICTL_READ8(sc, PCR_AFA); 849 afsr = PCICTL_READ8(sc, PCR_AFS); 850 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 851 device_get_nameunit(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 852 (u_long)afsr); 853 return (FILTER_HANDLED); 854} 855 856static int 857psycho_powerdebug(void *arg __unused) 858{ 859 860 kdb_enter(KDB_WHY_POWERFAIL, "powerfail"); 861 return (FILTER_HANDLED); 862} 863 864static void 865psycho_powerdown(void *arg __unused) 866{ 867 static int shutdown; 868 869 /* As the interrupt is cleared we may be called multiple times. */ 870 if (shutdown != 0) 871 return; 872 shutdown++; 873 printf("Power Failure Detected: Shutting down NOW.\n"); 874 shutdown_nice(RB_POWEROFF); 875} 876 877static void 878psycho_overtemp(void *arg __unused) 879{ 880 static int shutdown; 881 882 /* As the interrupt is cleared we may be called multiple times. */ 883 if (shutdown != 0) 884 return; 885 shutdown++; 886 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 887 shutdown_nice(RB_POWEROFF); 888} 889 890#ifdef PSYCHO_MAP_WAKEUP 891static int 892psycho_wakeup(void *arg) 893{ 894 struct psycho_softc *sc = arg; 895 896 /* We don't really have a framework to deal with this properly. */ 897 device_printf(sc->sc_dev, "power management wakeup\n"); 898 return (FILTER_HANDLED); 899} 900#endif /* PSYCHO_MAP_WAKEUP */ 901 902static void 903psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 904{ 905 struct iommu_state *is = sc->sc_is; 906 907 /* Punch in our copies. */ 908 is->is_bustag = rman_get_bustag(sc->sc_mem_res); 909 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res); 910 is->is_iommu = PSR_IOMMU; 911 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 912 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 913 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 914 is->is_dva = PSR_IOMMU_SVADIAG; 915 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 916 917 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0); 918} 919 920static int 921psycho_maxslots(device_t dev) 922{ 923 924 /* XXX: is this correct? */ 925 return (PCI_SLOTMAX); 926} 927 928static uint32_t 929psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 930 int width) 931{ 932 struct psycho_softc *sc; 933 bus_space_handle_t bh; 934 u_long offset = 0; 935 uint8_t byte; 936 uint16_t shrt; 937 uint32_t r, wrd; 938 int i; 939 940 sc = device_get_softc(dev); 941 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 942 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 943 return (-1); 944 945 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 946 947 /* 948 * The Hummingbird and Sabre bridges are picky in that they 949 * only allow their config space to be accessed using the 950 * "native" width of the respective register being accessed 951 * and return semi-random other content of their config space 952 * otherwise. Given that the PCI specs don't say anything 953 * about such a (unusual) limitation and lots of stuff expects 954 * to be able to access the contents of the config space at 955 * any width we allow just that. We do this by using a copy 956 * of the header of the bridge (the rest is all zero anyway) 957 * read during attach (expect for PCIR_STATUS) in order to 958 * simplify things. 959 * The Psycho bridges contain a dupe of their header at 0x80 960 * which we nullify that way also. 961 */ 962 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE && 963 func == PCS_FUNC) { 964 if (offset % width != 0) 965 return (-1); 966 967 if (reg >= sizeof(sc->sc_pci_hpbcfg)) 968 return (0); 969 970 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) || 971 reg == PCIR_STATUS || reg == PCIR_STATUS + 1) 972 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS], 973 bus_space_read_2(sc->sc_pci_cfgt, bh, 974 PSYCHO_CONF_OFF(sc->sc_pci_secbus, 975 PCS_DEVICE, PCS_FUNC, PCIR_STATUS))); 976 977 switch (width) { 978 case 1: 979 return (sc->sc_pci_hpbcfg[reg]); 980 case 2: 981 return (le16dec(&sc->sc_pci_hpbcfg[reg])); 982 case 4: 983 return (le32dec(&sc->sc_pci_hpbcfg[reg])); 984 } 985 } 986 987 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 988 switch (width) { 989 case 1: 990 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 991 r = byte; 992 break; 993 case 2: 994 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 995 r = shrt; 996 break; 997 case 4: 998 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 999 r = wrd; 1000 break; 1001 default: 1002 panic("%s: bad width", __func__); 1003 /* NOTREACHED */ 1004 } 1005 1006 if (i) { 1007#ifdef PSYCHO_DEBUG 1008 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 1009 __func__, bus, slot, func, reg); 1010#endif 1011 r = -1; 1012 } 1013 return (r); 1014} 1015 1016static void 1017psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1018 u_int reg, uint32_t val, int width) 1019{ 1020 struct psycho_softc *sc; 1021 bus_space_handle_t bh; 1022 u_long offset = 0; 1023 1024 sc = device_get_softc(dev); 1025 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1026 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1027 return; 1028 1029 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 1030 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1031 switch (width) { 1032 case 1: 1033 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1034 break; 1035 case 2: 1036 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1037 break; 1038 case 4: 1039 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1040 break; 1041 default: 1042 panic("%s: bad width", __func__); 1043 /* NOTREACHED */ 1044 } 1045} 1046 1047static int 1048psycho_route_interrupt(device_t bridge, device_t dev, int pin) 1049{ 1050 struct psycho_softc *sc; 1051 struct ofw_pci_register reg; 1052 bus_addr_t intrmap; 1053 ofw_pci_intr_t pintr, mintr; 1054 1055 sc = device_get_softc(bridge); 1056 pintr = pin; 1057 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1058 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1059 NULL)) 1060 return (mintr); 1061 /* 1062 * If this is outside of the range for an intpin, it's likely a full 1063 * INO, and no mapping is required at all; this happens on the U30, 1064 * where there's no interrupt map at the Psycho node. Fortunately, 1065 * there seem to be no INOs in the intpin range on this boxen, so 1066 * this easy heuristics will do. 1067 */ 1068 if (pin > 4) 1069 return (pin); 1070 /* 1071 * Guess the INO; we always assume that this is a non-OBIO 1072 * device, and that pin is a "real" intpin number. Determine 1073 * the mapping register to be used by the slot number. 1074 * We only need to do this on E450s, it seems; here, the slot numbers 1075 * for bus A are one-based, while those for bus B seemingly have an 1076 * offset of 2 (hence the factor of 3 below). 1077 */ 1078 intrmap = PSR_PCIA0_INT_MAP + 1079 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 1080 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 1081 device_printf(bridge, 1082 "guessing interrupt %d for device %d.%d pin %d\n", 1083 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 1084 return (mintr); 1085} 1086 1087static int 1088psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1089{ 1090 struct psycho_softc *sc; 1091 1092 sc = device_get_softc(dev); 1093 switch (which) { 1094 case PCIB_IVAR_DOMAIN: 1095 *result = device_get_unit(dev); 1096 return (0); 1097 case PCIB_IVAR_BUS: 1098 *result = sc->sc_pci_secbus; 1099 return (0); 1100 } 1101 return (ENOENT); 1102} 1103 1104static void 1105sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1106{ 1107 struct iommu_state *is = dt->dt_cookie; 1108 1109 if ((map->dm_flags & DMF_LOADED) == 0) 1110 return; 1111 1112 if ((op & BUS_DMASYNC_POSTREAD) != 0) 1113 (void)bus_space_read_8(is->is_bustag, is->is_bushandle, 1114 PSR_DMA_WRITE_SYNC); 1115 1116 if ((op & BUS_DMASYNC_PREWRITE) != 0) 1117 membar(Sync); 1118} 1119 1120static void 1121psycho_intr_enable(void *arg) 1122{ 1123 struct intr_vector *iv = arg; 1124 struct psycho_icarg *pica = iv->iv_icarg; 1125 1126 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, 1127 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1128} 1129 1130static void 1131psycho_intr_disable(void *arg) 1132{ 1133 struct intr_vector *iv = arg; 1134 struct psycho_icarg *pica = iv->iv_icarg; 1135 1136 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec); 1137} 1138 1139static void 1140psycho_intr_assign(void *arg) 1141{ 1142 struct intr_vector *iv = arg; 1143 struct psycho_icarg *pica = iv->iv_icarg; 1144 1145 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID( 1146 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid)); 1147} 1148 1149static void 1150psycho_intr_clear(void *arg) 1151{ 1152 struct intr_vector *iv = arg; 1153 struct psycho_icarg *pica = iv->iv_icarg; 1154 1155 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, INTCLR_IDLE); 1156} 1157 1158static int 1159psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 1160 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1161 void **cookiep) 1162{ 1163 struct psycho_softc *sc; 1164 u_long vec; 1165 1166 sc = device_get_softc(dev); 1167 /* 1168 * Make sure the vector is fully specified and we registered 1169 * our interrupt controller for it. 1170 */ 1171 vec = rman_get_start(ires); 1172 if (INTIGN(vec) != sc->sc_ign || 1173 intr_vectors[vec].iv_ic != &psycho_ic) { 1174 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1175 return (EINVAL); 1176 } 1177 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1178 arg, cookiep)); 1179} 1180 1181static struct resource * 1182psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1183 u_long start, u_long end, u_long count, u_int flags) 1184{ 1185 struct psycho_softc *sc; 1186 struct resource *rv; 1187 struct rman *rm; 1188 1189 sc = device_get_softc(bus); 1190 switch (type) { 1191 case SYS_RES_IRQ: 1192 /* 1193 * XXX: Don't accept blank ranges for now, only single 1194 * interrupts. The other case should not happen with 1195 * the MI PCI code... 1196 * XXX: This may return a resource that is out of the 1197 * range that was specified. Is this correct...? 1198 */ 1199 if (start != end) 1200 panic("%s: XXX: interrupt range", __func__); 1201 start = end = INTMAP_VEC(sc->sc_ign, end); 1202 return (bus_generic_alloc_resource(bus, child, type, rid, 1203 start, end, count, flags)); 1204 case SYS_RES_MEMORY: 1205 rm = &sc->sc_pci_mem_rman; 1206 break; 1207 case SYS_RES_IOPORT: 1208 rm = &sc->sc_pci_io_rman; 1209 break; 1210 default: 1211 return (NULL); 1212 } 1213 1214 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 1215 child); 1216 if (rv == NULL) 1217 return (NULL); 1218 rman_set_rid(rv, *rid); 1219 1220 if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type, 1221 *rid, rv) != 0) { 1222 rman_release_resource(rv); 1223 return (NULL); 1224 } 1225 return (rv); 1226} 1227 1228static int 1229psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1230 struct resource *r) 1231{ 1232 struct psycho_softc *sc; 1233 struct bus_space_tag *tag; 1234 1235 sc = device_get_softc(bus); 1236 switch (type) { 1237 case SYS_RES_IRQ: 1238 return (bus_generic_activate_resource(bus, child, type, rid, 1239 r)); 1240 case SYS_RES_MEMORY: 1241 tag = sparc64_alloc_bus_tag(r, PCI_MEMORY_BUS_SPACE); 1242 if (tag == NULL) 1243 return (ENOMEM); 1244 rman_set_bustag(r, tag); 1245 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] + 1246 rman_get_start(r)); 1247 break; 1248 case SYS_RES_IOPORT: 1249 rman_set_bustag(r, sc->sc_pci_iot); 1250 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] + 1251 rman_get_start(r)); 1252 break; 1253 } 1254 return (rman_activate_resource(r)); 1255} 1256 1257static int 1258psycho_adjust_resource(device_t bus, device_t child, int type, 1259 struct resource *r, u_long start, u_long end) 1260{ 1261 struct psycho_softc *sc; 1262 struct rman *rm; 1263 1264 sc = device_get_softc(bus); 1265 switch (type) { 1266 case SYS_RES_IRQ: 1267 return (bus_generic_adjust_resource(bus, child, type, r, 1268 start, end)); 1269 case SYS_RES_MEMORY: 1270 rm = &sc->sc_pci_mem_rman; 1271 break; 1272 case SYS_RES_IOPORT: 1273 rm = &sc->sc_pci_io_rman; 1274 break; 1275 default: 1276 return (EINVAL); 1277 } 1278 if (rman_is_region_manager(r, rm) == 0) 1279 return (EINVAL); 1280 return (rman_adjust_resource(r, start, end)); 1281} 1282 1283static bus_dma_tag_t 1284psycho_get_dma_tag(device_t bus, device_t child __unused) 1285{ 1286 struct psycho_softc *sc; 1287 1288 sc = device_get_softc(bus); 1289 return (sc->sc_pci_dmat); 1290} 1291 1292static phandle_t 1293psycho_get_node(device_t bus, device_t child __unused) 1294{ 1295 struct psycho_softc *sc; 1296 1297 sc = device_get_softc(bus); 1298 /* We only have one child, the PCI bus, which needs our own node. */ 1299 return (sc->sc_node); 1300} 1301 1302static void 1303psycho_setup_device(device_t bus, device_t child) 1304{ 1305 struct psycho_softc *sc; 1306 uint32_t rev; 1307 1308 sc = device_get_softc(bus); 1309 /* 1310 * Revision 0 EBus bridges have a bug which prevents them from 1311 * working when bus parking is enabled. 1312 */ 1313 if ((strcmp(ofw_bus_get_name(child), "ebus") == 0 || 1314 strcmp(ofw_bus_get_name(child), "pci108e,1000") == 0) && 1315 OF_getprop(ofw_bus_get_node(child), "revision-id", &rev, 1316 sizeof(rev)) > 0 && rev == 0) 1317 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS) & 1318 ~PCICTL_ARB_PARK); 1319} 1320