psycho.c revision 131376
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 131376 2004-06-30 23:21:07Z marius $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#define __RMAN_RESOURCE_VISIBLE 40#include "opt_ofw_pci.h" 41#include "opt_psycho.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/bus.h> 46#include <sys/kernel.h> 47#include <sys/module.h> 48#include <sys/malloc.h> 49#include <sys/pcpu.h> 50 51#include <dev/ofw/openfirm.h> 52#include <dev/ofw/ofw_pci.h> 53 54#include <machine/bus.h> 55#include <machine/bus_private.h> 56#include <machine/iommureg.h> 57#include <machine/bus_common.h> 58#include <machine/frame.h> 59#include <machine/intr_machdep.h> 60#include <machine/nexusvar.h> 61#include <machine/ofw_bus.h> 62#include <machine/ofw_upa.h> 63#include <machine/resource.h> 64 65#include <sys/rman.h> 66 67#include <machine/iommuvar.h> 68 69#include <dev/pci/pcivar.h> 70#include <dev/pci/pcireg.h> 71 72#include <sparc64/pci/ofw_pci.h> 73#include <sparc64/pci/psychoreg.h> 74#include <sparc64/pci/psychovar.h> 75 76#include "pcib_if.h" 77 78static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 79 int, driver_intr_t); 80static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 81 bus_addr_t *, u_long *); 82static void psycho_intr_stub(void *); 83static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 84 85/* Interrupt handlers */ 86static void psycho_ue(void *); 87static void psycho_ce(void *); 88static void psycho_bus_a(void *); 89static void psycho_bus_b(void *); 90static void psycho_powerfail(void *); 91#ifdef PSYCHO_MAP_WAKEUP 92static void psycho_wakeup(void *); 93#endif 94 95/* IOMMU support */ 96static void psycho_iommu_init(struct psycho_softc *, int); 97 98/* 99 * Methods. 100 */ 101static device_probe_t psycho_probe; 102static device_attach_t psycho_attach; 103static bus_read_ivar_t psycho_read_ivar; 104static bus_setup_intr_t psycho_setup_intr; 105static bus_teardown_intr_t psycho_teardown_intr; 106static bus_alloc_resource_t psycho_alloc_resource; 107static bus_activate_resource_t psycho_activate_resource; 108static bus_deactivate_resource_t psycho_deactivate_resource; 109static bus_release_resource_t psycho_release_resource; 110static pcib_maxslots_t psycho_maxslots; 111static pcib_read_config_t psycho_read_config; 112static pcib_write_config_t psycho_write_config; 113static pcib_route_interrupt_t psycho_route_interrupt; 114static ofw_pci_intr_pending_t psycho_intr_pending; 115static ofw_pci_get_bus_handle_t psycho_get_bus_handle; 116static ofw_pci_get_node_t psycho_get_node; 117static ofw_pci_adjust_busrange_t psycho_adjust_busrange; 118 119static device_method_t psycho_methods[] = { 120 /* Device interface */ 121 DEVMETHOD(device_probe, psycho_probe), 122 DEVMETHOD(device_attach, psycho_attach), 123 124 /* Bus interface */ 125 DEVMETHOD(bus_print_child, bus_generic_print_child), 126 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 127 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 128 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 129 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 130 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 131 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 132 DEVMETHOD(bus_release_resource, psycho_release_resource), 133 134 /* pcib interface */ 135 DEVMETHOD(pcib_maxslots, psycho_maxslots), 136 DEVMETHOD(pcib_read_config, psycho_read_config), 137 DEVMETHOD(pcib_write_config, psycho_write_config), 138 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 139 140 /* ofw_pci interface */ 141 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 142 DEVMETHOD(ofw_pci_get_bus_handle, psycho_get_bus_handle), 143 DEVMETHOD(ofw_pci_get_node, psycho_get_node), 144 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange), 145 146 { 0, 0 } 147}; 148 149static driver_t psycho_driver = { 150 "pcib", 151 psycho_methods, 152 sizeof(struct psycho_softc), 153}; 154 155static devclass_t psycho_devclass; 156 157DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 158 159SLIST_HEAD(, psycho_softc) psycho_softcs = 160 SLIST_HEAD_INITIALIZER(psycho_softcs); 161 162struct psycho_clr { 163 struct psycho_softc *pci_sc; 164 bus_addr_t pci_clr; /* clear register */ 165 driver_intr_t *pci_handler; /* handler to call */ 166 void *pci_arg; /* argument for the handler */ 167 void *pci_cookie; /* interrupt cookie of parent bus */ 168}; 169 170struct psycho_strayclr { 171 struct psycho_softc *psc_sc; 172 bus_addr_t psc_clr; /* clear register */ 173}; 174 175#define PSYCHO_READ8(sc, off) \ 176 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 177#define PSYCHO_WRITE8(sc, off, v) \ 178 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 179#define PCICTL_READ8(sc, off) \ 180 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 181#define PCICTL_WRITE8(sc, off, v) \ 182 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 183 184/* 185 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 186 * single PCI bus and does not have a streaming buffer. It often has an APB 187 * (advanced PCI bridge) connected to it, which was designed specifically for 188 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 189 * appears as two "simba"'s underneath the sabre. 190 * 191 * "psycho" and "psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 192 * and manage two PCI buses. "psycho" has two 64-bit 33MHz buses, while 193 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 194 * will usually find a "psycho+" since I don't think the original "psycho" 195 * ever shipped, and if it did it would be in the U30. 196 * 197 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 198 * both part of the same IC, they only have a single register space. As such, 199 * they need to be configured together, even though the autoconfiguration will 200 * attach them separately. 201 * 202 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 203 * as pci1 and pci2, although they have been implemented with other PCI bus 204 * numbers on some machines. 205 * 206 * On UltraII machines, there can be any number of "psycho+" ICs, each 207 * providing two PCI buses. 208 */ 209#ifdef DEBUGGER_ON_POWERFAIL 210#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST 211#else 212#define PSYCHO_PWRFAIL_INT_FLAGS 0 213#endif 214 215#define OFW_PCI_TYPE "pci" 216 217struct psycho_desc { 218 char *pd_string; 219 int pd_mode; 220 char *pd_name; 221}; 222 223static struct psycho_desc psycho_compats[] = { 224 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 225 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" }, 226 { "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" }, 227 { NULL, 0, NULL } 228}; 229 230static struct psycho_desc psycho_models[] = { 231 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 232 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 233 { NULL, 0, NULL } 234}; 235 236static struct psycho_desc * 237psycho_find_desc(struct psycho_desc *table, char *string) 238{ 239 struct psycho_desc *desc; 240 241 for (desc = table; desc->pd_string != NULL; desc++) { 242 if (strcmp(desc->pd_string, string) == 0) 243 return (desc); 244 } 245 return (NULL); 246} 247 248static struct psycho_desc * 249psycho_get_desc(phandle_t node, char *model) 250{ 251 struct psycho_desc *rv; 252 char compat[32]; 253 254 rv = NULL; 255 if (model != NULL) 256 rv = psycho_find_desc(psycho_models, model); 257 if (rv == NULL && 258 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 259 rv = psycho_find_desc(psycho_compats, compat); 260 return (rv); 261} 262 263static int 264psycho_probe(device_t dev) 265{ 266 phandle_t node; 267 char *dtype; 268 269 node = nexus_get_node(dev); 270 dtype = nexus_get_device_type(dev); 271 if (nexus_get_reg(dev) != NULL && dtype != NULL && 272 strcmp(dtype, OFW_PCI_TYPE) == 0 && 273 psycho_get_desc(node, nexus_get_model(dev)) != NULL) { 274 device_set_desc(dev, "U2P UPA-PCI bridge"); 275 return (0); 276 } 277 278 return (ENXIO); 279} 280 281static int 282psycho_attach(device_t dev) 283{ 284 struct psycho_softc *sc; 285 struct psycho_softc *osc = NULL; 286 struct psycho_softc *asc; 287 struct upa_regs *reg; 288 struct psycho_desc *desc; 289 phandle_t node; 290 u_int64_t csr; 291 u_long mlen; 292 int psycho_br[2]; 293 int n, i, nreg, rid; 294#ifdef PSYCHO_DEBUG 295 bus_addr_t map, clr; 296 u_int64_t mr; 297#endif 298 299 node = nexus_get_node(dev); 300 sc = device_get_softc(dev); 301 desc = psycho_get_desc(node, nexus_get_model(dev)); 302 303 sc->sc_node = node; 304 sc->sc_dev = dev; 305 sc->sc_dmatag = nexus_get_dmatag(dev); 306 sc->sc_mode = desc->pd_mode; 307 308 /* 309 * The psycho gets three register banks: 310 * (0) per-PBM configuration and status registers 311 * (1) per-PBM PCI configuration space, containing only the 312 * PBM 256-byte PCI header 313 * (2) the shared psycho configuration registers 314 */ 315 reg = nexus_get_reg(dev); 316 nreg = nexus_get_nreg(dev); 317 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 318 if (nreg <= 2) 319 panic("psycho_attach: %d not enough registers", nreg); 320 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[2]); 321 mlen = UPA_REG_SIZE(®[2]); 322 sc->sc_pcictl = UPA_REG_PHYS(®[0]) - sc->sc_basepaddr; 323 switch (sc->sc_pcictl) { 324 case PSR_PCICTL0: 325 sc->sc_half = 0; 326 break; 327 case PSR_PCICTL1: 328 sc->sc_half = 1; 329 break; 330 default: 331 panic("psycho_attach: bogus pci control register " 332 "location"); 333 } 334 } else { 335 if (nreg <= 0) 336 panic("psycho_attach: %d not enough registers", nreg); 337 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[0]); 338 mlen = UPA_REG_SIZE(reg); 339 sc->sc_pcictl = PSR_PCICTL0; 340 sc->sc_half = 0; 341 } 342 343 /* 344 * Match other psycho's that are already configured against 345 * the base physical address. This will be the same for a 346 * pair of devices that share register space. 347 */ 348 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 349 if (asc->sc_basepaddr == sc->sc_basepaddr) { 350 /* Found partner */ 351 osc = asc; 352 break; 353 } 354 } 355 356 if (osc == NULL) { 357 rid = 0; 358 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 359 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 360 RF_ACTIVE); 361 if (sc->sc_mem_res == NULL || 362 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 363 panic("psycho_attach: can't allocate device memory"); 364 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 365 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 366 } else { 367 /* 368 * There's another psycho using the same register space. Copy the 369 * relevant stuff. 370 */ 371 sc->sc_mem_res = NULL; 372 sc->sc_bustag = osc->sc_bustag; 373 sc->sc_bushandle = osc->sc_bushandle; 374 } 375 csr = PSYCHO_READ8(sc, PSR_CS); 376 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 377 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 378 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 379 380 device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n", 381 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 382 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign, 'A' + sc->sc_half); 383 384 /* Setup the PCI control register. */ 385 csr = PCICTL_READ8(sc, PCR_CS); 386 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 387 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 388 PCICTL_RTRYWAIT); 389 PCICTL_WRITE8(sc, PCR_CS, csr); 390 391 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 392 /* Use the PROM preset for now. */ 393 csr = PCICTL_READ8(sc, PCR_TAS); 394 if (csr == 0) 395 panic("psycho_attach: sabre TAS not initialized."); 396 sc->sc_dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 397 } else 398 sc->sc_dvmabase = -1; 399 400 /* Initialize memory and i/o rmans */ 401 sc->sc_io_rman.rm_type = RMAN_ARRAY; 402 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 403 if (rman_init(&sc->sc_io_rman) != 0 || 404 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 405 panic("psycho_probe: failed to set up i/o rman"); 406 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 407 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 408 if (rman_init(&sc->sc_mem_rman) != 0 || 409 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 410 panic("psycho_probe: failed to set up memory rman"); 411 412 sc->sc_nrange = OF_getprop_alloc(sc->sc_node, "ranges", 413 sizeof(*sc->sc_range), (void **)&sc->sc_range); 414 if (sc->sc_nrange == -1) 415 panic("could not get psycho ranges"); 416 /* 417 * Find the addresses of the various bus spaces. 418 * There should not be multiple ones of one kind. 419 * The physical start addresses of the ranges are the configuration, 420 * memory and IO handles. 421 */ 422 for (n = 0; n < sc->sc_nrange; n++) { 423 i = UPA_RANGE_CS(&sc->sc_range[n]); 424 if (sc->sc_bh[i] != 0) 425 panic("psycho_attach: duplicate range for space %d", i); 426 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 427 } 428 /* 429 * Check that all needed handles are present. The PCI_CS_MEM64 one is 430 * not currently used. 431 */ 432 for (n = 0; n < 3; n++) { 433 if (sc->sc_bh[n] == 0) 434 panic("psycho_attach: range %d missing", n); 435 } 436 437 /* Register the softc, this is needed for paired psychos. */ 438 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 439 440 /* 441 * If we're a sabre or the first of a pair of psycho's to arrive here, 442 * start up the IOMMU. 443 */ 444 if (osc == NULL) { 445 /* 446 * Establish handlers for interesting interrupts.... 447 * 448 * XXX We need to remember these and remove this to support 449 * hotplug on the UPA/FHC bus. 450 * 451 * XXX Not all controllers have these, but installing them 452 * is better than trying to sort through this mess. 453 */ 454 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 455 psycho_ue); 456 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 457 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 458 psycho_bus_a); 459 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, 460 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 461 /* Psycho-specific initialization. */ 462 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 463 /* 464 * Sabres do not have the following two interrupts. 465 */ 466 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 467 INTR_FAST, psycho_bus_b); 468#ifdef PSYCHO_MAP_WAKEUP 469 /* 470 * psycho_wakeup() doesn't do anything useful right 471 * now. 472 */ 473 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 474 psycho_wakeup); 475#endif /* PSYCHO_MAP_WAKEUP */ 476 477 /* Initialize the counter-timer. */ 478 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 479 PSR_TC0); 480 } 481 482 /* 483 * Setup IOMMU and PCI configuration if we're the first 484 * of a pair of psycho's to arrive here. 485 * 486 * We should calculate a TSB size based on amount of RAM 487 * and number of bus controllers and number and type of 488 * child devices. 489 * 490 * For the moment, 32KB should be more than enough. 491 */ 492 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 493 M_NOWAIT); 494 if (sc->sc_is == NULL) 495 panic("psycho_attach: malloc iommu_state failed"); 496 sc->sc_is->is_sb[0] = 0; 497 sc->sc_is->is_sb[1] = 0; 498 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 499 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 500 psycho_iommu_init(sc, 3); 501 } else { 502 /* Just copy IOMMU state, config tag and address */ 503 sc->sc_is = osc->sc_is; 504 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 505 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 506 iommu_reset(sc->sc_is); 507 } 508 509 /* Allocate our tags. */ 510 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 511 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 512 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 513 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 514 0x3ffffffff, 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_dmat) != 0) 515 panic("psycho_attach: bus_dma_tag_create failed"); 516 /* Customize the tag. */ 517 sc->sc_dmat->dt_cookie = sc->sc_is; 518 sc->sc_dmat->dt_mt = &iommu_dma_methods; 519 /* XXX: register as root dma tag (kludge). */ 520 sparc64_root_dma_tag = sc->sc_dmat; 521 522#ifdef PSYCHO_DEBUG 523 /* 524 * Enable all interrupts and clear all interrupt states. 525 * This aids the debugging of interrupt routing problems. 526 */ 527 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 528 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 529 mr = PSYCHO_READ8(sc, map); 530 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 531 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 532 for (i = 0; i < 4; i++) 533 PCICTL_WRITE8(sc, clr + i * 8, 0); 534 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 535 } 536 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 537 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 538 mr = PSYCHO_READ8(sc, map); 539 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 540 (u_long)mr, (u_long)clr); 541 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 542 PSYCHO_WRITE8(sc, clr, 0); 543 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 544 } 545#endif /* PSYCHO_DEBUG */ 546 547 /* 548 * Get the bus range from the firmware; it is used solely for obtaining 549 * the inital bus number, and cannot be trusted on all machines. 550 */ 551 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 552 if (n == -1) 553 panic("could not get psycho bus-range"); 554 if (n != sizeof(psycho_br)) 555 panic("broken psycho bus-range (%d)", n); 556 557 sc->sc_secbus = sc->sc_subbus = ofw_pci_alloc_busno(sc->sc_node); 558 /* 559 * Program the bus range registers. 560 * NOTE: for the psycho, the second write changes the bus number the 561 * psycho itself uses for it's configuration space, so these 562 * writes must be kept in this order! 563 * The sabre always uses bus 0, but there only can be one sabre per 564 * machine. 565 */ 566 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS, 567 sc->sc_subbus, 1); 568 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS, 569 sc->sc_secbus, 1); 570 571 ofw_bus_setup_iinfo(node, &sc->sc_iinfo, sizeof(ofw_pci_intr_t)); 572 573 device_add_child(dev, "pci", sc->sc_secbus); 574 return (bus_generic_attach(dev)); 575} 576 577static void 578psycho_set_intr(struct psycho_softc *sc, int index, 579 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 580{ 581 int rid, vec; 582 u_int64_t mr; 583 584 mr = PSYCHO_READ8(sc, map); 585 vec = INTVEC(mr); 586 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 587 vec, vec, 1, RF_ACTIVE); 588 if (sc->sc_irq_res[index] == NULL) 589 panic("psycho_set_intr: failed to get interrupt"); 590 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 591 handler, sc, &sc->sc_ihand[index]); 592 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 593} 594 595static int 596psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 597 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 598{ 599 bus_addr_t intrmap, intrclr; 600 u_int64_t im; 601 u_long diag; 602 int found; 603 604 found = 0; 605 /* Hunt thru obio first */ 606 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 607 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 608 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 609 diag >>= 2) { 610 im = PSYCHO_READ8(sc, intrmap); 611 if (INTINO(im) == ino) { 612 diag &= 2; 613 found = 1; 614 break; 615 } 616 } 617 618 if (!found) { 619 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 620 /* Now do PCI interrupts */ 621 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 622 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 623 diag >>= 8) { 624 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 625 (intrmap == PSR_PCIA2_INT_MAP || 626 intrmap == PSR_PCIA3_INT_MAP)) 627 continue; 628 im = PSYCHO_READ8(sc, intrmap); 629 if (((im ^ ino) & 0x3c) == 0) { 630 intrclr += 8 * (ino & 3); 631 diag = (diag >> ((ino & 3) * 2)) & 2; 632 found = 1; 633 break; 634 } 635 } 636 } 637 if (intrmapptr != NULL) 638 *intrmapptr = intrmap; 639 if (intrclrptr != NULL) 640 *intrclrptr = intrclr; 641 if (intrdiagptr != NULL) 642 *intrdiagptr = diag; 643 return (found); 644} 645 646/* 647 * Interrupt handlers. 648 */ 649static void 650psycho_ue(void *arg) 651{ 652 struct psycho_softc *sc = (struct psycho_softc *)arg; 653 u_int64_t afar, afsr; 654 655 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 656 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 657 /* 658 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 659 * the AFAR to be set to the physical address of the TTE entry that 660 * was invalid/write protected. Call into the iommu code to have 661 * them decoded to virtual IO addresses. 662 */ 663 if ((afsr & UEAFSR_P_DTE) != 0) 664 iommu_decode_fault(sc->sc_is, afar); 665 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 666 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 667} 668 669static void 670psycho_ce(void *arg) 671{ 672 struct psycho_softc *sc = (struct psycho_softc *)arg; 673 u_int64_t afar, afsr; 674 675 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 676 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 677 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 678 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 679 /* Clear the error bits that we caught. */ 680 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); 681 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 682} 683 684static void 685psycho_bus_a(void *arg) 686{ 687 struct psycho_softc *sc = (struct psycho_softc *)arg; 688 u_int64_t afar, afsr; 689 690 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 691 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 692 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx", 693 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 694} 695 696static void 697psycho_bus_b(void *arg) 698{ 699 struct psycho_softc *sc = (struct psycho_softc *)arg; 700 u_int64_t afar, afsr; 701 702 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 703 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 704 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx", 705 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 706} 707 708static void 709psycho_powerfail(void *arg) 710{ 711 712#ifdef DEBUGGER_ON_POWERFAIL 713 struct psycho_softc *sc = (struct psycho_softc *)arg; 714 715 Debugger("powerfail"); 716 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 717#else 718 printf("Power Failure Detected: Shutting down NOW.\n"); 719 shutdown_nice(0); 720#endif 721} 722 723#ifdef PSYCHO_MAP_WAKEUP 724static void 725psycho_wakeup(void *arg) 726{ 727 struct psycho_softc *sc = (struct psycho_softc *)arg; 728 729 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 730 /* Gee, we don't really have a framework to deal with this properly. */ 731 device_printf(sc->sc_dev, "power management wakeup\n"); 732} 733#endif /* PSYCHO_MAP_WAKEUP */ 734 735void 736psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 737{ 738 char *name; 739 struct iommu_state *is = sc->sc_is; 740 741 /* punch in our copies */ 742 is->is_bustag = sc->sc_bustag; 743 is->is_bushandle = sc->sc_bushandle; 744 is->is_iommu = PSR_IOMMU; 745 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 746 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 747 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 748 is->is_dva = PSR_IOMMU_SVADIAG; 749 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 750 751 /* give us a nice name.. */ 752 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 753 if (name == 0) 754 panic("couldn't malloc iommu name"); 755 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev)); 756 757 iommu_init(name, is, tsbsize, sc->sc_dvmabase, 0); 758} 759 760static int 761psycho_maxslots(device_t dev) 762{ 763 764 /* XXX: is this correct? */ 765 return (PCI_SLOTMAX); 766} 767 768static u_int32_t 769psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 770 int width) 771{ 772 struct psycho_softc *sc; 773 bus_space_handle_t bh; 774 u_long offset = 0; 775 u_int8_t byte; 776 u_int16_t shrt; 777 u_int32_t wrd; 778 u_int32_t r; 779 int i; 780 781 sc = (struct psycho_softc *)device_get_softc(dev); 782 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 783 bh = sc->sc_bh[PCI_CS_CONFIG]; 784 switch (width) { 785 case 1: 786 i = bus_space_peek_1(sc->sc_cfgt, bh, offset, &byte); 787 r = byte; 788 break; 789 case 2: 790 i = bus_space_peek_2(sc->sc_cfgt, bh, offset, &shrt); 791 r = shrt; 792 break; 793 case 4: 794 i = bus_space_peek_4(sc->sc_cfgt, bh, offset, &wrd); 795 r = wrd; 796 break; 797 default: 798 panic("psycho_read_config: bad width"); 799 } 800 801 if (i) { 802#ifdef PSYCHO_DEBUG 803 printf("psycho read data error reading: %d.%d.%d: 0x%x\n", 804 bus, slot, func, reg); 805#endif 806 r = -1; 807 } 808 return (r); 809} 810 811static void 812psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 813 u_int reg, u_int32_t val, int width) 814{ 815 struct psycho_softc *sc; 816 bus_space_handle_t bh; 817 u_long offset = 0; 818 819 sc = (struct psycho_softc *)device_get_softc(dev); 820 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 821 bh = sc->sc_bh[PCI_CS_CONFIG]; 822 switch (width) { 823 case 1: 824 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 825 break; 826 case 2: 827 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 828 break; 829 case 4: 830 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 831 break; 832 default: 833 panic("psycho_write_config: bad width"); 834 } 835} 836 837static int 838psycho_route_interrupt(device_t bridge, device_t dev, int pin) 839{ 840 struct psycho_softc *sc = device_get_softc(bridge); 841 struct ofw_pci_register reg; 842 bus_addr_t intrmap; 843 phandle_t node = ofw_pci_get_node(dev); 844 ofw_pci_intr_t pintr, mintr; 845 u_int8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 846 847 pintr = pin; 848 if (ofw_bus_lookup_imap(node, &sc->sc_iinfo, ®, sizeof(reg), 849 &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 850 return (mintr); 851 /* 852 * If this is outside of the range for an intpin, it's likely a full 853 * INO, and no mapping is required at all; this happens on the u30, 854 * where there's no interrupt map at the psycho node. Fortunately, 855 * there seem to be no INOs in the intpin range on this boxen, so 856 * this easy heuristics will do. 857 */ 858 if (pin > 4) 859 return (pin); 860 /* 861 * Guess the INO; we always assume that this is a non-OBIO 862 * device, and that pin is a "real" intpin number. Determine 863 * the mapping register to be used by the slot number. 864 * We only need to do this on e450s, it seems; here, the slot numbers 865 * for bus A are one-based, while those for bus B seemingly have an 866 * offset of 2 (hence the factor of 3 below). 867 */ 868 intrmap = PSR_PCIA0_INT_MAP + 869 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 870 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 871 device_printf(bridge, "guessing interrupt %d for device %d/%d pin %d\n", 872 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 873 return (mintr); 874} 875 876static int 877psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 878{ 879 struct psycho_softc *sc; 880 881 sc = (struct psycho_softc *)device_get_softc(dev); 882 switch (which) { 883 case PCIB_IVAR_BUS: 884 *result = sc->sc_secbus; 885 return (0); 886 } 887 return (ENOENT); 888} 889 890/* Write to the correct clr register, and call the actual handler. */ 891static void 892psycho_intr_stub(void *arg) 893{ 894 struct psycho_clr *pc; 895 896 pc = (struct psycho_clr *)arg; 897 pc->pci_handler(pc->pci_arg); 898 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 899} 900 901static int 902psycho_setup_intr(device_t dev, device_t child, 903 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 904 void **cookiep) 905{ 906 struct psycho_softc *sc; 907 struct psycho_clr *pc; 908 bus_addr_t intrmapptr, intrclrptr; 909 long vec = rman_get_start(ires); 910 u_int64_t mr; 911 int ino, error; 912 913 sc = (struct psycho_softc *)device_get_softc(dev); 914 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 915 if (pc == NULL) 916 return (0); 917 918 /* 919 * Hunt through all the interrupt mapping regs to look for our 920 * interrupt vector. 921 * 922 * XXX We only compare INOs rather than IGNs since the firmware may 923 * not provide the IGN and the IGN is constant for all devices on that 924 * PCI controller. This could cause problems for the FFB/external 925 * interrupt which has a full vector that can be set arbitrarily. 926 */ 927 ino = INTINO(vec); 928 929 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 930 device_printf(dev, "Cannot find interrupt vector %lx\n", vec); 931 free(pc, M_DEVBUF); 932 return (0); 933 } 934 935#ifdef PSYCHO_DEBUG 936 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 937 ino, (u_long)intrmapptr, (u_long)intrclrptr); 938#endif 939 pc->pci_sc = sc; 940 pc->pci_arg = arg; 941 pc->pci_handler = intr; 942 pc->pci_clr = intrclrptr; 943 /* Disable the interrupt while we fiddle with it */ 944 mr = PSYCHO_READ8(sc, intrmapptr); 945 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 946 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 947 psycho_intr_stub, pc, cookiep); 948 if (error != 0) { 949 free(pc, M_DEVBUF); 950 return (error); 951 } 952 pc->pci_cookie = *cookiep; 953 *cookiep = pc; 954 955 /* 956 * Clear the interrupt, it might have been triggered before it was 957 * set up. 958 */ 959 PSYCHO_WRITE8(sc, intrclrptr, 0); 960 /* 961 * Enable the interrupt and program the target module now we have the 962 * handler installed. 963 */ 964 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 965 return (error); 966} 967 968static int 969psycho_teardown_intr(device_t dev, device_t child, 970 struct resource *vec, void *cookie) 971{ 972 struct psycho_clr *pc; 973 int error; 974 975 pc = (struct psycho_clr *)cookie; 976 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 977 pc->pci_cookie); 978 /* 979 * Don't disable the interrupt for now, so that stray interupts get 980 * detected... 981 */ 982 if (error != 0) 983 free(pc, M_DEVBUF); 984 return (error); 985} 986 987static struct resource * 988psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 989 u_long start, u_long end, u_long count, u_int flags) 990{ 991 struct psycho_softc *sc; 992 struct resource *rv; 993 struct rman *rm; 994 bus_space_tag_t bt; 995 bus_space_handle_t bh; 996 int needactivate = flags & RF_ACTIVE; 997 998 flags &= ~RF_ACTIVE; 999 1000 sc = (struct psycho_softc *)device_get_softc(bus); 1001 if (type == SYS_RES_IRQ) { 1002 /* 1003 * XXX: Don't accept blank ranges for now, only single 1004 * interrupts. The other case should not happen with the MI pci 1005 * code... 1006 * XXX: This may return a resource that is out of the range 1007 * that was specified. Is this correct...? 1008 */ 1009 if (start != end) 1010 panic("psycho_alloc_resource: XXX: interrupt range"); 1011 start = end |= sc->sc_ign; 1012 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1013 rid, start, end, count, flags)); 1014 } 1015 switch (type) { 1016 case SYS_RES_MEMORY: 1017 rm = &sc->sc_mem_rman; 1018 bt = sc->sc_memt; 1019 bh = sc->sc_bh[PCI_CS_MEM32]; 1020 break; 1021 case SYS_RES_IOPORT: 1022 rm = &sc->sc_io_rman; 1023 bt = sc->sc_iot; 1024 bh = sc->sc_bh[PCI_CS_IO]; 1025 break; 1026 default: 1027 return (NULL); 1028 } 1029 1030 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1031 if (rv == NULL) 1032 return (NULL); 1033 1034 bh += rman_get_start(rv); 1035 rman_set_bustag(rv, bt); 1036 rman_set_bushandle(rv, bh); 1037 1038 if (needactivate) { 1039 if (bus_activate_resource(child, type, *rid, rv)) { 1040 rman_release_resource(rv); 1041 return (NULL); 1042 } 1043 } 1044 1045 return (rv); 1046} 1047 1048static int 1049psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1050 struct resource *r) 1051{ 1052 void *p; 1053 int error; 1054 1055 if (type == SYS_RES_IRQ) 1056 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1057 type, rid, r)); 1058 if (type == SYS_RES_MEMORY) { 1059 /* 1060 * Need to memory-map the device space, as some drivers depend 1061 * on the virtual address being set and useable. 1062 */ 1063 error = sparc64_bus_mem_map(rman_get_bustag(r), 1064 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1065 if (error != 0) 1066 return (error); 1067 rman_set_virtual(r, p); 1068 } 1069 return (rman_activate_resource(r)); 1070} 1071 1072static int 1073psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1074 struct resource *r) 1075{ 1076 1077 if (type == SYS_RES_IRQ) 1078 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1079 type, rid, r)); 1080 if (type == SYS_RES_MEMORY) { 1081 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1082 rman_set_virtual(r, NULL); 1083 } 1084 return (rman_deactivate_resource(r)); 1085} 1086 1087static int 1088psycho_release_resource(device_t bus, device_t child, int type, int rid, 1089 struct resource *r) 1090{ 1091 int error; 1092 1093 if (type == SYS_RES_IRQ) 1094 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1095 type, rid, r)); 1096 if (rman_get_flags(r) & RF_ACTIVE) { 1097 error = bus_deactivate_resource(child, type, rid, r); 1098 if (error) 1099 return error; 1100 } 1101 return (rman_release_resource(r)); 1102} 1103 1104static int 1105psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1106{ 1107 struct psycho_softc *sc; 1108 u_long diag; 1109 1110 sc = (struct psycho_softc *)device_get_softc(dev); 1111 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1112 device_printf(dev, "psycho_intr_pending: mapping not found for" 1113 " %d\n", intr); 1114 return (0); 1115 } 1116 return (diag != 0); 1117} 1118 1119static bus_space_handle_t 1120psycho_get_bus_handle(device_t dev, int type, bus_space_handle_t childhdl, 1121 bus_space_tag_t *tag) 1122{ 1123 struct psycho_softc *sc; 1124 1125 sc = (struct psycho_softc *)device_get_softc(dev); 1126 switch (type) { 1127 case SYS_RES_IOPORT: 1128 *tag = sc->sc_iot; 1129 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1130 case SYS_RES_MEMORY: 1131 *tag = sc->sc_memt; 1132 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1133 default: 1134 panic("psycho_get_bus_handle: illegal space\n"); 1135 } 1136} 1137 1138static phandle_t 1139psycho_get_node(device_t bus, device_t dev) 1140{ 1141 struct psycho_softc *sc = device_get_softc(bus); 1142 1143 /* We only have one child, the PCI bus, which needs our own node. */ 1144 return (sc->sc_node); 1145} 1146 1147static void 1148psycho_adjust_busrange(device_t dev, u_int subbus) 1149{ 1150 struct psycho_softc *sc = device_get_softc(dev); 1151 1152 /* If necessary, adjust the subordinate bus number register. */ 1153 if (subbus > sc->sc_subbus) { 1154#ifdef PSYCHO_DEBUG 1155 device_printf(dev, 1156 "adjusting secondary bus number from %d to %d\n", 1157 sc->sc_subbus, subbus); 1158#endif 1159 sc->sc_subbus = subbus; 1160 PCIB_WRITE_CONFIG(dev, sc->sc_secbus, PCS_DEVICE, PCS_FUNC, 1161 PCSR_SUBBUS, subbus, 1); 1162 } 1163} 1164 1165static bus_space_tag_t 1166psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1167{ 1168 bus_space_tag_t bt; 1169 1170 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1171 M_NOWAIT | M_ZERO); 1172 if (bt == NULL) 1173 panic("psycho_alloc_bus_tag: out of memory"); 1174 1175 bzero(bt, sizeof *bt); 1176 bt->bst_cookie = sc; 1177 bt->bst_parent = sc->sc_bustag; 1178 bt->bst_type = type; 1179 return (bt); 1180} 1181