psycho.c revision 108815
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * All rights reserved. 4 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 108815 2003-01-06 19:43:10Z tmm $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_psycho.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46#include <sys/pcpu.h> 47 48#include <ofw/openfirm.h> 49#include <ofw/ofw_pci.h> 50 51#include <machine/bus.h> 52#include <machine/iommureg.h> 53#include <machine/bus_common.h> 54#include <machine/frame.h> 55#include <machine/intr_machdep.h> 56#include <machine/nexusvar.h> 57#include <machine/ofw_upa.h> 58#include <machine/resource.h> 59 60#include <sys/rman.h> 61 62#include <machine/iommuvar.h> 63 64#include <pci/pcivar.h> 65#include <pci/pcireg.h> 66 67#include <sparc64/pci/ofw_pci.h> 68#include <sparc64/pci/psychoreg.h> 69#include <sparc64/pci/psychovar.h> 70 71#include "pcib_if.h" 72#include "sparcbus_if.h" 73 74static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 75static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 76 int, driver_intr_t); 77static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 78 bus_addr_t *, u_long *); 79static void psycho_intr_stub(void *); 80#ifdef PSYCHO_STRAY 81static void psycho_intr_stray(void *); 82#endif 83static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 84 85 86/* Interrupt handlers */ 87static void psycho_ue(void *); 88static void psycho_ce(void *); 89static void psycho_bus_a(void *); 90static void psycho_bus_b(void *); 91static void psycho_powerfail(void *); 92#ifdef PSYCHO_MAP_WAKEUP 93static void psycho_wakeup(void *); 94#endif 95 96/* IOMMU support */ 97static void psycho_iommu_init(struct psycho_softc *, int); 98static ofw_pci_binit_t psycho_binit; 99 100/* 101 * bus space and bus dma support for UltraSPARC `psycho'. note that most 102 * of the bus dma support is provided by the iommu dvma controller. 103 */ 104static int psycho_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, int, 105 bus_dmamap_t *); 106static int psycho_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 107static int psycho_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 108 void *, bus_size_t, bus_dmamap_callback_t *, void *, int); 109static void psycho_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 110static void psycho_dmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 111 bus_dmasync_op_t); 112static int psycho_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, void **, int, 113 bus_dmamap_t *); 114static void psycho_dmamem_free(bus_dma_tag_t, bus_dma_tag_t, void *, 115 bus_dmamap_t); 116 117/* 118 * autoconfiguration 119 */ 120static int psycho_probe(device_t); 121static int psycho_attach(device_t); 122static int psycho_read_ivar(device_t, device_t, int, u_long *); 123static int psycho_setup_intr(device_t, device_t, struct resource *, int, 124 driver_intr_t *, void *, void **); 125static int psycho_teardown_intr(device_t, device_t, struct resource *, void *); 126static struct resource *psycho_alloc_resource(device_t, device_t, int, int *, 127 u_long, u_long, u_long, u_int); 128static int psycho_activate_resource(device_t, device_t, int, int, 129 struct resource *); 130static int psycho_deactivate_resource(device_t, device_t, int, int, 131 struct resource *); 132static int psycho_release_resource(device_t, device_t, int, int, 133 struct resource *); 134static int psycho_maxslots(device_t); 135static u_int32_t psycho_read_config(device_t, u_int, u_int, u_int, u_int, int); 136static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, 137 int); 138static int psycho_route_interrupt(device_t, device_t, int); 139static int psycho_intr_pending(device_t, int); 140static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id, 141 bus_space_handle_t childhdl, bus_space_tag_t *tag); 142 143static device_method_t psycho_methods[] = { 144 /* Device interface */ 145 DEVMETHOD(device_probe, psycho_probe), 146 DEVMETHOD(device_attach, psycho_attach), 147 148 /* Bus interface */ 149 DEVMETHOD(bus_print_child, bus_generic_print_child), 150 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 151 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 152 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 153 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 154 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 155 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 156 DEVMETHOD(bus_release_resource, psycho_release_resource), 157 158 /* pcib interface */ 159 DEVMETHOD(pcib_maxslots, psycho_maxslots), 160 DEVMETHOD(pcib_read_config, psycho_read_config), 161 DEVMETHOD(pcib_write_config, psycho_write_config), 162 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 163 164 /* sparcbus interface */ 165 DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending), 166 DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle), 167 168 { 0, 0 } 169}; 170 171static driver_t psycho_driver = { 172 "pcib", 173 psycho_methods, 174 sizeof(struct psycho_softc), 175}; 176 177static devclass_t psycho_devclass; 178 179DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 180 181SLIST_HEAD(, psycho_softc) psycho_softcs = 182 SLIST_HEAD_INITIALIZER(psycho_softcs); 183 184struct psycho_clr { 185 struct psycho_softc *pci_sc; 186 bus_addr_t pci_clr; /* clear register */ 187 driver_intr_t *pci_handler; /* handler to call */ 188 void *pci_arg; /* argument for the handler */ 189 void *pci_cookie; /* interrupt cookie of parent bus */ 190}; 191 192struct psycho_strayclr { 193 struct psycho_softc *psc_sc; 194 bus_addr_t psc_clr; /* clear register */ 195}; 196 197#define PSYCHO_READ8(sc, off) \ 198 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 199#define PSYCHO_WRITE8(sc, off, v) \ 200 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 201#define PCICTL_READ8(sc, off) \ 202 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 203#define PCICTL_WRITE8(sc, off, v) \ 204 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 205 206/* 207 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 208 * single PCI bus and does not have a streaming buffer. It often has an APB 209 * (advanced PCI bridge) connected to it, which was designed specifically for 210 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 211 * appears as two "simba"'s underneath the sabre. 212 * 213 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 214 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 215 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 216 * will usually find a "psycho+" since I don't think the original "psycho" 217 * ever shipped, and if it did it would be in the U30. 218 * 219 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 220 * both part of the same IC, they only have a single register space. As such, 221 * they need to be configured together, even though the autoconfiguration will 222 * attach them separately. 223 * 224 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 225 * as pci1 and pci2, although they have been implemented with other PCI bus 226 * numbers on some machines. 227 * 228 * On UltraII machines, there can be any number of "psycho+" ICs, each 229 * providing two PCI buses. 230 * 231 * 232 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 233 * the values of the following interrupts in this order: 234 * 235 * PCI Bus Error (30) 236 * DMA UE (2e) 237 * DMA CE (2f) 238 * Power Fail (25) 239 * 240 * We really should attach handlers for each. 241 */ 242#ifdef DEBUGGER_ON_POWERFAIL 243#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST 244#else 245#define PSYCHO_PWRFAIL_INT_FLAGS 0 246#endif 247 248#define OFW_PCI_TYPE "pci" 249 250struct psycho_desc { 251 char *pd_string; 252 int pd_mode; 253 char *pd_name; 254}; 255 256static struct psycho_desc psycho_compats[] = { 257 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 258 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" }, 259 { "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" }, 260 { NULL, 0, NULL } 261}; 262 263static struct psycho_desc psycho_models[] = { 264 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 265 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 266 { NULL, 0, NULL } 267}; 268 269static struct psycho_desc * 270psycho_find_desc(struct psycho_desc *table, char *string) 271{ 272 struct psycho_desc *desc; 273 274 for (desc = table; desc->pd_string != NULL; desc++) { 275 if (strcmp(desc->pd_string, string) == 0) 276 return (desc); 277 } 278 return (NULL); 279} 280 281static struct psycho_desc * 282psycho_get_desc(phandle_t node, char *model) 283{ 284 struct psycho_desc *rv; 285 char compat[32]; 286 287 rv = NULL; 288 if (model != NULL) 289 rv = psycho_find_desc(psycho_models, model); 290 if (rv == NULL && 291 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 292 rv = psycho_find_desc(psycho_compats, compat); 293 return (rv); 294} 295 296static int 297psycho_probe(device_t dev) 298{ 299 phandle_t node; 300 char *dtype; 301 302 node = nexus_get_node(dev); 303 dtype = nexus_get_device_type(dev); 304 if (nexus_get_reg(dev) != NULL && dtype != NULL && 305 strcmp(dtype, OFW_PCI_TYPE) == 0 && 306 psycho_get_desc(node, nexus_get_model(dev)) != NULL) { 307 device_set_desc(dev, "U2P UPA-PCI bridge"); 308 return (0); 309 } 310 311 return (ENXIO); 312} 313 314/* 315 * SUNW,psycho initialisation .. 316 * - find the per-psycho registers 317 * - figure out the IGN. 318 * - find our partner psycho 319 * - configure ourselves 320 * - bus range, bus, 321 * - interrupt map, 322 * - setup the chipsets. 323 * - if we're the first of the pair, initialise the IOMMU, otherwise 324 * just copy it's tags and addresses. 325 */ 326static int 327psycho_attach(device_t dev) 328{ 329 struct psycho_softc *sc; 330 struct psycho_softc *osc = NULL; 331 struct psycho_softc *asc; 332 struct upa_regs *reg; 333 struct ofw_pci_bdesc obd; 334 struct psycho_desc *desc; 335 phandle_t node; 336 u_int64_t csr; 337 u_long pcictl_offs, mlen; 338 int psycho_br[2]; 339 int n, i, nreg, rid; 340#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 341 bus_addr_t map, clr; 342 u_int64_t mr; 343#endif 344#ifdef PSYCHO_STRAY 345 struct psycho_strayclr *sclr; 346#endif 347 348 node = nexus_get_node(dev); 349 sc = device_get_softc(dev); 350 desc = psycho_get_desc(node, nexus_get_model(dev)); 351 352 sc->sc_node = node; 353 sc->sc_dev = dev; 354 sc->sc_dmatag = nexus_get_dmatag(dev); 355 sc->sc_mode = desc->pd_mode; 356 357 /* 358 * The psycho gets three register banks: 359 * (0) per-PBM configuration and status registers 360 * (1) per-PBM PCI configuration space, containing only the 361 * PBM 256-byte PCI header 362 * (2) the shared psycho configuration registers (struct psychoreg) 363 */ 364 reg = nexus_get_reg(dev); 365 nreg = nexus_get_nreg(dev); 366 /* Register layouts are different. stuupid. */ 367 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 368 if (nreg <= 2) 369 panic("psycho_attach: %d not enough registers", nreg); 370 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[2]); 371 mlen = UPA_REG_SIZE(®[2]); 372 pcictl_offs = UPA_REG_PHYS(®[0]); 373 } else { 374 if (nreg <= 0) 375 panic("psycho_attach: %d not enough registers", nreg); 376 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[0]); 377 mlen = UPA_REG_SIZE(reg); 378 pcictl_offs = sc->sc_basepaddr + PSR_PCICTL0; 379 } 380 381 /* 382 * Match other psycho's that are already configured against 383 * the base physical address. This will be the same for a 384 * pair of devices that share register space. 385 */ 386 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 387 if (asc->sc_basepaddr == sc->sc_basepaddr) { 388 /* Found partner */ 389 osc = asc; 390 break; 391 } 392 } 393 394 if (osc == NULL) { 395 rid = 0; 396 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 397 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 398 RF_ACTIVE); 399 if (sc->sc_mem_res == NULL || 400 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 401 panic("psycho_attach: can't allocate device memory"); 402 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 403 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 404 } else { 405 /* 406 * There's another psycho using the same register space. Copy the 407 * relevant stuff. 408 */ 409 sc->sc_mem_res = NULL; 410 sc->sc_bustag = osc->sc_bustag; 411 sc->sc_bushandle = osc->sc_bushandle; 412 } 413 if (pcictl_offs < sc->sc_basepaddr) 414 panic("psycho_attach: bogus pci control register location"); 415 sc->sc_pcictl = pcictl_offs - sc->sc_basepaddr; 416 csr = PSYCHO_READ8(sc, PSR_CS); 417 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 418 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 419 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 420 421 device_printf(dev, "%s, impl %d, version %d, ign %#x\n", 422 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 423 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign); 424 425 /* 426 * Setup the PCI control register 427 */ 428 csr = PCICTL_READ8(sc, PCR_CS); 429 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 430 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 431 PCICTL_RTRYWAIT); 432 PCICTL_WRITE8(sc, PCR_CS, csr); 433 434 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 435 /* 436 * Use the PROM preset for now. 437 */ 438 csr = PCICTL_READ8(sc, PCR_TAS); 439 if (csr == 0) 440 panic("psycho_attach: sabre TAS not initialized."); 441 sc->sc_dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 442 } else 443 sc->sc_dvmabase = -1; 444 445 /* Grab the psycho ranges */ 446 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 447 448 /* Initialize memory and i/o rmans */ 449 sc->sc_io_rman.rm_type = RMAN_ARRAY; 450 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 451 if (rman_init(&sc->sc_io_rman) != 0 || 452 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 453 panic("psycho_probe: failed to set up i/o rman"); 454 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 455 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 456 if (rman_init(&sc->sc_mem_rman) != 0 || 457 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 458 panic("psycho_probe: failed to set up memory rman"); 459 /* 460 * Find the addresses of the various bus spaces. 461 * There should not be multiple ones of one kind. 462 * The physical start addresses of the ranges are the configuration, 463 * memory and IO handles. 464 */ 465 for (n = 0; n < sc->sc_nrange; n++) { 466 i = UPA_RANGE_CS(&sc->sc_range[n]); 467 if (sc->sc_bh[i] != 0) 468 panic("psycho_attach: duplicate range for space %d", i); 469 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 470 } 471 /* 472 * Check that all needed handles are present. The PCI_CS_MEM64 one is 473 * not currently used. 474 */ 475 for (n = 0; n < 3; n++) { 476 if (sc->sc_bh[n] == 0) 477 panic("psycho_attach: range %d missing", n); 478 } 479 480 /* allocate our tags */ 481 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 482 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 483 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 484 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 485 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_dmat) != 0) 486 panic("psycho_attach: bus_dma_tag_create failed"); 487 /* Customize the tag */ 488 sc->sc_dmat->dt_cookie = sc; 489 sc->sc_dmat->dt_dmamap_create = psycho_dmamap_create; 490 sc->sc_dmat->dt_dmamap_destroy = psycho_dmamap_destroy; 491 sc->sc_dmat->dt_dmamap_load = psycho_dmamap_load; 492 sc->sc_dmat->dt_dmamap_unload = psycho_dmamap_unload; 493 sc->sc_dmat->dt_dmamap_sync = psycho_dmamap_sync; 494 sc->sc_dmat->dt_dmamem_alloc = psycho_dmamem_alloc; 495 sc->sc_dmat->dt_dmamem_free = psycho_dmamem_free; 496 /* XXX: register as root dma tag (kluge). */ 497 sparc64_root_dma_tag = sc->sc_dmat; 498 499 /* Register the softc, this is needed for paired psychos. */ 500 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 501 502 /* 503 * And finally, if we're a sabre or the first of a pair of psycho's to 504 * arrive here, start up the IOMMU and get a config space tag. 505 */ 506 if (osc == NULL) { 507 /* 508 * Establish handlers for interesting interrupts.... 509 * 510 * XXX We need to remember these and remove this to support 511 * hotplug on the UPA/FHC bus. 512 * 513 * XXX Not all controllers have these, but installing them 514 * is better than trying to sort through this mess. 515 */ 516 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 517 psycho_ue); 518 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 519 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 520 psycho_bus_a); 521 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, 522 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 523 /* Psycho-specific initialization. */ 524 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 525 /* 526 * Sabres do not have the following two interrupts. 527 */ 528 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 529 INTR_FAST, psycho_bus_b); 530#ifdef PSYCHO_MAP_WAKEUP 531 /* 532 * psycho_wakeup() doesn't do anything useful right 533 * now. 534 */ 535 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 536 psycho_wakeup); 537#endif /* PSYCHO_MAP_WAKEUP */ 538 539 /* Initialize the counter-timer. */ 540 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 541 PSR_TC0); 542 } 543 544 /* 545 * Setup IOMMU and PCI configuration if we're the first 546 * of a pair of psycho's to arrive here. 547 * 548 * We should calculate a TSB size based on amount of RAM 549 * and number of bus controllers and number and type of 550 * child devices. 551 * 552 * For the moment, 32KB should be more than enough. 553 */ 554 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 555 M_NOWAIT); 556 if (sc->sc_is == NULL) 557 panic("psycho_attach: malloc iommu_state failed"); 558 sc->sc_is->is_sb[0] = 0; 559 sc->sc_is->is_sb[1] = 0; 560 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 561 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 562 psycho_iommu_init(sc, 2); 563 } else { 564 /* Just copy IOMMU state, config tag and address */ 565 sc->sc_is = osc->sc_is; 566 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 567 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 568 iommu_reset(sc->sc_is); 569 } 570 571 /* 572 * Enable all interrupts, clear all interrupt states, and install an 573 * interrupt handler for OBIO interrupts, which can be ISA ones 574 * (to frob the interrupt clear registers). 575 * This aids the debugging of interrupt routing problems, and is needed 576 * for isa drivers that use isa_irq_pending (otherwise the registers 577 * will never be cleared). 578 */ 579#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 580 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 581 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 582 mr = PSYCHO_READ8(sc, map); 583#ifdef PSYCHO_DEBUG 584 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 585#endif 586 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 587 for (i = 0; i < 4; i++) 588 PCICTL_WRITE8(sc, clr + i * 8, 0); 589 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 590 } 591 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 592 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 593 mr = PSYCHO_READ8(sc, map); 594#ifdef PSYCHO_DEBUG 595 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 596 (u_long)mr, (u_long)clr); 597#endif 598 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 599 PSYCHO_WRITE8(sc, clr, 0); 600#ifdef PSYCHO_STRAY 601 /* 602 * This can cause interrupt storms, and is therefore disabled 603 * by default. 604 * XXX: use intr_setup() to not confuse higher level code 605 */ 606 if (INTVEC(mr) != 0x7e6 && INTVEC(mr) != 0x7e7 && 607 INTVEC(mr) != 0) { 608 sclr = malloc(sizeof(*sclr), M_DEVBUF, M_WAITOK); 609 sclr->psc_sc = sc; 610 sclr->psc_clr = clr; 611 intr_setup(PIL_LOW, intr_fast, INTVEC(mr), 612 psycho_intr_stray, sclr); 613 } 614#endif 615 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 616 } 617#endif 618 619 /* 620 * Get the bus range from the firmware; it is used solely for obtaining 621 * the inital bus number, and cannot be trusted on all machines. 622 */ 623 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 624 if (n == -1) 625 panic("could not get psycho bus-range"); 626 if (n != sizeof(psycho_br)) 627 panic("broken psycho bus-range (%d)", n); 628 629 sc->sc_busno = ofw_pci_alloc_busno(sc->sc_node); 630 obd.obd_bus = psycho_br[0]; 631 obd.obd_secbus = obd.obd_subbus = sc->sc_busno; 632 obd.obd_slot = PCS_DEVICE; 633 obd.obd_func = PCS_FUNC; 634 obd.obd_init = psycho_binit; 635 obd.obd_super = NULL; 636 /* Initial setup. */ 637 psycho_binit(dev, &obd); 638 /* Update the bus number to what was just programmed. */ 639 obd.obd_bus = obd.obd_secbus; 640 /* 641 * Initialize the interrupt registers of all devices hanging from 642 * the host bridge directly or indirectly via PCI-PCI bridges. 643 * The MI code (and the PCI spec) assume that this is done during 644 * system initialization, however the firmware does not do this 645 * at least on some models, and we probably shouldn't trust that 646 * the firmware uses the same model as this driver if it does. 647 * Additionally, set up the bus numbers and ranges. 648 */ 649 ofw_pci_init(dev, sc->sc_node, sc->sc_ign, &obd); 650 651 device_add_child(dev, "pci", device_get_unit(dev)); 652 return (bus_generic_attach(dev)); 653} 654 655static void 656psycho_set_intr(struct psycho_softc *sc, int index, 657 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 658{ 659 int rid, vec; 660 u_int64_t mr; 661 662 mr = PSYCHO_READ8(sc, map); 663 vec = INTVEC(mr); 664 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 665 vec, vec, 1, RF_ACTIVE); 666 if (sc->sc_irq_res[index] == NULL) 667 panic("psycho_set_intr: failed to get interrupt"); 668 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 669 handler, sc, &sc->sc_ihand[index]); 670 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 671} 672 673static int 674psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 675 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 676{ 677 bus_addr_t intrmap, intrclr; 678 u_int64_t im; 679 u_long diag; 680 int found; 681 682 found = 0; 683 /* Hunt thru obio first */ 684 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 685 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 686 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 687 diag >>= 2) { 688 im = PSYCHO_READ8(sc, intrmap); 689 if (INTINO(im) == ino) { 690 diag &= 2; 691 found = 1; 692 break; 693 } 694 } 695 696 if (!found) { 697 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 698 /* Now do PCI interrupts */ 699 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 700 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 701 diag >>= 8) { 702 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 703 (intrmap == PSR_PCIA2_INT_MAP || 704 intrmap == PSR_PCIA3_INT_MAP)) 705 continue; 706 im = PSYCHO_READ8(sc, intrmap); 707 if (((im ^ ino) & 0x3c) == 0) { 708 intrclr += 8 * (ino & 3); 709 diag = (diag >> ((ino & 3) * 2)) & 2; 710 found = 1; 711 break; 712 } 713 } 714 } 715 if (intrmapptr != NULL) 716 *intrmapptr = intrmap; 717 if (intrclrptr != NULL) 718 *intrclrptr = intrclr; 719 if (intrdiagptr != NULL) 720 *intrdiagptr = diag; 721 return (found); 722} 723 724/* grovel the OBP for various psycho properties */ 725static void 726psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 727{ 728 729 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 730 if (*np == -1) 731 panic("could not get psycho ranges"); 732} 733 734/* 735 * Interrupt handlers. 736 */ 737static void 738psycho_ue(void *arg) 739{ 740 struct psycho_softc *sc = (struct psycho_softc *)arg; 741 u_int64_t afar, afsr; 742 743 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 744 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 745 /* 746 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 747 * the AFAR to be set to the physical address of the TTE entry that 748 * was invalid/write protected. Call into the iommu code to have 749 * them decoded to virtual IO addresses. 750 */ 751 if ((afsr & UEAFSR_P_DTE) != 0) 752 iommu_decode_fault(sc->sc_is, afar); 753 /* It's uncorrectable. Dump the regs and panic. */ 754 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 755 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 756} 757 758static void 759psycho_ce(void *arg) 760{ 761 struct psycho_softc *sc = (struct psycho_softc *)arg; 762 u_int64_t afar, afsr; 763 764 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 765 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 766 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 767 /* It's correctable. Dump the regs and continue. */ 768 printf("%s: correctable DMA error AFAR %#lx AFSR %#lx\n", 769 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 770} 771 772static void 773psycho_bus_a(void *arg) 774{ 775 struct psycho_softc *sc = (struct psycho_softc *)arg; 776 u_int64_t afar, afsr; 777 778 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 779 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 780 /* It's uncorrectable. Dump the regs and panic. */ 781 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx", 782 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 783} 784 785static void 786psycho_bus_b(void *arg) 787{ 788 struct psycho_softc *sc = (struct psycho_softc *)arg; 789 u_int64_t afar, afsr; 790 791 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 792 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 793 /* It's uncorrectable. Dump the regs and panic. */ 794 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx", 795 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 796} 797 798static void 799psycho_powerfail(void *arg) 800{ 801 802 /* We lost power. Try to shut down NOW. */ 803#ifdef DEBUGGER_ON_POWERFAIL 804 struct psycho_softc *sc = (struct psycho_softc *)arg; 805 806 Debugger("powerfail"); 807 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 808#else 809 printf("Power Failure Detected: Shutting down NOW.\n"); 810 shutdown_nice(0); 811#endif 812} 813 814#ifdef PSYCHO_MAP_WAKEUP 815static void 816psycho_wakeup(void *arg) 817{ 818 struct psycho_softc *sc = (struct psycho_softc *)arg; 819 820 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 821 /* Gee, we don't really have a framework to deal with this properly. */ 822 printf("%s: power management wakeup\n", device_get_name(sc->sc_dev)); 823} 824#endif /* PSYCHO_MAP_WAKEUP */ 825 826/* initialise the IOMMU... */ 827void 828psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 829{ 830 char *name; 831 struct iommu_state *is = sc->sc_is; 832 833 /* punch in our copies */ 834 is->is_bustag = sc->sc_bustag; 835 is->is_bushandle = sc->sc_bushandle; 836 is->is_iommu = PSR_IOMMU; 837 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 838 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 839 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 840 is->is_dva = PSR_IOMMU_SVADIAG; 841 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 842 843 /* give us a nice name.. */ 844 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 845 if (name == 0) 846 panic("couldn't malloc iommu name"); 847 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 848 849 iommu_init(name, is, tsbsize, sc->sc_dvmabase, 0); 850} 851 852static void 853psycho_binit(device_t busdev, struct ofw_pci_bdesc *obd) 854{ 855 856#ifdef PSYCHO_DEBUG 857 printf("psycho at %u/%u/%u: setting bus #s to %u/%u/%u\n", 858 obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus, 859 obd->obd_secbus, obd->obd_subbus); 860#endif /* PSYCHO_DEBUG */ 861 /* 862 * NOTE: this must be kept in this order, since the last write will 863 * change the config space address of the psycho. 864 */ 865 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 866 PCSR_SUBBUS, obd->obd_subbus, 1); 867 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 868 PCSR_SECBUS, obd->obd_secbus, 1); 869} 870 871static int 872psycho_maxslots(device_t dev) 873{ 874 875 /* 876 * XXX: is this correct? At any rate, a number that is too high 877 * shouldn't do any harm, if only because of the way things are 878 * handled in psycho_read_config. 879 */ 880 return (31); 881} 882 883/* 884 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 885 * creates the resource lists. This needs to be moved around once other bus 886 * drivers are added. Moving it to the MI code should maybe be reconsidered 887 * if one of these devices appear in non-sparc64 boxen. It's likely that not 888 * all BIOSes/firmwares can deal with them. 889 */ 890struct psycho_dquirk { 891 u_int32_t dq_devid; 892 int dq_quirk; 893}; 894 895/* Quirk types. May be or'ed together. */ 896#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 897 898static struct psycho_dquirk dquirks[] = { 899 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 900 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 901 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 902 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 903}; 904 905#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 906 907static u_int32_t 908psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 909 int width) 910{ 911 struct psycho_softc *sc; 912 bus_space_handle_t bh; 913 u_long offset = 0; 914 u_int32_t r, devid; 915 int i; 916 917 /* 918 * The psycho bridge does not tolerate accesses to unconfigured PCI 919 * devices' or function's config space, so look up the device in the 920 * firmware device tree first, and if it is not present, return a value 921 * that will make the detection code think that there is no device here. 922 * This is ugly... 923 */ 924 if (reg == 0 && ofw_pci_find_node(bus, slot, func) == 0) 925 return (0xffffffff); 926 sc = (struct psycho_softc *)device_get_softc(dev); 927 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 928 bh = sc->sc_bh[PCI_CS_CONFIG]; 929 switch (width) { 930 case 1: 931 r = bus_space_read_1(sc->sc_cfgt, bh, offset); 932 break; 933 case 2: 934 r = bus_space_read_2(sc->sc_cfgt, bh, offset); 935 break; 936 case 4: 937 r = bus_space_read_4(sc->sc_cfgt, bh, offset); 938 break; 939 default: 940 panic("psycho_read_config: bad width"); 941 } 942 if (reg == PCIR_INTPIN && r == 0) { 943 /* Check for DQT_BAD_INTPIN quirk. */ 944 devid = psycho_read_config(dev, bus, slot, func, 945 PCIR_DEVVENDOR, 4); 946 for (i = 0; i < NDQUIRKS; i++) { 947 if (dquirks[i].dq_devid == devid) { 948 /* 949 * Need to set the intpin to a value != 0 so 950 * that the MI code will think that this device 951 * has an interrupt. 952 * Just use 1 (intpin a) for now. This is, of 953 * course, bogus, but since interrupts are 954 * routed in advance, this does not really 955 * matter. 956 */ 957 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 958 r = 1; 959 break; 960 } 961 } 962 } 963 return (r); 964} 965 966static void 967psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 968 u_int reg, u_int32_t val, int width) 969{ 970 struct psycho_softc *sc; 971 bus_space_handle_t bh; 972 u_long offset = 0; 973 974 sc = (struct psycho_softc *)device_get_softc(dev); 975 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 976 bh = sc->sc_bh[PCI_CS_CONFIG]; 977 switch (width) { 978 case 1: 979 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 980 break; 981 case 2: 982 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 983 break; 984 case 4: 985 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 986 break; 987 default: 988 panic("psycho_write_config: bad width"); 989 } 990} 991 992static int 993psycho_route_interrupt(device_t bus, device_t dev, int pin) 994{ 995 996 /* 997 * XXX: ugly loathsome hack: 998 * We can't use ofw_pci_route_intr() here; the device passed may be 999 * the one of a bridge, so the original device can't be recovered. 1000 * 1001 * We need to use the firmware to route interrupts, however it has 1002 * no interface which could be used to interpret intpins; instead, 1003 * all assignments are done by device. 1004 * 1005 * The MI pci code will try to reroute interrupts of 0, although they 1006 * are correct; all other interrupts are preinitialized, so if we 1007 * get here, the intline is either 0 (so return 0), or we hit a 1008 * device which was not preinitialized (e.g. hotplugged stuff), in 1009 * which case we are lost. 1010 */ 1011 return (0); 1012} 1013 1014static int 1015psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1016{ 1017 struct psycho_softc *sc; 1018 1019 sc = (struct psycho_softc *)device_get_softc(dev); 1020 switch (which) { 1021 case PCIB_IVAR_BUS: 1022 *result = sc->sc_busno; 1023 return (0); 1024 } 1025 return (ENOENT); 1026} 1027 1028/* Write to the correct clr register, and call the actual handler. */ 1029static void 1030psycho_intr_stub(void *arg) 1031{ 1032 struct psycho_clr *pc; 1033 1034 pc = (struct psycho_clr *)arg; 1035 pc->pci_handler(pc->pci_arg); 1036 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1037} 1038 1039#ifdef PSYCHO_STRAY 1040/* 1041 * Write to the correct clr register and return. arg is the address of the clear 1042 * register to be used. 1043 * XXX: print a message? 1044 */ 1045static void 1046psycho_intr_stray(void *arg) 1047{ 1048 struct psycho_strayclr *sclr = arg; 1049 1050 PSYCHO_WRITE8(sclr->psc_sc, sclr->psc_clr, 0); 1051} 1052#endif 1053 1054static int 1055psycho_setup_intr(device_t dev, device_t child, 1056 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1057 void **cookiep) 1058{ 1059 struct psycho_softc *sc; 1060 struct psycho_clr *pc; 1061 bus_addr_t intrmapptr, intrclrptr; 1062 long vec = rman_get_start(ires); 1063 u_int64_t mr; 1064 int ino, error; 1065 1066 sc = (struct psycho_softc *)device_get_softc(dev); 1067 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1068 if (pc == NULL) 1069 return (NULL); 1070 1071 /* 1072 * Hunt through all the interrupt mapping regs to look for our 1073 * interrupt vector. 1074 * 1075 * XXX We only compare INOs rather than IGNs since the firmware may 1076 * not provide the IGN and the IGN is constant for all device on that 1077 * PCI controller. This could cause problems for the FFB/external 1078 * interrupt which has a full vector that can be set arbitrarily. 1079 */ 1080 ino = INTINO(vec); 1081 1082 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1083 printf("Cannot find interrupt vector %lx\n", vec); 1084 free(pc, M_DEVBUF); 1085 return (NULL); 1086 } 1087 1088#ifdef PSYCHO_DEBUG 1089 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1090 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1091#endif 1092 pc->pci_sc = sc; 1093 pc->pci_arg = arg; 1094 pc->pci_handler = intr; 1095 pc->pci_clr = intrclrptr; 1096 /* Disable the interrupt while we fiddle with it */ 1097 mr = PSYCHO_READ8(sc, intrmapptr); 1098 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1099 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1100 psycho_intr_stub, pc, cookiep); 1101 if (error != 0) { 1102 free(pc, M_DEVBUF); 1103 return (error); 1104 } 1105 pc->pci_cookie = *cookiep; 1106 *cookiep = pc; 1107 1108 /* 1109 * Clear the interrupt, it might have been triggered before it was 1110 * set up. 1111 */ 1112 PSYCHO_WRITE8(sc, intrclrptr, 0); 1113 /* 1114 * Enable the interrupt and program the target module now we have the 1115 * handler installed. 1116 */ 1117 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 1118 return (error); 1119} 1120 1121static int 1122psycho_teardown_intr(device_t dev, device_t child, 1123 struct resource *vec, void *cookie) 1124{ 1125 struct psycho_clr *pc; 1126 int error; 1127 1128 pc = (struct psycho_clr *)cookie; 1129 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1130 pc->pci_cookie); 1131 /* 1132 * Don't disable the interrupt for now, so that stray interupts get 1133 * detected... 1134 */ 1135 if (error != 0) 1136 free(pc, M_DEVBUF); 1137 return (error); 1138} 1139 1140static struct resource * 1141psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1142 u_long start, u_long end, u_long count, u_int flags) 1143{ 1144 struct psycho_softc *sc; 1145 struct resource *rv; 1146 struct rman *rm; 1147 bus_space_tag_t bt; 1148 bus_space_handle_t bh; 1149 int needactivate = flags & RF_ACTIVE; 1150 1151 flags &= ~RF_ACTIVE; 1152 1153 sc = (struct psycho_softc *)device_get_softc(bus); 1154 if (type == SYS_RES_IRQ) { 1155 /* 1156 * XXX: Don't accept blank ranges for now, only single 1157 * interrupts. The other case should not happen with the MI pci 1158 * code... 1159 * XXX: This may return a resource that is out of the range 1160 * that was specified. Is this correct...? 1161 */ 1162 if (start != end) 1163 panic("psycho_alloc_resource: XXX: interrupt range"); 1164 start = end |= sc->sc_ign; 1165 return (bus_alloc_resource(bus, type, rid, start, end, 1166 count, flags)); 1167 } 1168 switch (type) { 1169 case SYS_RES_MEMORY: 1170 rm = &sc->sc_mem_rman; 1171 bt = sc->sc_memt; 1172 bh = sc->sc_bh[PCI_CS_MEM32]; 1173 break; 1174 case SYS_RES_IOPORT: 1175 rm = &sc->sc_io_rman; 1176 bt = sc->sc_iot; 1177 bh = sc->sc_bh[PCI_CS_IO]; 1178 break; 1179 default: 1180 return (NULL); 1181 } 1182 1183 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1184 if (rv == NULL) 1185 return (NULL); 1186 1187 bh += rman_get_start(rv); 1188 rman_set_bustag(rv, bt); 1189 rman_set_bushandle(rv, bh); 1190 1191 if (needactivate) { 1192 if (bus_activate_resource(child, type, *rid, rv)) { 1193 rman_release_resource(rv); 1194 return (NULL); 1195 } 1196 } 1197 1198 return (rv); 1199} 1200 1201static int 1202psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1203 struct resource *r) 1204{ 1205 void *p; 1206 int error; 1207 1208 if (type == SYS_RES_IRQ) 1209 return (bus_activate_resource(bus, type, rid, r)); 1210 if (type == SYS_RES_MEMORY) { 1211 /* 1212 * Need to memory-map the device space, as some drivers depend 1213 * on the virtual address being set and useable. 1214 */ 1215 error = sparc64_bus_mem_map(rman_get_bustag(r), 1216 rman_get_bushandle(r), rman_get_size(r), 0, NULL, &p); 1217 if (error != 0) 1218 return (error); 1219 rman_set_virtual(r, p); 1220 } 1221 return (rman_activate_resource(r)); 1222} 1223 1224static int 1225psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1226 struct resource *r) 1227{ 1228 1229 if (type == SYS_RES_IRQ) 1230 return (bus_deactivate_resource(bus, type, rid, r)); 1231 if (type == SYS_RES_MEMORY) { 1232 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1233 rman_set_virtual(r, NULL); 1234 } 1235 return (rman_deactivate_resource(r)); 1236} 1237 1238static int 1239psycho_release_resource(device_t bus, device_t child, int type, int rid, 1240 struct resource *r) 1241{ 1242 int error; 1243 1244 if (type == SYS_RES_IRQ) 1245 return (bus_release_resource(bus, type, rid, r)); 1246 if (rman_get_flags(r) & RF_ACTIVE) { 1247 error = bus_deactivate_resource(child, type, rid, r); 1248 if (error) 1249 return error; 1250 } 1251 return (rman_release_resource(r)); 1252} 1253 1254static int 1255psycho_intr_pending(device_t dev, int intr) 1256{ 1257 struct psycho_softc *sc; 1258 u_long diag; 1259 1260 sc = (struct psycho_softc *)device_get_softc(dev); 1261 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1262 printf("psycho_intr_pending: mapping not found for %d\n", intr); 1263 return (0); 1264 } 1265 return (diag != 0); 1266} 1267 1268static bus_space_handle_t 1269psycho_get_bus_handle(device_t dev, enum sbbt_id id, 1270 bus_space_handle_t childhdl, bus_space_tag_t *tag) 1271{ 1272 struct psycho_softc *sc; 1273 1274 sc = (struct psycho_softc *)device_get_softc(dev); 1275 switch(id) { 1276 case SBBT_IO: 1277 *tag = sc->sc_iot; 1278 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1279 case SBBT_MEM: 1280 *tag = sc->sc_memt; 1281 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1282 default: 1283 panic("psycho_get_bus_handle: illegal space\n"); 1284 } 1285} 1286 1287/* 1288 * below here is bus space and bus dma support 1289 */ 1290static bus_space_tag_t 1291psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1292{ 1293 bus_space_tag_t bt; 1294 1295 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1296 M_NOWAIT | M_ZERO); 1297 if (bt == NULL) 1298 panic("psycho_alloc_bus_tag: out of memory"); 1299 1300 bzero(bt, sizeof *bt); 1301 bt->bst_cookie = sc; 1302 bt->bst_parent = sc->sc_bustag; 1303 bt->bst_type = type; 1304 return (bt); 1305} 1306 1307/* 1308 * hooks into the iommu dvma calls. 1309 */ 1310static int 1311psycho_dmamem_alloc(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 1312 int flags, bus_dmamap_t *mapp) 1313{ 1314 struct psycho_softc *sc; 1315 1316 sc = (struct psycho_softc *)pdmat->dt_cookie; 1317 return (iommu_dvmamem_alloc(pdmat, ddmat, sc->sc_is, vaddr, flags, 1318 mapp)); 1319} 1320 1321static void 1322psycho_dmamem_free(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 1323 bus_dmamap_t map) 1324{ 1325 struct psycho_softc *sc; 1326 1327 sc = (struct psycho_softc *)pdmat->dt_cookie; 1328 iommu_dvmamem_free(pdmat, ddmat, sc->sc_is, vaddr, map); 1329} 1330 1331static int 1332psycho_dmamap_create(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, int flags, 1333 bus_dmamap_t *mapp) 1334{ 1335 struct psycho_softc *sc; 1336 1337 sc = (struct psycho_softc *)pdmat->dt_cookie; 1338 return (iommu_dvmamap_create(pdmat, ddmat, sc->sc_is, flags, mapp)); 1339 1340} 1341 1342static int 1343psycho_dmamap_destroy(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 1344 bus_dmamap_t map) 1345{ 1346 struct psycho_softc *sc; 1347 1348 sc = (struct psycho_softc *)pdmat->dt_cookie; 1349 return (iommu_dvmamap_destroy(pdmat, ddmat, sc->sc_is, map)); 1350} 1351 1352static int 1353psycho_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1354 void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback, 1355 void *callback_arg, int flags) 1356{ 1357 struct psycho_softc *sc; 1358 1359 sc = (struct psycho_softc *)pdmat->dt_cookie; 1360 return (iommu_dvmamap_load(pdmat, ddmat, sc->sc_is, map, buf, buflen, 1361 callback, callback_arg, flags)); 1362} 1363 1364static void 1365psycho_dmamap_unload(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 1366{ 1367 struct psycho_softc *sc; 1368 1369 sc = (struct psycho_softc *)pdmat->dt_cookie; 1370 iommu_dvmamap_unload(pdmat, ddmat, sc->sc_is, map); 1371} 1372 1373static void 1374psycho_dmamap_sync(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1375 bus_dmasync_op_t op) 1376{ 1377 struct psycho_softc *sc; 1378 1379 sc = (struct psycho_softc *)pdmat->dt_cookie; 1380 iommu_dvmamap_sync(pdmat, ddmat, sc->sc_is, map, op); 1381} 1382