psycho.c revision 105274
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * All rights reserved. 4 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 105274 2002-10-16 17:03:36Z tmm $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_psycho.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46 47#include <ofw/openfirm.h> 48#include <ofw/ofw_pci.h> 49 50#include <machine/bus.h> 51#include <machine/iommureg.h> 52#include <machine/bus_common.h> 53#include <machine/frame.h> 54#include <machine/intr_machdep.h> 55#include <machine/nexusvar.h> 56#include <machine/ofw_upa.h> 57#include <machine/resource.h> 58 59#include <sys/rman.h> 60 61#include <machine/iommuvar.h> 62 63#include <pci/pcivar.h> 64#include <pci/pcireg.h> 65 66#include <sparc64/pci/ofw_pci.h> 67#include <sparc64/pci/psychoreg.h> 68#include <sparc64/pci/psychovar.h> 69 70#include "pcib_if.h" 71#include "sparcbus_if.h" 72 73static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 74static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 75 int, driver_intr_t); 76static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 77 bus_addr_t *, u_long *); 78static void psycho_intr_stub(void *); 79#ifdef PSYCHO_STRAY 80static void psycho_intr_stray(void *); 81#endif 82static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 83 84 85/* Interrupt handlers */ 86static void psycho_ue(void *); 87static void psycho_ce(void *); 88static void psycho_bus_a(void *); 89static void psycho_bus_b(void *); 90static void psycho_powerfail(void *); 91#ifdef PSYCHO_MAP_WAKEUP 92static void psycho_wakeup(void *); 93#endif 94 95/* IOMMU support */ 96static void psycho_iommu_init(struct psycho_softc *, int); 97static ofw_pci_binit_t psycho_binit; 98 99/* 100 * bus space and bus dma support for UltraSPARC `psycho'. note that most 101 * of the bus dma support is provided by the iommu dvma controller. 102 */ 103static int psycho_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, int, 104 bus_dmamap_t *); 105static int psycho_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 106static int psycho_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 107 void *, bus_size_t, bus_dmamap_callback_t *, void *, int); 108static void psycho_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 109static void psycho_dmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 110 bus_dmasync_op_t); 111static int psycho_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, void **, int, 112 bus_dmamap_t *); 113static void psycho_dmamem_free(bus_dma_tag_t, bus_dma_tag_t, void *, 114 bus_dmamap_t); 115 116/* 117 * autoconfiguration 118 */ 119static int psycho_probe(device_t); 120static int psycho_attach(device_t); 121static int psycho_read_ivar(device_t, device_t, int, u_long *); 122static int psycho_setup_intr(device_t, device_t, struct resource *, int, 123 driver_intr_t *, void *, void **); 124static int psycho_teardown_intr(device_t, device_t, struct resource *, void *); 125static struct resource *psycho_alloc_resource(device_t, device_t, int, int *, 126 u_long, u_long, u_long, u_int); 127static int psycho_activate_resource(device_t, device_t, int, int, 128 struct resource *); 129static int psycho_deactivate_resource(device_t, device_t, int, int, 130 struct resource *); 131static int psycho_release_resource(device_t, device_t, int, int, 132 struct resource *); 133static int psycho_maxslots(device_t); 134static u_int32_t psycho_read_config(device_t, u_int, u_int, u_int, u_int, int); 135static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, 136 int); 137static int psycho_route_interrupt(device_t, device_t, int); 138static int psycho_intr_pending(device_t, int); 139static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id, 140 bus_space_handle_t childhdl, bus_space_tag_t *tag); 141 142static device_method_t psycho_methods[] = { 143 /* Device interface */ 144 DEVMETHOD(device_probe, psycho_probe), 145 DEVMETHOD(device_attach, psycho_attach), 146 147 /* Bus interface */ 148 DEVMETHOD(bus_print_child, bus_generic_print_child), 149 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 150 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 151 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 152 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 153 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 154 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 155 DEVMETHOD(bus_release_resource, psycho_release_resource), 156 157 /* pcib interface */ 158 DEVMETHOD(pcib_maxslots, psycho_maxslots), 159 DEVMETHOD(pcib_read_config, psycho_read_config), 160 DEVMETHOD(pcib_write_config, psycho_write_config), 161 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 162 163 /* sparcbus interface */ 164 DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending), 165 DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle), 166 167 { 0, 0 } 168}; 169 170static driver_t psycho_driver = { 171 "pcib", 172 psycho_methods, 173 sizeof(struct psycho_softc), 174}; 175 176static devclass_t psycho_devclass; 177 178DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 179 180SLIST_HEAD(, psycho_softc) psycho_softcs = 181 SLIST_HEAD_INITIALIZER(psycho_softcs); 182 183struct psycho_clr { 184 struct psycho_softc *pci_sc; 185 bus_addr_t pci_clr; /* clear register */ 186 driver_intr_t *pci_handler; /* handler to call */ 187 void *pci_arg; /* argument for the handler */ 188 void *pci_cookie; /* interrupt cookie of parent bus */ 189}; 190 191struct psycho_strayclr { 192 struct psycho_softc *psc_sc; 193 bus_addr_t psc_clr; /* clear register */ 194}; 195 196#define PSYCHO_READ8(sc, off) \ 197 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 198#define PSYCHO_WRITE8(sc, off, v) \ 199 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 200#define PCICTL_READ8(sc, off) \ 201 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 202#define PCICTL_WRITE8(sc, off, v) \ 203 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 204 205/* 206 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 207 * single PCI bus and does not have a streaming buffer. It often has an APB 208 * (advanced PCI bridge) connected to it, which was designed specifically for 209 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 210 * appears as two "simba"'s underneath the sabre. 211 * 212 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 213 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 214 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 215 * will usually find a "psycho+" since I don't think the original "psycho" 216 * ever shipped, and if it did it would be in the U30. 217 * 218 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 219 * both part of the same IC, they only have a single register space. As such, 220 * they need to be configured together, even though the autoconfiguration will 221 * attach them separately. 222 * 223 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 224 * as pci1 and pci2, although they have been implemented with other PCI bus 225 * numbers on some machines. 226 * 227 * On UltraII machines, there can be any number of "psycho+" ICs, each 228 * providing two PCI buses. 229 * 230 * 231 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 232 * the values of the following interrupts in this order: 233 * 234 * PCI Bus Error (30) 235 * DMA UE (2e) 236 * DMA CE (2f) 237 * Power Fail (25) 238 * 239 * We really should attach handlers for each. 240 */ 241#define OFW_PCI_TYPE "pci" 242#define OFW_SABRE_MODEL "SUNW,sabre" 243#define OFW_SABRE_COMPAT "pci108e,a001" 244#define OFW_SIMBA_MODEL "SUNW,simba" 245#define OFW_PSYCHO_MODEL "SUNW,psycho" 246 247static int 248psycho_probe(device_t dev) 249{ 250 phandle_t node; 251 char *dtype, *model; 252 static char compat[32]; 253 254 node = nexus_get_node(dev); 255 if (OF_getprop(node, "compatible", compat, sizeof(compat)) == -1) 256 compat[0] = '\0'; 257 258 dtype = nexus_get_device_type(dev); 259 model = nexus_get_model(dev); 260 /* match on a type of "pci" and a sabre or a psycho */ 261 if (nexus_get_reg(dev) != NULL && dtype != NULL && 262 strcmp(dtype, OFW_PCI_TYPE) == 0 && 263 ((model != NULL && (strcmp(model, OFW_SABRE_MODEL) == 0 || 264 strcmp(model, OFW_PSYCHO_MODEL) == 0)) || 265 strcmp(compat, OFW_SABRE_COMPAT) == 0)) { 266 device_set_desc(dev, "U2P UPA-PCI bridge"); 267 return (0); 268 } 269 270 return (ENXIO); 271} 272 273/* 274 * SUNW,psycho initialisation .. 275 * - find the per-psycho registers 276 * - figure out the IGN. 277 * - find our partner psycho 278 * - configure ourselves 279 * - bus range, bus, 280 * - interrupt map, 281 * - setup the chipsets. 282 * - if we're the first of the pair, initialise the IOMMU, otherwise 283 * just copy it's tags and addresses. 284 */ 285static int 286psycho_attach(device_t dev) 287{ 288 struct psycho_softc *sc; 289 struct psycho_softc *osc = NULL; 290 struct psycho_softc *asc; 291 struct upa_regs *reg; 292 struct ofw_pci_bdesc obd; 293 char compat[32]; 294 char *model; 295 phandle_t node; 296 u_int64_t csr; 297 u_long pcictl_offs, mlen; 298 int psycho_br[2]; 299 int n, i, nreg, rid; 300#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 301 bus_addr_t map, clr; 302 u_int64_t mr; 303#endif 304#ifdef PSYCHO_STRAY 305 struct psycho_strayclr *sclr; 306#endif 307 308 node = nexus_get_node(dev); 309 sc = device_get_softc(dev); 310 if (OF_getprop(node, "compatible", compat, sizeof(compat)) == -1) 311 compat[0] = '\0'; 312 313 sc->sc_node = node; 314 sc->sc_dev = dev; 315 sc->sc_dmatag = nexus_get_dmatag(dev); 316 317 /* 318 * call the model-specific initialisation routine. 319 */ 320 model = nexus_get_model(dev); 321 if ((model != NULL && 322 strcmp(model, OFW_SABRE_MODEL) == 0) || 323 strcmp(compat, OFW_SABRE_COMPAT) == 0) { 324 sc->sc_mode = PSYCHO_MODE_SABRE; 325 if (model == NULL) 326 model = "sabre"; 327 } else if (model != NULL && 328 strcmp(model, OFW_PSYCHO_MODEL) == 0) 329 sc->sc_mode = PSYCHO_MODE_PSYCHO; 330 else 331 panic("psycho_attach: unknown model!"); 332 333 /* 334 * The psycho gets three register banks: 335 * (0) per-PBM configuration and status registers 336 * (1) per-PBM PCI configuration space, containing only the 337 * PBM 256-byte PCI header 338 * (2) the shared psycho configuration registers (struct psychoreg) 339 * 340 * XXX use the prom address for the psycho registers? we do so far. 341 */ 342 reg = nexus_get_reg(dev); 343 nreg = nexus_get_nreg(dev); 344 /* Register layouts are different. stuupid. */ 345 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 346 if (nreg <= 2) 347 panic("psycho_attach: %d not enough registers", nreg); 348 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[2]); 349 mlen = UPA_REG_SIZE(®[2]); 350 pcictl_offs = UPA_REG_PHYS(®[0]); 351 } else { 352 if (nreg <= 0) 353 panic("psycho_attach: %d not enough registers", nreg); 354 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[0]); 355 mlen = UPA_REG_SIZE(reg); 356 pcictl_offs = sc->sc_basepaddr + PSR_PCICTL0; 357 } 358 359 /* 360 * Match other psycho's that are already configured against 361 * the base physical address. This will be the same for a 362 * pair of devices that share register space. 363 */ 364 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 365 if (asc->sc_basepaddr == sc->sc_basepaddr) { 366 /* Found partner */ 367 osc = asc; 368 break; 369 } 370 } 371 372 if (osc == NULL) { 373 rid = 0; 374 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 375 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 376 RF_ACTIVE); 377 if (sc->sc_mem_res == NULL || 378 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 379 panic("psycho_attach: can't allocate device memory"); 380 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 381 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 382 } else { 383 /* 384 * There's another psycho using the same register space. Copy the 385 * relevant stuff. 386 */ 387 sc->sc_mem_res = NULL; 388 sc->sc_bustag = osc->sc_bustag; 389 sc->sc_bushandle = osc->sc_bushandle; 390 } 391 if (pcictl_offs < sc->sc_basepaddr) 392 panic("psycho_attach: bogus pci control register location"); 393 sc->sc_pcictl = pcictl_offs - sc->sc_basepaddr; 394 csr = PSYCHO_READ8(sc, PSR_CS); 395 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 396 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 397 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 398 399 device_printf(dev, "%s: impl %d, version %d: ign %x ", 400 model, (int)PSYCHO_GCSR_IMPL(csr), (int)PSYCHO_GCSR_VERS(csr), 401 sc->sc_ign); 402 403 /* 404 * Setup the PCI control register 405 */ 406 csr = PCICTL_READ8(sc, PCR_CS); 407 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 408 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 409 PCICTL_RTRYWAIT); 410 PCICTL_WRITE8(sc, PCR_CS, csr); 411 412 /* Grab the psycho ranges */ 413 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 414 415 /* Initialize memory and i/o rmans */ 416 sc->sc_io_rman.rm_type = RMAN_ARRAY; 417 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 418 if (rman_init(&sc->sc_io_rman) != 0 || 419 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 420 panic("psycho_probe: failed to set up i/o rman"); 421 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 422 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 423 if (rman_init(&sc->sc_mem_rman) != 0 || 424 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 425 panic("psycho_probe: failed to set up memory rman"); 426 /* 427 * Find the addresses of the various bus spaces. 428 * There should not be multiple ones of one kind. 429 * The physical start addresses of the ranges are the configuration, 430 * memory and IO handles. 431 */ 432 for (n = 0; n < sc->sc_nrange; n++) { 433 i = UPA_RANGE_CS(&sc->sc_range[n]); 434 if (sc->sc_bh[i] != 0) 435 panic("psycho_attach: duplicate range for space %d", i); 436 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 437 } 438 /* 439 * Check that all needed handles are present. The PCI_CS_MEM64 one is 440 * not currently used. 441 */ 442 for (n = 0; n < 3; n++) { 443 if (sc->sc_bh[n] == 0) 444 panic("psycho_attach: range %d missing", n); 445 } 446 447 /* allocate our tags */ 448 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 449 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 450 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 451 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 452 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_dmat) != 0) 453 panic("psycho_attach: bus_dma_tag_create failed"); 454 /* Customize the tag */ 455 sc->sc_dmat->cookie = sc; 456 sc->sc_dmat->dmamap_create = psycho_dmamap_create; 457 sc->sc_dmat->dmamap_destroy = psycho_dmamap_destroy; 458 sc->sc_dmat->dmamap_load = psycho_dmamap_load; 459 sc->sc_dmat->dmamap_unload = psycho_dmamap_unload; 460 sc->sc_dmat->dmamap_sync = psycho_dmamap_sync; 461 sc->sc_dmat->dmamem_alloc = psycho_dmamem_alloc; 462 sc->sc_dmat->dmamem_free = psycho_dmamem_free; 463 /* XXX: register as root dma tag (kluge). */ 464 sparc64_root_dma_tag = sc->sc_dmat; 465 466 /* Register the softc, this is needed for paired psychos. */ 467 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 468 469 /* 470 * And finally, if we're a sabre or the first of a pair of psycho's to 471 * arrive here, start up the IOMMU and get a config space tag. 472 */ 473 if (osc == NULL) { 474 /* 475 * Establish handlers for interesting interrupts.... 476 * 477 * XXX We need to remember these and remove this to support 478 * hotplug on the UPA/FHC bus. 479 * 480 * XXX Not all controllers have these, but installing them 481 * is better than trying to sort through this mess. 482 */ 483 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 484 psycho_ue); 485 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 486 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 487 psycho_bus_a); 488 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, INTR_FAST, 489 psycho_powerfail); 490 /* Psycho-specific initialization. */ 491 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 492 /* 493 * Sabres do not have the following two interrupts. 494 */ 495 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 496 INTR_FAST, psycho_bus_b); 497#ifdef PSYCHO_MAP_WAKEUP 498 /* 499 * psycho_wakeup() doesn't do anything useful right 500 * now. 501 */ 502 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 503 psycho_wakeup); 504#endif /* PSYCHO_MAP_WAKEUP */ 505 506 /* Initialize the counter-timer. */ 507 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 508 PSR_TC0); 509 } 510 511 /* 512 * Setup IOMMU and PCI configuration if we're the first 513 * of a pair of psycho's to arrive here. 514 * 515 * We should calculate a TSB size based on amount of RAM 516 * and number of bus controllers and number an type of 517 * child devices. 518 * 519 * For the moment, 32KB should be more than enough. 520 */ 521 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 522 M_NOWAIT); 523 if (sc->sc_is == NULL) 524 panic("psycho_attach: malloc iommu_state failed"); 525 sc->sc_is->is_sb[0] = 0; 526 sc->sc_is->is_sb[1] = 0; 527 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 528 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 529 psycho_iommu_init(sc, 2); 530 } else { 531 /* Just copy IOMMU state, config tag and address */ 532 sc->sc_is = osc->sc_is; 533 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 534 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 535 iommu_reset(sc->sc_is); 536 } 537 538 /* 539 * Enable all interrupts, clear all interrupt states, and install an 540 * interrupt handler for OBIO interrupts, which can be ISA ones 541 * (to frob the interrupt clear registers). 542 * This aids the debugging of interrupt routing problems, and is needed 543 * for isa drivers that use isa_irq_pending (otherwise the registers 544 * will never be cleared). 545 */ 546#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 547 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 548 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 549 mr = PSYCHO_READ8(sc, map); 550#ifdef PSYCHO_DEBUG 551 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 552#endif 553 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 554 for (i = 0; i < 4; i++) 555 PCICTL_WRITE8(sc, clr + i * 8, 0); 556 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 557 } 558 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 559 map <= PSR_FFB1_INT_MAP; map += 8, clr += 8, n++) { 560 mr = PSYCHO_READ8(sc, map); 561#ifdef PSYCHO_DEBUG 562 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 563 (u_long)mr, (u_long)clr); 564#endif 565 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 566 PSYCHO_WRITE8(sc, clr, 0); 567#ifdef PSYCHO_STRAY 568 /* 569 * This can cause interrupt storms, and is therefore disabled 570 * by default. 571 * XXX: use intr_setup() to not confuse higher level code 572 */ 573 if (INTVEC(mr) != 0x7e6 && INTVEC(mr) != 0x7e7 && 574 INTVEC(mr) != 0) { 575 sclr = malloc(sizeof(*sclr), M_DEVBUF, M_WAITOK); 576 sclr->psc_sc = sc; 577 sclr->psc_clr = clr; 578 intr_setup(PIL_LOW, intr_fast, INTVEC(mr), 579 psycho_intr_stray, sclr); 580 } 581#endif 582 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 583 } 584#endif 585 586 /* 587 * Get the bus range from the firmware; it is used solely for obtaining 588 * the inital bus number, and cannot be trusted on all machines. 589 */ 590 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 591 if (n == -1) 592 panic("could not get psycho bus-range"); 593 if (n != sizeof(psycho_br)) 594 panic("broken psycho bus-range (%d)", n); 595 596 sc->sc_busno = ofw_pci_alloc_busno(sc->sc_node); 597 obd.obd_bus = psycho_br[0]; 598 obd.obd_secbus = obd.obd_subbus = sc->sc_busno; 599 obd.obd_slot = PCS_DEVICE; 600 obd.obd_func = PCS_FUNC; 601 obd.obd_init = psycho_binit; 602 obd.obd_super = NULL; 603 /* Initial setup. */ 604 psycho_binit(dev, &obd); 605 /* Update the bus number to what was just programmed. */ 606 obd.obd_bus = obd.obd_secbus; 607 /* 608 * Initialize the interrupt registers of all devices hanging from 609 * the host bridge directly or indirectly via PCI-PCI bridges. 610 * The MI code (and the PCI spec) assume that this is done during 611 * system initialization, however the firmware does not do this 612 * at least on some models, and we probably shouldn't trust that 613 * the firmware uses the same model as this driver if it does. 614 * Additionally, set up the bus numbers and ranges. 615 */ 616 ofw_pci_init(dev, sc->sc_node, &obd); 617 618 device_add_child(dev, "pci", device_get_unit(dev)); 619 return (bus_generic_attach(dev)); 620} 621 622static void 623psycho_set_intr(struct psycho_softc *sc, int index, 624 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 625{ 626 int rid, vec; 627 u_int64_t mr; 628 629 mr = PSYCHO_READ8(sc, map); 630 vec = INTVEC(mr); 631 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 632 vec, vec, 1, RF_ACTIVE); 633 if (sc->sc_irq_res[index] == NULL) 634 panic("psycho_set_intr: failed to get interrupt"); 635 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 636 handler, sc, &sc->sc_ihand[index]); 637 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 638} 639 640static int 641psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 642 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 643{ 644 bus_addr_t intrmap, intrclr; 645 u_int64_t im; 646 u_long diag; 647 int found; 648 649 found = 0; 650 /* Hunt thru obio first */ 651 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 652 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 653 intrmap <= PSR_FFB1_INT_MAP; intrmap += 8, intrclr += 8, 654 diag >>= 2) { 655 im = PSYCHO_READ8(sc, intrmap); 656 if (INTINO(im) == ino) { 657 diag &= 2; 658 found = 1; 659 break; 660 } 661 } 662 663 if (!found) { 664 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 665 /* Now do PCI interrupts */ 666 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 667 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 668 diag >>= 8) { 669 im = PSYCHO_READ8(sc, intrmap); 670 if (((im ^ ino) & 0x3c) == 0) { 671 intrclr += 8 * (ino & 3); 672 diag = (diag >> ((ino & 3) * 2)) & 2; 673 found = 1; 674 break; 675 } 676 } 677 } 678 if (intrmapptr != NULL) 679 *intrmapptr = intrmap; 680 if (intrclrptr != NULL) 681 *intrclrptr = intrclr; 682 if (intrdiagptr != NULL) 683 *intrdiagptr = diag; 684 return (found); 685} 686 687/* grovel the OBP for various psycho properties */ 688static void 689psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 690{ 691 692 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 693 if (*np == -1) 694 panic("could not get psycho ranges"); 695} 696 697/* 698 * Interrupt handlers. 699 */ 700static void 701psycho_ue(void *arg) 702{ 703 struct psycho_softc *sc = (struct psycho_softc *)arg; 704 u_int64_t afar, afsr; 705 706 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 707 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 708 /* 709 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 710 * the AFAR to be set to the physical address of the TTE entry that 711 * was invalid/write protected. Call into the iommu code to have 712 * them decoded to virtual IO addresses. 713 */ 714 if ((afsr & UEAFSR_P_DTE) != 0) 715 iommu_decode_fault(sc->sc_is, afar); 716 /* It's uncorrectable. Dump the regs and panic. */ 717 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx\n", 718 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 719} 720 721static void 722psycho_ce(void *arg) 723{ 724 struct psycho_softc *sc = (struct psycho_softc *)arg; 725 u_int64_t afar, afsr; 726 727 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 728 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 729 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 730 /* It's correctable. Dump the regs and continue. */ 731 printf("%s: correctable DMA error AFAR %#lx AFSR %#lx\n", 732 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 733} 734 735static void 736psycho_bus_a(void *arg) 737{ 738 struct psycho_softc *sc = (struct psycho_softc *)arg; 739 u_int64_t afar, afsr; 740 741 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 742 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 743 /* It's uncorrectable. Dump the regs and panic. */ 744 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx\n", 745 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 746} 747 748static void 749psycho_bus_b(void *arg) 750{ 751 struct psycho_softc *sc = (struct psycho_softc *)arg; 752 u_int64_t afar, afsr; 753 754 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 755 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 756 /* It's uncorrectable. Dump the regs and panic. */ 757 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx\n", 758 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 759} 760 761static void 762psycho_powerfail(void *arg) 763{ 764 765 /* We lost power. Try to shut down NOW. */ 766#ifdef DEBUGGER_ON_POWERFAIL 767 struct psycho_softc *sc = (struct psycho_softc *)arg; 768 769 Debugger("powerfail"); 770 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 771#else 772 printf("Power Failure Detected: Shutting down NOW.\n"); 773 shutdown_nice(0); 774#endif 775} 776 777#ifdef PSYCHO_MAP_WAKEUP 778static void 779psycho_wakeup(void *arg) 780{ 781 struct psycho_softc *sc = (struct psycho_softc *)arg; 782 783 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 784 /* Gee, we don't really have a framework to deal with this properly. */ 785 printf("%s: power management wakeup\n", device_get_name(sc->sc_dev)); 786} 787#endif /* PSYCHO_MAP_WAKEUP */ 788 789/* initialise the IOMMU... */ 790void 791psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 792{ 793 char *name; 794 struct iommu_state *is = sc->sc_is; 795 u_int32_t iobase = -1; 796 int *vdma = NULL; 797 int nitem; 798 799 /* punch in our copies */ 800 is->is_bustag = sc->sc_bustag; 801 is->is_bushandle = sc->sc_bushandle; 802 is->is_iommu = PSR_IOMMU; 803 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 804 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 805 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 806 is->is_dva = PSR_IOMMU_SVADIAG; 807 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 808 809 /* 810 * Separate the men from the boys. Get the `virtual-dma' 811 * property for sabre and use that to make sure the damn 812 * iommu works. 813 * 814 * We could query the `#virtual-dma-size-cells' and 815 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 816 */ 817 nitem = OF_getprop_alloc(sc->sc_node, "virtual-dma", sizeof(vdma), 818 (void **)&vdma); 819 if (nitem > 0) { 820 iobase = vdma[0]; 821 tsbsize = ffs(vdma[1]); 822 if (tsbsize < 25 || tsbsize > 31 || 823 (vdma[1] & ~(1 << (tsbsize - 1))) != 0) { 824 printf("bogus tsb size %x, using 7\n", vdma[1]); 825 tsbsize = 31; 826 } 827 tsbsize -= 24; 828 free(vdma, M_OFWPROP); 829 } 830 831 /* give us a nice name.. */ 832 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 833 if (name == 0) 834 panic("couldn't malloc iommu name"); 835 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 836 837 iommu_init(name, is, tsbsize, iobase, 0); 838} 839 840static void 841psycho_binit(device_t busdev, struct ofw_pci_bdesc *obd) 842{ 843 844#ifdef PSYCHO_DEBUG 845 printf("psycho at %u/%u/%u: setting bus #s to %u/%u/%u\n", 846 obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus, 847 obd->obd_secbus, obd->obd_subbus); 848#endif /* PSYCHO_DEBUG */ 849 /* 850 * NOTE: this must be kept in this order, since the last write will 851 * change the config space address of the psycho. 852 */ 853 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 854 PCSR_SUBBUS, obd->obd_subbus, 1); 855 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 856 PCSR_SECBUS, obd->obd_secbus, 1); 857} 858 859static int 860psycho_maxslots(device_t dev) 861{ 862 863 /* 864 * XXX: is this correct? At any rate, a number that is too high 865 * shouldn't do any harm, if only because of the way things are 866 * handled in psycho_read_config. 867 */ 868 return (31); 869} 870 871/* 872 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 873 * creates the resource lists. This needs to be moved around once other bus 874 * drivers are added. Moving it to the MI code should maybe be reconsidered 875 * if one of these devices appear in non-sparc64 boxen. It's likely that not 876 * all BIOSes/firmwares can deal with them. 877 */ 878struct psycho_dquirk { 879 u_int32_t dq_devid; 880 int dq_quirk; 881}; 882 883/* Quirk types. May be or'ed together. */ 884#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 885 886static struct psycho_dquirk dquirks[] = { 887 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 888 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 889 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 890 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 891}; 892 893#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 894 895static u_int32_t 896psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 897 int width) 898{ 899 struct psycho_softc *sc; 900 bus_space_handle_t bh; 901 u_long offset = 0; 902 u_int32_t r, devid; 903 int i; 904 905 /* 906 * The psycho bridge does not tolerate accesses to unconfigured PCI 907 * devices' or function's config space, so look up the device in the 908 * firmware device tree first, and if it is not present, return a value 909 * that will make the detection code think that there is no device here. 910 * This is ugly... 911 */ 912 if (reg == 0 && ofw_pci_find_node(bus, slot, func) == 0) 913 return (0xffffffff); 914 sc = (struct psycho_softc *)device_get_softc(dev); 915 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 916 bh = sc->sc_bh[PCI_CS_CONFIG]; 917 switch (width) { 918 case 1: 919 r = bus_space_read_1(sc->sc_cfgt, bh, offset); 920 break; 921 case 2: 922 r = bus_space_read_2(sc->sc_cfgt, bh, offset); 923 break; 924 case 4: 925 r = bus_space_read_4(sc->sc_cfgt, bh, offset); 926 break; 927 default: 928 panic("psycho_read_config: bad width"); 929 } 930 if (reg == PCIR_INTPIN && r == 0) { 931 /* Check for DQT_BAD_INTPIN quirk. */ 932 devid = psycho_read_config(dev, bus, slot, func, 933 PCIR_DEVVENDOR, 4); 934 for (i = 0; i < NDQUIRKS; i++) { 935 if (dquirks[i].dq_devid == devid) { 936 /* 937 * Need to set the intpin to a value != 0 so 938 * that the MI code will think that this device 939 * has an interrupt. 940 * Just use 1 (intpin a) for now. This is, of 941 * course, bogus, but since interrupts are 942 * routed in advance, this does not really 943 * matter. 944 */ 945 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 946 r = 1; 947 break; 948 } 949 } 950 } 951 return (r); 952} 953 954static void 955psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 956 u_int reg, u_int32_t val, int width) 957{ 958 struct psycho_softc *sc; 959 bus_space_handle_t bh; 960 u_long offset = 0; 961 962 sc = (struct psycho_softc *)device_get_softc(dev); 963 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 964 bh = sc->sc_bh[PCI_CS_CONFIG]; 965 switch (width) { 966 case 1: 967 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 968 break; 969 case 2: 970 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 971 break; 972 case 4: 973 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 974 break; 975 default: 976 panic("psycho_write_config: bad width"); 977 } 978} 979 980static int 981psycho_route_interrupt(device_t bus, device_t dev, int pin) 982{ 983 984 /* 985 * XXX: ugly loathsome hack: 986 * We can't use ofw_pci_route_intr() here; the device passed may be 987 * the one of a bridge, so the original device can't be recovered. 988 * 989 * We need to use the firmware to route interrupts, however it has 990 * no interface which could be used to interpret intpins; instead, 991 * all assignments are done by device. 992 * 993 * The MI pci code will try to reroute interrupts of 0, although they 994 * are correct; all other interrupts are preinitialized, so if we 995 * get here, the intline is either 0 (so return 0), or we hit a 996 * device which was not preinitialized (e.g. hotplugged stuff), in 997 * which case we are lost. 998 */ 999 return (0); 1000} 1001 1002static int 1003psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1004{ 1005 struct psycho_softc *sc; 1006 1007 sc = (struct psycho_softc *)device_get_softc(dev); 1008 switch (which) { 1009 case PCIB_IVAR_BUS: 1010 *result = sc->sc_busno; 1011 return (0); 1012 } 1013 return (ENOENT); 1014} 1015 1016/* Write to the correct clr register, and call the actual handler. */ 1017static void 1018psycho_intr_stub(void *arg) 1019{ 1020 struct psycho_clr *pc; 1021 1022 pc = (struct psycho_clr *)arg; 1023 pc->pci_handler(pc->pci_arg); 1024 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1025} 1026 1027#ifdef PSYCHO_STRAY 1028/* 1029 * Write to the correct clr register and return. arg is the address of the clear 1030 * register to be used. 1031 * XXX: print a message? 1032 */ 1033static void 1034psycho_intr_stray(void *arg) 1035{ 1036 struct psycho_strayclr *sclr = arg; 1037 1038 PSYCHO_WRITE8(sclr->psc_sc, sclr->psc_clr, 0); 1039} 1040#endif 1041 1042static int 1043psycho_setup_intr(device_t dev, device_t child, 1044 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1045 void **cookiep) 1046{ 1047 struct psycho_softc *sc; 1048 struct psycho_clr *pc; 1049 bus_addr_t intrmapptr, intrclrptr; 1050 long vec = rman_get_start(ires); 1051 u_int64_t mr; 1052 int ino, error; 1053 1054 sc = (struct psycho_softc *)device_get_softc(dev); 1055 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1056 if (pc == NULL) 1057 return (NULL); 1058 1059 /* 1060 * Hunt through all the interrupt mapping regs to look for our 1061 * interrupt vector. 1062 * 1063 * XXX We only compare INOs rather than IGNs since the firmware may 1064 * not provide the IGN and the IGN is constant for all device on that 1065 * PCI controller. This could cause problems for the FFB/external 1066 * interrupt which has a full vector that can be set arbitrarily. 1067 */ 1068 ino = INTINO(vec); 1069 1070 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1071 printf("Cannot find interrupt vector %lx\n", vec); 1072 free(pc, M_DEVBUF); 1073 return (NULL); 1074 } 1075 1076#ifdef PSYCHO_DEBUG 1077 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1078 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1079#endif 1080 pc->pci_sc = sc; 1081 pc->pci_arg = arg; 1082 pc->pci_handler = intr; 1083 pc->pci_clr = intrclrptr; 1084 /* Disable the interrupt while we fiddle with it */ 1085 mr = PSYCHO_READ8(sc, intrmapptr); 1086 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1087 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1088 psycho_intr_stub, pc, cookiep); 1089 if (error != 0) { 1090 free(pc, M_DEVBUF); 1091 return (error); 1092 } 1093 pc->pci_cookie = *cookiep; 1094 *cookiep = pc; 1095 1096 /* 1097 * Clear the interrupt, it might have been triggered before it was 1098 * set up. 1099 */ 1100 PSYCHO_WRITE8(sc, intrclrptr, 0); 1101 /* 1102 * Enable the interrupt now we have the handler installed. 1103 * Read the current value as we can't change it besides the 1104 * valid bit so so make sure only this bit is changed. 1105 */ 1106 PSYCHO_WRITE8(sc, intrmapptr, mr | INTMAP_V); 1107 return (error); 1108} 1109 1110static int 1111psycho_teardown_intr(device_t dev, device_t child, 1112 struct resource *vec, void *cookie) 1113{ 1114 struct psycho_clr *pc; 1115 int error; 1116 1117 pc = (struct psycho_clr *)cookie; 1118 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1119 pc->pci_cookie); 1120 /* 1121 * Don't disable the interrupt for now, so that stray interupts get 1122 * detected... 1123 */ 1124 if (error != 0) 1125 free(pc, M_DEVBUF); 1126 return (error); 1127} 1128 1129static struct resource * 1130psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1131 u_long start, u_long end, u_long count, u_int flags) 1132{ 1133 struct psycho_softc *sc; 1134 struct resource *rv; 1135 struct rman *rm; 1136 bus_space_tag_t bt; 1137 bus_space_handle_t bh; 1138 int needactivate = flags & RF_ACTIVE; 1139 1140 flags &= ~RF_ACTIVE; 1141 1142 sc = (struct psycho_softc *)device_get_softc(bus); 1143 if (type == SYS_RES_IRQ) { 1144 /* 1145 * XXX: Don't accept blank ranges for now, only single 1146 * interrupts. The other case should not happen with the MI pci 1147 * code... 1148 * XXX: This may return a resource that is out of the range 1149 * that was specified. Is this correct...? 1150 */ 1151 if (start != end) 1152 panic("psycho_alloc_resource: XXX: interrupt range"); 1153 start = end |= sc->sc_ign; 1154 return (bus_alloc_resource(bus, type, rid, start, end, 1155 count, flags)); 1156 } 1157 switch (type) { 1158 case SYS_RES_MEMORY: 1159 rm = &sc->sc_mem_rman; 1160 bt = sc->sc_memt; 1161 bh = sc->sc_bh[PCI_CS_MEM32]; 1162 break; 1163 case SYS_RES_IOPORT: 1164 rm = &sc->sc_io_rman; 1165 bt = sc->sc_iot; 1166 /* XXX: probably should use ranges property here. */ 1167 bh = sc->sc_bh[PCI_CS_IO]; 1168 break; 1169 default: 1170 return (NULL); 1171 } 1172 1173 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1174 if (rv == NULL) 1175 return (NULL); 1176 1177 bh += rman_get_start(rv); 1178 rman_set_bustag(rv, bt); 1179 rman_set_bushandle(rv, bh); 1180 1181 if (needactivate) { 1182 if (bus_activate_resource(child, type, *rid, rv)) { 1183 rman_release_resource(rv); 1184 return (NULL); 1185 } 1186 } 1187 1188 return (rv); 1189} 1190 1191static int 1192psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1193 struct resource *r) 1194{ 1195 void *p; 1196 int error; 1197 1198 if (type == SYS_RES_IRQ) 1199 return (bus_activate_resource(bus, type, rid, r)); 1200 if (type == SYS_RES_MEMORY) { 1201 /* 1202 * Need to memory-map the device space, as some drivers depend 1203 * on the virtual address being set and useable. 1204 */ 1205 error = sparc64_bus_mem_map(rman_get_bustag(r), 1206 rman_get_bushandle(r), rman_get_size(r), 0, NULL, &p); 1207 if (error != 0) 1208 return (error); 1209 rman_set_virtual(r, p); 1210 } 1211 return (rman_activate_resource(r)); 1212} 1213 1214static int 1215psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1216 struct resource *r) 1217{ 1218 1219 if (type == SYS_RES_IRQ) 1220 return (bus_deactivate_resource(bus, type, rid, r)); 1221 if (type == SYS_RES_MEMORY) { 1222 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1223 rman_set_virtual(r, NULL); 1224 } 1225 return (rman_deactivate_resource(r)); 1226} 1227 1228static int 1229psycho_release_resource(device_t bus, device_t child, int type, int rid, 1230 struct resource *r) 1231{ 1232 int error; 1233 1234 if (type == SYS_RES_IRQ) 1235 return (bus_release_resource(bus, type, rid, r)); 1236 if (rman_get_flags(r) & RF_ACTIVE) { 1237 error = bus_deactivate_resource(child, type, rid, r); 1238 if (error) 1239 return error; 1240 } 1241 return (rman_release_resource(r)); 1242} 1243 1244static int 1245psycho_intr_pending(device_t dev, int intr) 1246{ 1247 struct psycho_softc *sc; 1248 u_long diag; 1249 1250 sc = (struct psycho_softc *)device_get_softc(dev); 1251 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1252 printf("psycho_intr_pending: mapping not found for %d\n", intr); 1253 return (0); 1254 } 1255 return (diag != 0); 1256} 1257 1258static bus_space_handle_t 1259psycho_get_bus_handle(device_t dev, enum sbbt_id id, 1260 bus_space_handle_t childhdl, bus_space_tag_t *tag) 1261{ 1262 struct psycho_softc *sc; 1263 1264 sc = (struct psycho_softc *)device_get_softc(dev); 1265 switch(id) { 1266 case SBBT_IO: 1267 *tag = sc->sc_iot; 1268 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1269 case SBBT_MEM: 1270 *tag = sc->sc_memt; 1271 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1272 default: 1273 panic("psycho_get_bus_handle: illegal space\n"); 1274 } 1275} 1276 1277/* 1278 * below here is bus space and bus dma support 1279 */ 1280static bus_space_tag_t 1281psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1282{ 1283 bus_space_tag_t bt; 1284 1285 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1286 M_NOWAIT | M_ZERO); 1287 if (bt == NULL) 1288 panic("psycho_alloc_bus_tag: out of memory"); 1289 1290 bzero(bt, sizeof *bt); 1291 bt->cookie = sc; 1292 bt->parent = sc->sc_bustag; 1293 bt->type = type; 1294 return (bt); 1295} 1296 1297/* 1298 * hooks into the iommu dvma calls. 1299 */ 1300static int 1301psycho_dmamem_alloc(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 1302 int flags, bus_dmamap_t *mapp) 1303{ 1304 struct psycho_softc *sc; 1305 1306 sc = (struct psycho_softc *)pdmat->cookie; 1307 return (iommu_dvmamem_alloc(pdmat, ddmat, sc->sc_is, vaddr, flags, 1308 mapp)); 1309} 1310 1311static void 1312psycho_dmamem_free(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 1313 bus_dmamap_t map) 1314{ 1315 struct psycho_softc *sc; 1316 1317 sc = (struct psycho_softc *)pdmat->cookie; 1318 iommu_dvmamem_free(pdmat, ddmat, sc->sc_is, vaddr, map); 1319} 1320 1321static int 1322psycho_dmamap_create(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, int flags, 1323 bus_dmamap_t *mapp) 1324{ 1325 struct psycho_softc *sc; 1326 1327 sc = (struct psycho_softc *)pdmat->cookie; 1328 return (iommu_dvmamap_create(pdmat, ddmat, sc->sc_is, flags, mapp)); 1329 1330} 1331 1332static int 1333psycho_dmamap_destroy(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 1334 bus_dmamap_t map) 1335{ 1336 struct psycho_softc *sc; 1337 1338 sc = (struct psycho_softc *)pdmat->cookie; 1339 return (iommu_dvmamap_destroy(pdmat, ddmat, sc->sc_is, map)); 1340} 1341 1342static int 1343psycho_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1344 void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback, 1345 void *callback_arg, int flags) 1346{ 1347 struct psycho_softc *sc; 1348 1349 sc = (struct psycho_softc *)pdmat->cookie; 1350 return (iommu_dvmamap_load(pdmat, ddmat, sc->sc_is, map, buf, buflen, 1351 callback, callback_arg, flags)); 1352} 1353 1354static void 1355psycho_dmamap_unload(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 1356{ 1357 struct psycho_softc *sc; 1358 1359 sc = (struct psycho_softc *)pdmat->cookie; 1360 iommu_dvmamap_unload(pdmat, ddmat, sc->sc_is, map); 1361} 1362 1363static void 1364psycho_dmamap_sync(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1365 bus_dmasync_op_t op) 1366{ 1367 struct psycho_softc *sc; 1368 1369 sc = (struct psycho_softc *)pdmat->cookie; 1370 iommu_dvmamap_sync(pdmat, ddmat, sc->sc_is, map, op); 1371} 1372