1295041Sbr/*- 2295972Sbr * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com> 3295041Sbr * All rights reserved. 4295041Sbr * 5295041Sbr * Portions of this software were developed by SRI International and the 6295041Sbr * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7295041Sbr * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8295041Sbr * 9295041Sbr * Portions of this software were developed by the University of Cambridge 10295041Sbr * Computer Laboratory as part of the CTSRD Project, with support from the 11295041Sbr * UK Higher Education Innovation Fund (HEIF). 12295041Sbr * 13295041Sbr * Redistribution and use in source and binary forms, with or without 14295041Sbr * modification, are permitted provided that the following conditions 15295041Sbr * are met: 16295041Sbr * 1. Redistributions of source code must retain the above copyright 17295041Sbr * notice, this list of conditions and the following disclaimer. 18295041Sbr * 2. Redistributions in binary form must reproduce the above copyright 19295041Sbr * notice, this list of conditions and the following disclaimer in the 20295041Sbr * documentation and/or other materials provided with the distribution. 21295041Sbr * 22295041Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23295041Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24295041Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25295041Sbr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26295041Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27295041Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28295041Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29295041Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30295041Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31295041Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32295041Sbr * SUCH DAMAGE. 33295041Sbr */ 34295041Sbr 35295041Sbr#include <machine/asm.h> 36295041Sbr#include <machine/param.h> 37295041Sbr__FBSDID("$FreeBSD: releng/11.0/sys/riscv/riscv/cpufunc_asm.S 295972 2016-02-24 16:50:34Z br $"); 38295041Sbr 39295041Sbr .text 40295041Sbr .align 2 41295041Sbr 42295041Sbr.Lpage_mask: 43295041Sbr .word PAGE_MASK 44295041Sbr 45295041SbrENTRY(riscv_nullop) 46295041Sbr ret 47295041SbrEND(riscv_nullop) 48295041Sbr 49295041Sbr/* 50295041Sbr * Generic functions to read/modify/write the internal coprocessor registers 51295041Sbr */ 52295041Sbr 53295041SbrENTRY(riscv_tlb_flushID) 54295041Sbr sfence.vm 55295041Sbr ret 56295041SbrEND(riscv_tlb_flushID) 57295041Sbr 58295041SbrENTRY(riscv_tlb_flushID_SE) 59295041Sbr sfence.vm 60295041Sbr ret 61295041SbrEND(riscv_tlb_flushID_SE) 62295041Sbr 63295041Sbr/* 64295041Sbr * void riscv_dcache_wb_range(vm_offset_t, vm_size_t) 65295041Sbr */ 66295041SbrENTRY(riscv_dcache_wb_range) 67295972Sbr sfence.vm 68295041Sbr ret 69295041SbrEND(riscv_dcache_wb_range) 70295041Sbr 71295041Sbr/* 72295041Sbr * void riscv_dcache_wbinv_range(vm_offset_t, vm_size_t) 73295041Sbr */ 74295041SbrENTRY(riscv_dcache_wbinv_range) 75295972Sbr sfence.vm 76295041Sbr ret 77295041SbrEND(riscv_dcache_wbinv_range) 78295041Sbr 79295041Sbr/* 80295041Sbr * void riscv_dcache_inv_range(vm_offset_t, vm_size_t) 81295041Sbr */ 82295041SbrENTRY(riscv_dcache_inv_range) 83295972Sbr sfence.vm 84295041Sbr ret 85295041SbrEND(riscv_dcache_inv_range) 86295041Sbr 87295041Sbr/* 88295041Sbr * void riscv_idcache_wbinv_range(vm_offset_t, vm_size_t) 89295041Sbr */ 90295041SbrENTRY(riscv_idcache_wbinv_range) 91295972Sbr fence.i 92295972Sbr sfence.vm 93295041Sbr ret 94295041SbrEND(riscv_idcache_wbinv_range) 95295041Sbr 96295041Sbr/* 97295041Sbr * void riscv_icache_sync_range(vm_offset_t, vm_size_t) 98295041Sbr */ 99295041SbrENTRY(riscv_icache_sync_range) 100295972Sbr fence.i 101295041Sbr ret 102295041SbrEND(riscv_icache_sync_range) 103