spr.h revision 96249
1239313Sdim/* 2239313Sdim * Copyright (c) 2001 The NetBSD Foundation, Inc. 3239313Sdim * All rights reserved. 4239313Sdim * 5239313Sdim * Redistribution and use in source and binary forms, with or without 6239313Sdim * modification, are permitted provided that the following conditions 7239313Sdim * are met: 8239313Sdim * 1. Redistributions of source code must retain the above copyright 9239313Sdim * notice, this list of conditions and the following disclaimer. 10239313Sdim * 2. Redistributions in binary form must reproduce the above copyright 11239313Sdim * notice, this list of conditions and the following disclaimer in the 12239313Sdim * documentation and/or other materials provided with the distribution. 13239313Sdim * 3. All advertising materials mentioning features or use of this software 14239313Sdim * must display the following acknowledgement: 15239313Sdim * This product includes software developed by the NetBSD 16239313Sdim * Foundation, Inc. and its contributors. 17239313Sdim * 4. Neither the name of The NetBSD Foundation nor the names of its 18239313Sdim * contributors may be used to endorse or promote products derived 19239313Sdim * from this software without specific prior written permission. 20239313Sdim * 21239313Sdim * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22239313Sdim * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23239313Sdim * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24249423Sdim * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25239313Sdim * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26239313Sdim * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27239313Sdim * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28239313Sdim * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29239313Sdim * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30239313Sdim * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31239313Sdim * POSSIBILITY OF SUCH DAMAGE. 32239313Sdim * 33239313Sdim * $FreeBSD: head/sys/powerpc/include/spr.h 96249 2002-05-09 14:04:43Z benno $ 34239313Sdim */ 35263508Sdim#ifndef _POWERPC_SPR_H_ 36263508Sdim#define _POWERPC_SPR_H_ 37263508Sdim 38263508Sdim#ifndef _LOCORE 39263508Sdim#define mtspr(reg, val) \ 40263508Sdim __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 41263508Sdim#define mfspr(reg) \ 42263508Sdim ( { u_int32_t val; \ 43263508Sdim __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ 44263508Sdim val; } ) 45263508Sdim#endif /* _LOCORE */ 46263508Sdim 47263508Sdim/* 48263508Sdim * Special Purpose Register declarations. 49263508Sdim * 50263508Sdim * The first column in the comments indicates which PowerPC 51263508Sdim * architectures the SPR is valid on - 4 for 4xx series, 52263508Sdim * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series. 53263508Sdim */ 54263508Sdim 55263508Sdim#define SPR_MQ 0x000 /* .6. 601 MQ register */ 56263508Sdim#define SPR_XER 0x001 /* 468 Fixed Point Exception Register */ 57263508Sdim#define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */ 58263508Sdim#define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */ 59263508Sdim#define SPR_LR 0x008 /* 468 Link Register */ 60263508Sdim#define SPR_CTR 0x009 /* 468 Count Register */ 61263508Sdim#define SPR_DSISR 0x012 /* .68 DSI exception source */ 62263508Sdim#define DSISR_DIRECT 0x80000000 /* Direct-store error exception */ 63263508Sdim#define DSISR_NOTFOUND 0x40000000 /* Translation not found */ 64263508Sdim#define DSISR_PROTECT 0x08000000 /* Memory access not permitted */ 65263508Sdim#define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */ 66239313Sdim#define DSISR_STORE 0x02000000 /* Store operation */ 67239313Sdim#define DSISR_DABR 0x00400000 /* DABR match */ 68239313Sdim#define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */ 69239313Sdim#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */ 70239313Sdim#define SPR_DAR 0x013 /* .68 Data Address Register */ 71239313Sdim#define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */ 72239313Sdim#define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */ 73239313Sdim#define SPR_DEC 0x016 /* .68 DECrementer register */ 74239313Sdim#define SPR_SDR1 0x019 /* .68 Page table base address register */ 75239313Sdim#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */ 76239313Sdim#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */ 77239313Sdim#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */ 78239313Sdim#define SPR_SPRG0 0x110 /* 468 SPR General 0 */ 79239313Sdim#define SPR_SPRG1 0x111 /* 468 SPR General 1 */ 80239313Sdim#define SPR_SPRG2 0x112 /* 468 SPR General 2 */ 81249423Sdim#define SPR_SPRG3 0x113 /* 468 SPR General 3 */ 82249423Sdim#define SPR_SPRG4 0x114 /* 4.. SPR General 4 */ 83239313Sdim#define SPR_SPRG5 0x115 /* 4.. SPR General 5 */ 84239313Sdim#define SPR_SPRG6 0x116 /* 4.. SPR General 6 */ 85239313Sdim#define SPR_SPRG7 0x117 /* 4.. SPR General 7 */ 86239313Sdim#define SPR_EAR 0x11a /* .68 External Access Register */ 87249423Sdim#define SPR_TBL 0x11c /* 468 Time Base Lower */ 88239313Sdim#define SPR_TBU 0x11d /* 468 Time Base Upper */ 89239313Sdim#define SPR_PVR 0x11f /* 468 Processor Version Register */ 90239313Sdim#define PVR_MPC601 0x0001 91249423Sdim#define PVR_MPC603 0x0003 92239313Sdim#define PVR_MPC604 0x0004 93239313Sdim#define PVR_MPC602 0x0005 94239313Sdim#define PVR_MPC603e 0x0006 95239313Sdim#define PVR_MPC603ev 0x0007 96249423Sdim#define PVR_MPC750 0x0008 97239313Sdim#define PVR_MPC604ev 0x0009 98239313Sdim#define PVR_MPC7400 0x000c 99239313Sdim#define PVR_MPC620 0x0014 100239313Sdim#define PVR_MPC860 0x0050 101239313Sdim#define PVR_MPC8240 0x0081 102239313Sdim#define PVR_MPC7450 0x8000 103239313Sdim#define PVR_MPC7455 0x8001 104239313Sdim#define PVR_MPC7410 0x800c 105239313Sdim#define PVR_IBM405GP 0x4011 106263508Sdim#define PVR_IBM405L 0x4161 107263508Sdim#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */ 108243830Sdim#define SPR_IBAT0L 0x211 /* .68 Instruction BAT Reg 0 Lower */ 109239313Sdim#define SPR_IBAT1U 0x212 /* .68 Instruction BAT Reg 1 Upper */ 110239313Sdim#define SPR_IBAT1L 0x213 /* .68 Instruction BAT Reg 1 Lower */ 111239313Sdim#define SPR_IBAT2U 0x214 /* .68 Instruction BAT Reg 2 Upper */ 112239313Sdim#define SPR_IBAT2L 0x215 /* .68 Instruction BAT Reg 2 Lower */ 113239313Sdim#define SPR_IBAT3U 0x216 /* .68 Instruction BAT Reg 3 Upper */ 114239313Sdim#define SPR_IBAT3L 0x217 /* .68 Instruction BAT Reg 3 Lower */ 115239313Sdim#define SPR_DBAT0U 0x218 /* .68 Data BAT Reg 0 Upper */ 116239313Sdim#define SPR_DBAT0L 0x219 /* .68 Data BAT Reg 0 Lower */ 117239313Sdim#define SPR_DBAT1U 0x21a /* .68 Data BAT Reg 1 Upper */ 118239313Sdim#define SPR_DBAT1L 0x21b /* .68 Data BAT Reg 1 Lower */ 119249423Sdim#define SPR_DBAT2U 0x21c /* .68 Data BAT Reg 2 Upper */ 120239313Sdim#define SPR_DBAT2L 0x21d /* .68 Data BAT Reg 2 Lower */ 121249423Sdim#define SPR_DBAT3U 0x21e /* .68 Data BAT Reg 3 Upper */ 122239313Sdim#define SPR_DBAT3L 0x21f /* .68 Data BAT Reg 3 Lower */ 123239313Sdim#define SPI_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */ 124263508Sdim#define SPI_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */ 125239313Sdim#define SPI_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */ 126239313Sdim#define SPI_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */ 127239313Sdim#define SPI_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */ 128263508Sdim#define SPI_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */ 129263508Sdim#define SPI_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */ 130263508Sdim#define SPI_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */ 131263508Sdim#define SPI_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */ 132263508Sdim#define SPI_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */ 133263508Sdim#define SPI_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */ 134239313Sdim#define SPI_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */ 135239313Sdim#define SPI_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */ 136263508Sdim#define SPI_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */ 137239313Sdim#define SPI_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */ 138249423Sdim#define SPI_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */ 139239313Sdim#define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */ 140249423Sdim#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */ 141249423Sdim#define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */ 142249423Sdim#define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */ 143249423Sdim#define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */ 144263508Sdim#define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */ 145239313Sdim#define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ 146263508Sdim#define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ 147263508Sdim#define SPR_PID 0x3b1 /* 4.. Process ID */ 148263508Sdim#define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */ 149263508Sdim#define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */ 150263508Sdim#define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */ 151263508Sdim#define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */ 152263508Sdim#define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */ 153263508Sdim#define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */ 154263508Sdim#define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */ 155263508Sdim#define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */ 156263508Sdim#define SPR_MMCR0_FC 0x80000000 /* Freeze counters */ 157263508Sdim#define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ 158263508Sdim#define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ 159263508Sdim#define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */ 160263508Sdim#define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */ 161263508Sdim#define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */ 162263508Sdim#define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */ 163263508Sdim#define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */ 164263508Sdim#define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */ 165263508Sdim#define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */ 166263508Sdim#define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ 167263508Sdim#define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */ 168263508Sdim#define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */ 169263508Sdim#define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ 170263508Sdim#define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ 171263508Sdim#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ 172263508Sdim#define SPR_MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */ 173263508Sdim#define SPR_MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */ 174263508Sdim#define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */ 175263508Sdim#define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */ 176263508Sdim#define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */ 177263508Sdim#define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */ 178263508Sdim#define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */ 179263508Sdim#define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */ 180263508Sdim#define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */ 181263508Sdim#define SPR_MMCR1_PMC3SEL(x) ((x) << 27) /* PMC 3 selector */ 182263508Sdim#define SPR_MMCR1_PMC4SEL(x) ((x) << 22) /* PMC 4 selector */ 183263508Sdim#define SPR_MMCR1_PMC5SEL(x) ((x) << 17) /* PMC 5 selector */ 184263508Sdim#define SPR_MMCR1_PMC6SEL(x) ((x) << 11) /* PMC 6 selector */ 185263508Sdim 186263508Sdim#define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */ 187263508Sdim#define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */ 188263508Sdim#define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */ 189263508Sdim#define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */ 190263508Sdim#define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */ 191263508Sdim#define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */ 192263508Sdim#define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */ 193263508Sdim#define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */ 194263508Sdim#define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */ 195239313Sdim#define SPR_ESR 0x3d4 /* 4.. Exception Syndrome Register */ 196239313Sdim#define ESR_MCI 0x80000000 /* Machine check - instruction */ 197249423Sdim#define ESR_PIL 0x08000000 /* Program interrupt - illegal */ 198249423Sdim#define ESR_PPR 0x04000000 /* Program interrupt - privileged */ 199249423Sdim#define ESR_PTR 0x02000000 /* Program interrupt - trap */ 200249423Sdim#define ESR_DST 0x00800000 /* Data storage interrupt - store fault */ 201239313Sdim#define ESR_DIZ 0x00800000 /* Data/instruction storage interrupt - zone fault */ 202239313Sdim#define ESR_U0F 0x00008000 /* Data storage interrupt - U0 fault */ 203239313Sdim#define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */ 204239313Sdim#define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */ 205239313Sdim#define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */ 206249423Sdim#define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */ 207249423Sdim#define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */ 208239313Sdim#define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */ 209239313Sdim#define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */ 210249423Sdim#define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */ 211249423Sdim#define SPR_TSR 0x3d8 /* 4.. Timer Status Register */ 212249423Sdim#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ 213249423Sdim#define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */ 214249423Sdim#define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */ 215239313Sdim#define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */ 216249423Sdim#define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */ 217249423Sdim#define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */ 218249423Sdim#define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */ 219249423Sdim#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ 220249423Sdim#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ 221249423Sdim#define SPR_TCR 0x3da /* 4.. Timer Control Register */ 222249423Sdim#define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */ 223249423Sdim#define TCR_WP_2_17 0x00000000 /* 2**17 clocks */ 224239313Sdim#define TCR_WP_2_21 0x40000000 /* 2**21 clocks */ 225249423Sdim#define TCR_WP_2_25 0x80000000 /* 2**25 clocks */ 226249423Sdim#define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */ 227249423Sdim#define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */ 228249423Sdim#define TCR_WRC_NONE 0x00000000 /* No watchdog reset */ 229239313Sdim#define TCR_WRC_CORE 0x10000000 /* Core reset */ 230239313Sdim#define TCR_WRC_CHIP 0x20000000 /* Chip reset */ 231239313Sdim#define TCR_WRC_SYSTEM 0x30000000 /* System reset */ 232239313Sdim#define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ 233239313Sdim#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ 234249423Sdim#define TCR_FP_MASK 0x03000000 /* FIT Period */ 235239313Sdim#define TCR_FP_2_9 0x00000000 /* 2**9 clocks */ 236239313Sdim#define TCR_FP_2_13 0x01000000 /* 2**13 clocks */ 237239313Sdim#define TCR_FP_2_17 0x02000000 /* 2**17 clocks */ 238239313Sdim#define TCR_FP_2_21 0x03000000 /* 2**21 clocks */ 239239313Sdim#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 240239313Sdim#define TCR_ARE 0x00400000 /* Auto Reload Enable */ 241239313Sdim#define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */ 242239313Sdim#define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */ 243239313Sdim#define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */ 244#define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */ 245#define DBSR_IC 0x80000000 /* Instruction completion debug event */ 246#define DBSR_BT 0x40000000 /* Branch Taken debug event */ 247#define DBSR_EDE 0x20000000 /* Exception debug event */ 248#define DBSR_TIE 0x10000000 /* Trap Instruction debug event */ 249#define DBSR_UDE 0x08000000 /* Unconditional debug event */ 250#define DBSR_IA1 0x04000000 /* IAC1 debug event */ 251#define DBSR_IA2 0x02000000 /* IAC2 debug event */ 252#define DBSR_DR1 0x01000000 /* DAC1 Read debug event */ 253#define DBSR_DW1 0x00800000 /* DAC1 Write debug event */ 254#define DBSR_DR2 0x00400000 /* DAC2 Read debug event */ 255#define DBSR_DW2 0x00200000 /* DAC2 Write debug event */ 256#define DBSR_IDE 0x00100000 /* Imprecise debug event */ 257#define DBSR_IA3 0x00080000 /* IAC3 debug event */ 258#define DBSR_IA4 0x00040000 /* IAC4 debug event */ 259#define DBSR_MRR 0x00000300 /* Most recent reset */ 260#define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ 261#define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ 262#define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */ 263#define DBCR0_EDM 0x80000000 /* External Debug Mode */ 264#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 265#define DBCR0_RST_MASK 0x30000000 /* ReSeT */ 266#define DBCR0_RST_NONE 0x00000000 /* No action */ 267#define DBCR0_RST_CORE 0x10000000 /* Core reset */ 268#define DBCR0_RST_CHIP 0x20000000 /* Chip reset */ 269#define DBCR0_RST_SYSTEM 0x30000000 /* System reset */ 270#define DBCR0_IC 0x08000000 /* Instruction Completion debug event */ 271#define DBCR0_BT 0x04000000 /* Branch Taken debug event */ 272#define DBCR0_EDE 0x02000000 /* Exception Debug Event */ 273#define DBCR0_TDE 0x01000000 /* Trap Debug Event */ 274#define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */ 275#define DBCR0_IA2 0x00400000 /* IAC 2 debug event */ 276#define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */ 277#define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */ 278#define DBCR0_IA3 0x00080000 /* IAC 3 debug event */ 279#define DBCR0_IA4 0x00040000 /* IAC 4 debug event */ 280#define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */ 281#define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */ 282#define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */ 283#define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */ 284#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 285#define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */ 286#define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */ 287#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */ 288#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */ 289#define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */ 290#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */ 291#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */ 292#define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ 293#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ 294#define L2CR_L2E 0x80000000 /* 0: L2 enable */ 295#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ 296#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ 297#define L2SIZ_2M 0x00000000 298#define L2SIZ_256K 0x10000000 299#define L2SIZ_512K 0x20000000 300#define L2SIZ_1M 0x30000000 301#define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */ 302#define L2CLK_DIS 0x00000000 /* disable L2 clock */ 303#define L2CLK_10 0x02000000 /* core clock / 1 */ 304#define L2CLK_15 0x04000000 /* / 1.5 */ 305#define L2CLK_20 0x08000000 /* / 2 */ 306#define L2CLK_25 0x0a000000 /* / 2.5 */ 307#define L2CLK_30 0x0c000000 /* / 3 */ 308#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ 309#define L2RAM_FLOWTHRU_BURST 0x00000000 310#define L2RAM_PIPELINE_BURST 0x01000000 311#define L2RAM_PIPELINE_LATE 0x01800000 312#define L2CR_L2DO 0x00400000 /* 9: L2 data-only. 313 Setting this bit disables instruction 314 caching. */ 315#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ 316#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). 317 Enables automatic operation of the 318 L2ZZ (low-power mode) signal. */ 319#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ 320#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ 321#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ 322#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ 323#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ 324#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ 325#define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */ 326 /* progress (read only). */ 327#define SPR_L3CR 0x3fa /* .6. L3 Control Register */ 328#define L3CR_L3E 0x80000000 /* 0: L3 enable */ 329#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ 330#define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */ 331#define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */ 332#define SPR_THRM1 0x3fc /* .6. Thermal Management Register */ 333#define SPR_THRM2 0x3fd /* .6. Thermal Management Register */ 334#define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */ 335#define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */ 336#define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */ 337#define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */ 338#define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */ 339#define SPR_THRM_VALID 0x00000001 /* Valid bit */ 340#define SPR_THRM3 0x3fe /* .6. Thermal Management Register */ 341#define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */ 342#define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */ 343#define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */ 344#define SPR_PIR 0x3ff /* .6. Processor Identification Register */ 345 346/* Time Base Register declarations */ 347#define TBR_TBL 0x10c /* 468 Time Base Lower */ 348#define TBR_TBU 0x10d /* 468 Time Base Upper */ 349 350/* Performance counter declarations */ 351#define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */ 352 353/* The first five countable [non-]events are common to all the PMC's */ 354#define PMCN_NONE 0 /* Count nothing */ 355#define PMCN_CYCLES 1 /* Processor cycles */ 356#define PMCN_ICOMP 2 /* Instructions completed */ 357#define PMCN_TBLTRANS 3 /* TBL bit transitions */ 358#define PCMN_IDISPATCH 4 /* Instructions dispatched */ 359 360#endif /* !_POWERPC_SPR_H_ */ 361