177957Sbenno/*- 277957Sbenno * Copyright (C) 1995, 1996 Wolfgang Solfrank. 377957Sbenno * Copyright (C) 1995, 1996 TooLs GmbH. 477957Sbenno * All rights reserved. 577957Sbenno * 677957Sbenno * Redistribution and use in source and binary forms, with or without 777957Sbenno * modification, are permitted provided that the following conditions 877957Sbenno * are met: 977957Sbenno * 1. Redistributions of source code must retain the above copyright 1077957Sbenno * notice, this list of conditions and the following disclaimer. 1177957Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1277957Sbenno * notice, this list of conditions and the following disclaimer in the 1377957Sbenno * documentation and/or other materials provided with the distribution. 1477957Sbenno * 3. All advertising materials mentioning features or use of this software 1577957Sbenno * must display the following acknowledgement: 1677957Sbenno * This product includes software developed by TooLs GmbH. 1777957Sbenno * 4. The name of TooLs GmbH may not be used to endorse or promote products 1877957Sbenno * derived from this software without specific prior written permission. 1977957Sbenno * 2077957Sbenno * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 2177957Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2277957Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2377957Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2477957Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 2577957Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 2677957Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 2777957Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 2877957Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 2977957Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3077957Sbenno * 3177957Sbenno * $NetBSD: pte.h,v 1.2 1998/08/31 14:43:40 tsubai Exp $ 3277957Sbenno * $FreeBSD: releng/11.0/sys/powerpc/include/pte.h 295642 2016-02-16 02:13:55Z jhibbits $ 3377957Sbenno */ 3477957Sbenno 3577957Sbenno#ifndef _MACHINE_PTE_H_ 3677957Sbenno#define _MACHINE_PTE_H_ 3777957Sbenno 38176770Sraj#if defined(AIM) 39176770Sraj 4077957Sbenno/* 4177957Sbenno * Page Table Entries 4277957Sbenno */ 4377957Sbenno#ifndef LOCORE 4477957Sbenno 45152310Sgrehan/* 32-bit PTE */ 4677957Sbennostruct pte { 47152310Sgrehan u_int32_t pte_hi; 48152310Sgrehan u_int32_t pte_lo; 4977957Sbenno}; 5090643Sbenno 5190643Sbennostruct pteg { 5290643Sbenno struct pte pt[8]; 5390643Sbenno}; 54152310Sgrehan 55152310Sgrehan/* 64-bit (long) PTE */ 56152310Sgrehanstruct lpte { 57152310Sgrehan u_int64_t pte_hi; 58152310Sgrehan u_int64_t pte_lo; 59152310Sgrehan}; 60152310Sgrehan 61152310Sgrehanstruct lpteg { 62152310Sgrehan struct lpte pt[8]; 63152310Sgrehan}; 64152310Sgrehan 6577957Sbenno#endif /* LOCORE */ 66152310Sgrehan 67152310Sgrehan/* 32-bit PTE definitions */ 68152310Sgrehan 6977957Sbenno/* High word: */ 7077957Sbenno#define PTE_VALID 0x80000000 7177957Sbenno#define PTE_VSID_SHFT 7 7277957Sbenno#define PTE_HID 0x00000040 7377957Sbenno#define PTE_API 0x0000003f 7477957Sbenno/* Low word: */ 7577957Sbenno#define PTE_RPGN 0xfffff000 7677957Sbenno#define PTE_REF 0x00000100 7777957Sbenno#define PTE_CHG 0x00000080 7877957Sbenno#define PTE_WIMG 0x00000078 7977957Sbenno#define PTE_W 0x00000040 8077957Sbenno#define PTE_I 0x00000020 8177957Sbenno#define PTE_M 0x00000010 8277957Sbenno#define PTE_G 0x00000008 8377957Sbenno#define PTE_PP 0x00000003 8490643Sbenno#define PTE_SO 0x00000000 /* Super. Only (U: XX, S: RW) */ 8590643Sbenno#define PTE_SW 0x00000001 /* Super. Write-Only (U: RO, S: RW) */ 8690643Sbenno#define PTE_BW 0x00000002 /* Supervisor (U: RW, S: RW) */ 8790643Sbenno#define PTE_BR 0x00000003 /* Both Read Only (U: RO, S: RO) */ 8890643Sbenno#define PTE_RW PTE_BW 8990643Sbenno#define PTE_RO PTE_BR 9077957Sbenno 9196250Sbenno#define PTE_EXEC 0x00000200 /* pseudo bit in attrs; page is exec */ 9296250Sbenno 93152310Sgrehan/* 64-bit PTE definitions */ 94152310Sgrehan 95152310Sgrehan/* High quadword: */ 96152310Sgrehan#define LPTE_VSID_SHIFT 12 97217044Snwhitehorn#define LPTE_AVPN_MASK 0xFFFFFFFFFFFFFF80ULL 98152310Sgrehan#define LPTE_API 0x0000000000000F80ULL 99255415Snwhitehorn#define LPTE_SWBITS 0x0000000000000078ULL 100255415Snwhitehorn#define LPTE_WIRED 0x0000000000000010ULL 101255415Snwhitehorn#define LPTE_LOCKED 0x0000000000000008ULL 102152310Sgrehan#define LPTE_BIG 0x0000000000000004ULL /* 4kb/16Mb page */ 103152310Sgrehan#define LPTE_HID 0x0000000000000002ULL 104152310Sgrehan#define LPTE_VALID 0x0000000000000001ULL 105152310Sgrehan 106152310Sgrehan/* Low quadword: */ 107152310Sgrehan#define EXTEND_PTE(x) UINT64_C(x) /* make constants 64-bit */ 108152310Sgrehan#define LPTE_RPGN 0xfffffffffffff000ULL 109152310Sgrehan#define LPTE_REF EXTEND_PTE( PTE_REF ) 110152310Sgrehan#define LPTE_CHG EXTEND_PTE( PTE_CHG ) 111152310Sgrehan#define LPTE_WIMG EXTEND_PTE( PTE_WIMG ) 112152310Sgrehan#define LPTE_W EXTEND_PTE( PTE_W ) 113152310Sgrehan#define LPTE_I EXTEND_PTE( PTE_I ) 114152310Sgrehan#define LPTE_M EXTEND_PTE( PTE_M ) 115152310Sgrehan#define LPTE_G EXTEND_PTE( PTE_G ) 116152310Sgrehan#define LPTE_NOEXEC 0x0000000000000004ULL 117152310Sgrehan#define LPTE_PP EXTEND_PTE( PTE_PP ) 118152310Sgrehan 119152310Sgrehan#define LPTE_SO EXTEND_PTE( PTE_SO ) /* Super. Only */ 120152310Sgrehan#define LPTE_SW EXTEND_PTE( PTE_SW ) /* Super. Write-Only */ 121152310Sgrehan#define LPTE_BW EXTEND_PTE( PTE_BW ) /* Supervisor */ 122152310Sgrehan#define LPTE_BR EXTEND_PTE( PTE_BR ) /* Both Read Only */ 123152310Sgrehan#define LPTE_RW LPTE_BW 124152310Sgrehan#define LPTE_RO LPTE_BR 125152310Sgrehan 12677957Sbenno#ifndef LOCORE 12777957Sbennotypedef struct pte pte_t; 128152310Sgrehantypedef struct lpte lpte_t; 12977957Sbenno#endif /* LOCORE */ 13077957Sbenno 13177957Sbenno/* 13277957Sbenno * Extract bits from address 13377957Sbenno */ 13477957Sbenno#define ADDR_SR_SHFT 28 135209975Snwhitehorn#define ADDR_PIDX 0x0ffff000UL 13677957Sbenno#define ADDR_PIDX_SHFT 12 13777957Sbenno#define ADDR_API_SHFT 22 138183290Snwhitehorn#define ADDR_API_SHFT64 16 139209975Snwhitehorn#define ADDR_POFF 0x00000fffUL 14077957Sbenno 14177957Sbenno/* 14277957Sbenno * Bits in DSISR: 14377957Sbenno */ 14477957Sbenno#define DSISR_DIRECT 0x80000000 14577957Sbenno#define DSISR_NOTFOUND 0x40000000 14677957Sbenno#define DSISR_PROTECT 0x08000000 14777957Sbenno#define DSISR_INVRX 0x04000000 14877957Sbenno#define DSISR_STORE 0x02000000 14977957Sbenno#define DSISR_DABR 0x00400000 15077957Sbenno#define DSISR_SEGMENT 0x00200000 15177957Sbenno#define DSISR_EAR 0x00100000 15277957Sbenno 15377957Sbenno/* 15477957Sbenno * Bits in SRR1 on ISI: 15577957Sbenno */ 15677957Sbenno#define ISSRR1_NOTFOUND 0x40000000 15777957Sbenno#define ISSRR1_DIRECT 0x10000000 15877957Sbenno#define ISSRR1_PROTECT 0x08000000 15977957Sbenno#define ISSRR1_SEGMENT 0x00200000 16077957Sbenno 161236141Sraj#else /* BOOKE */ 162176770Sraj 163176770Sraj#include <machine/tlb.h> 164176770Sraj 165176770Sraj/* 166176770Sraj * 1st level - page table directory (pdir) 167176770Sraj * 168176770Sraj * pdir consists of 1024 entries, each being a pointer to 169176770Sraj * second level entity, i.e. the actual page table (ptbl). 170176770Sraj */ 171176770Sraj#define PDIR_SHIFT 22 172176770Sraj#define PDIR_SIZE (1 << PDIR_SHIFT) /* va range mapped by pdir */ 173176770Sraj#define PDIR_MASK (~(PDIR_SIZE - 1)) 174176770Sraj#define PDIR_NENTRIES 1024 /* number of page tables in pdir */ 175176770Sraj 176176770Sraj/* Returns pdir entry number for given va */ 177176770Sraj#define PDIR_IDX(va) ((va) >> PDIR_SHIFT) 178176770Sraj 179176770Sraj#define PDIR_ENTRY_SHIFT 2 /* entry size is 2^2 = 4 bytes */ 180176770Sraj 181176770Sraj/* 182176770Sraj * 2nd level - page table (ptbl) 183176770Sraj * 184176770Sraj * Page table covers 1024 page table entries. Page 185176770Sraj * table entry (pte) is 32 bit wide and defines mapping 186176770Sraj * for a single page. 187176770Sraj */ 188176770Sraj#define PTBL_SHIFT PAGE_SHIFT 189176770Sraj#define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */ 190209975Snwhitehorn#define PTBL_MASK ((PDIR_SIZE - 1) & ~((1 << PAGE_SHIFT) - 1)) 191176770Sraj#define PTBL_NENTRIES 1024 /* number of pages mapped by ptbl */ 192176770Sraj 193176770Sraj/* Returns ptbl entry number for given va */ 194176770Sraj#define PTBL_IDX(va) (((va) & PTBL_MASK) >> PTBL_SHIFT) 195176770Sraj 196176770Sraj/* Size of ptbl in pages, 1024 entries, each sizeof(struct pte_entry). */ 197176770Sraj#define PTBL_PAGES 2 198176770Sraj#define PTBL_ENTRY_SHIFT 3 /* entry size is 2^3 = 8 bytes */ 199176770Sraj 200176770Sraj/* 201176770Sraj * Flags for pte_remove() routine. 202176770Sraj */ 203176770Sraj#define PTBL_HOLD 0x00000001 /* do not unhold ptbl pages */ 204176770Sraj#define PTBL_UNHOLD 0x00000002 /* unhold and attempt to free ptbl pages */ 205176770Sraj 206176770Sraj#define PTBL_HOLD_FLAG(pmap) (((pmap) == kernel_pmap) ? PTBL_HOLD : PTBL_UNHOLD) 207176770Sraj 208176770Sraj/* 209176770Sraj * Page Table Entry definitions and macros. 210287015Sjhibbits * 211287015Sjhibbits * RPN need only be 32-bit because Book-E has 36-bit addresses, and the smallest 212287015Sjhibbits * page size is 4k (12-bit mask), so RPN can really fit into 24 bits. 213176770Sraj */ 214176770Sraj#ifndef LOCORE 215295520Sjhibbitstypedef uint64_t pte_t; 216176770Sraj#endif 217176770Sraj 218176770Sraj/* RPN mask, TLB0 4K pages */ 219176770Sraj#define PTE_PA_MASK PAGE_MASK 220176770Sraj 221236141Sraj#if defined(BOOKE_E500) 222236141Sraj 223176770Sraj/* PTE bits assigned to MAS2, MAS3 flags */ 224295520Sjhibbits#define PTE_MAS2_SHIFT 19 225295520Sjhibbits#define PTE_W (MAS2_W << PTE_MAS2_SHIFT) 226295520Sjhibbits#define PTE_I (MAS2_I << PTE_MAS2_SHIFT) 227295520Sjhibbits#define PTE_M (MAS2_M << PTE_MAS2_SHIFT) 228295520Sjhibbits#define PTE_G (MAS2_G << PTE_MAS2_SHIFT) 229176770Sraj#define PTE_MAS2_MASK (MAS2_G | MAS2_M | MAS2_I | MAS2_W) 230176770Sraj 231295520Sjhibbits#define PTE_MAS3_SHIFT 2 232176770Sraj#define PTE_UX (MAS3_UX << PTE_MAS3_SHIFT) 233176770Sraj#define PTE_SX (MAS3_SX << PTE_MAS3_SHIFT) 234176770Sraj#define PTE_UW (MAS3_UW << PTE_MAS3_SHIFT) 235176770Sraj#define PTE_SW (MAS3_SW << PTE_MAS3_SHIFT) 236176770Sraj#define PTE_UR (MAS3_UR << PTE_MAS3_SHIFT) 237176770Sraj#define PTE_SR (MAS3_SR << PTE_MAS3_SHIFT) 238176770Sraj#define PTE_MAS3_MASK ((MAS3_UX | MAS3_SX | MAS3_UW \ 239176770Sraj | MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT) 240176770Sraj 241295520Sjhibbits#define PTE_PS_SHIFT 8 242295520Sjhibbits#define PTE_PS_4KB (2 << PTE_PS_SHIFT) 243295520Sjhibbits 244236141Sraj#elif defined(BOOKE_PPC4XX) 245236141Sraj 246236141Sraj#define PTE_WL1 TLB_WL1 247236141Sraj#define PTE_IL2I TLB_IL2I 248236141Sraj#define PTE_IL2D TLB_IL2D 249236141Sraj 250236141Sraj#define PTE_W TLB_W 251236141Sraj#define PTE_I TLB_I 252236141Sraj#define PTE_M TLB_M 253236141Sraj#define PTE_G TLB_G 254236141Sraj 255236141Sraj#define PTE_UX TLB_UX 256236141Sraj#define PTE_SX TLB_SX 257236141Sraj#define PTE_UW TLB_UW 258236141Sraj#define PTE_SW TLB_SW 259236141Sraj#define PTE_UR TLB_UR 260236141Sraj#define PTE_SR TLB_SR 261236141Sraj 262236141Sraj#endif 263236141Sraj 264176770Sraj/* Other PTE flags */ 265295520Sjhibbits#define PTE_VALID 0x00000001 /* Valid */ 266295520Sjhibbits#define PTE_MODIFIED 0x00001000 /* Modified */ 267295520Sjhibbits#define PTE_WIRED 0x00002000 /* Wired */ 268295520Sjhibbits#define PTE_MANAGED 0x00000002 /* Managed */ 269295520Sjhibbits#define PTE_REFERENCED 0x00040000 /* Referenced */ 270176770Sraj 271176770Sraj/* Macro argument must of pte_t type. */ 272295520Sjhibbits#define PTE_ARPN_SHIFT 12 273295642Sjhibbits#define PTE_FLAGS_MASK 0x00ffffff 274295520Sjhibbits#define PTE_RPN_FROM_PA(pa) (((pa) & ~PAGE_MASK) << PTE_ARPN_SHIFT) 275295520Sjhibbits#define PTE_PA(pte) ((vm_paddr_t)(*pte >> PTE_ARPN_SHIFT) & ~PAGE_MASK) 276295520Sjhibbits#define PTE_ISVALID(pte) ((*pte) & PTE_VALID) 277295520Sjhibbits#define PTE_ISWIRED(pte) ((*pte) & PTE_WIRED) 278295520Sjhibbits#define PTE_ISMANAGED(pte) ((*pte) & PTE_MANAGED) 279295520Sjhibbits#define PTE_ISMODIFIED(pte) ((*pte) & PTE_MODIFIED) 280295520Sjhibbits#define PTE_ISREFERENCED(pte) ((*pte) & PTE_REFERENCED) 281176770Sraj 282285148Sjhibbits#endif /* BOOKE */ 283176770Sraj#endif /* _MACHINE_PTE_H_ */ 284