1139825Simp/*- 277957Sbenno * Copyright (c) 1997 Per Fogelstrom, Opsycon AB and RTMX Inc, USA. 377957Sbenno * 477957Sbenno * Redistribution and use in source and binary forms, with or without 577957Sbenno * modification, are permitted provided that the following conditions 677957Sbenno * are met: 777957Sbenno * 1. Redistributions of source code must retain the above copyright 877957Sbenno * notice, this list of conditions and the following disclaimer. 977957Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1077957Sbenno * notice, this list of conditions and the following disclaimer in the 1177957Sbenno * documentation and/or other materials provided with the distribution. 1277957Sbenno * 3. All advertising materials mentioning features or use of this software 1377957Sbenno * must display the following acknowledgement: 1477957Sbenno * This product includes software developed under OpenBSD by 1577957Sbenno * Per Fogelstrom Opsycon AB for RTMX Inc, North Carolina, USA. 1677957Sbenno * 4. The name of the author may not be used to endorse or promote products 1777957Sbenno * derived from this software without specific prior written permission. 1877957Sbenno * 1977957Sbenno * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 2077957Sbenno * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 2177957Sbenno * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2277957Sbenno * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 2377957Sbenno * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2477957Sbenno * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2577957Sbenno * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2677957Sbenno * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2777957Sbenno * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2877957Sbenno * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2977957Sbenno * SUCH DAMAGE. 3077957Sbenno * 3177957Sbenno * $NetBSD: pio.h,v 1.1 1998/05/15 10:15:54 tsubai Exp $ 3277957Sbenno * $OpenBSD: pio.h,v 1.1 1997/10/13 10:53:47 pefo Exp $ 3377957Sbenno * $FreeBSD: releng/11.0/sys/powerpc/include/pio.h 235013 2012-05-04 16:00:22Z nwhitehorn $ 3477957Sbenno */ 3577957Sbenno 3677957Sbenno#ifndef _MACHINE_PIO_H_ 3777957Sbenno#define _MACHINE_PIO_H_ 3877957Sbenno/* 3977957Sbenno * I/O macros. 4077957Sbenno */ 4177957Sbenno 42235013Snwhitehorn/* 43235013Snwhitehorn * Use sync so that bus space operations cannot sneak out the bottom of 44235013Snwhitehorn * mutex-protected sections (mutex release does not guarantee completion of 45235013Snwhitehorn * accesses to caching-inhibited memory on some systems) 46235013Snwhitehorn */ 47235013Snwhitehorn#define powerpc_iomb() __asm __volatile("sync" : : : "memory") 48234579Snwhitehorn 4977957Sbennostatic __inline void 5077957Sbenno__outb(volatile u_int8_t *a, u_int8_t v) 5177957Sbenno{ 5277957Sbenno *a = v; 53234579Snwhitehorn powerpc_iomb(); 5477957Sbenno} 5577957Sbenno 5677957Sbennostatic __inline void 5777957Sbenno__outw(volatile u_int16_t *a, u_int16_t v) 5877957Sbenno{ 5977957Sbenno *a = v; 60234579Snwhitehorn powerpc_iomb(); 6177957Sbenno} 6277957Sbenno 6377957Sbennostatic __inline void 6477957Sbenno__outl(volatile u_int32_t *a, u_int32_t v) 6577957Sbenno{ 6677957Sbenno *a = v; 67234579Snwhitehorn powerpc_iomb(); 6877957Sbenno} 6977957Sbenno 7077957Sbennostatic __inline void 71193578Sraj__outll(volatile u_int64_t *a, u_int64_t v) 72193578Sraj{ 73193578Sraj *a = v; 74234579Snwhitehorn powerpc_iomb(); 75193578Sraj} 76193578Sraj 77193578Srajstatic __inline void 7877957Sbenno__outwrb(volatile u_int16_t *a, u_int16_t v) 7977957Sbenno{ 8077957Sbenno __asm__ volatile("sthbrx %0, 0, %1" :: "r"(v), "r"(a)); 81234579Snwhitehorn powerpc_iomb(); 8277957Sbenno} 8377957Sbenno 8477957Sbennostatic __inline void 8577957Sbenno__outlrb(volatile u_int32_t *a, u_int32_t v) 8677957Sbenno{ 8777957Sbenno __asm__ volatile("stwbrx %0, 0, %1" :: "r"(v), "r"(a)); 88234579Snwhitehorn powerpc_iomb(); 8977957Sbenno} 9077957Sbenno 9177957Sbennostatic __inline u_int8_t 9277957Sbenno__inb(volatile u_int8_t *a) 9377957Sbenno{ 9477957Sbenno u_int8_t _v_; 9577957Sbenno 9677957Sbenno _v_ = *a; 97234579Snwhitehorn powerpc_iomb(); 9877957Sbenno return _v_; 9977957Sbenno} 10077957Sbenno 10177957Sbennostatic __inline u_int16_t 10277957Sbenno__inw(volatile u_int16_t *a) 10377957Sbenno{ 10477957Sbenno u_int16_t _v_; 10577957Sbenno 10677957Sbenno _v_ = *a; 107234579Snwhitehorn powerpc_iomb(); 10877957Sbenno return _v_; 10977957Sbenno} 11077957Sbenno 11177957Sbennostatic __inline u_int32_t 11277957Sbenno__inl(volatile u_int32_t *a) 11377957Sbenno{ 11477957Sbenno u_int32_t _v_; 11577957Sbenno 11677957Sbenno _v_ = *a; 117234579Snwhitehorn powerpc_iomb(); 11877957Sbenno return _v_; 11977957Sbenno} 12077957Sbenno 121193578Srajstatic __inline u_int64_t 122193578Sraj__inll(volatile u_int64_t *a) 123193578Sraj{ 124193578Sraj u_int64_t _v_; 125193578Sraj 126193578Sraj _v_ = *a; 127234579Snwhitehorn powerpc_iomb(); 128193578Sraj return _v_; 129193578Sraj} 130193578Sraj 13177957Sbennostatic __inline u_int16_t 13277957Sbenno__inwrb(volatile u_int16_t *a) 13377957Sbenno{ 13477957Sbenno u_int16_t _v_; 13577957Sbenno 13677957Sbenno __asm__ volatile("lhbrx %0, 0, %1" : "=r"(_v_) : "r"(a)); 137234579Snwhitehorn powerpc_iomb(); 13877957Sbenno return _v_; 13977957Sbenno} 14077957Sbenno 14177957Sbennostatic __inline u_int32_t 14277957Sbenno__inlrb(volatile u_int32_t *a) 14377957Sbenno{ 14477957Sbenno u_int32_t _v_; 14577957Sbenno 14677957Sbenno __asm__ volatile("lwbrx %0, 0, %1" : "=r"(_v_) : "r"(a)); 147234579Snwhitehorn powerpc_iomb(); 14877957Sbenno return _v_; 14977957Sbenno} 15077957Sbenno 15177957Sbenno#define outb(a,v) (__outb((volatile u_int8_t *)(a), v)) 15277957Sbenno#define out8(a,v) outb(a,v) 15377957Sbenno#define outw(a,v) (__outw((volatile u_int16_t *)(a), v)) 15477957Sbenno#define out16(a,v) outw(a,v) 15577957Sbenno#define outl(a,v) (__outl((volatile u_int32_t *)(a), v)) 15677957Sbenno#define out32(a,v) outl(a,v) 157193578Sraj#define outll(a,v) (__outll((volatile u_int64_t *)(a), v)) 158193578Sraj#define out64(a,v) outll(a,v) 15977957Sbenno#define inb(a) (__inb((volatile u_int8_t *)(a))) 16077957Sbenno#define in8(a) inb(a) 16177957Sbenno#define inw(a) (__inw((volatile u_int16_t *)(a))) 16277957Sbenno#define in16(a) inw(a) 16377957Sbenno#define inl(a) (__inl((volatile u_int32_t *)(a))) 16477957Sbenno#define in32(a) inl(a) 165193578Sraj#define inll(a) (__inll((volatile u_int64_t *)(a))) 166193578Sraj#define in64(a) inll(a) 16777957Sbenno 16877957Sbenno#define out8rb(a,v) outb(a,v) 16977957Sbenno#define outwrb(a,v) (__outwrb((volatile u_int16_t *)(a), v)) 17077957Sbenno#define out16rb(a,v) outwrb(a,v) 17177957Sbenno#define outlrb(a,v) (__outlrb((volatile u_int32_t *)(a), v)) 17277957Sbenno#define out32rb(a,v) outlrb(a,v) 17377957Sbenno#define in8rb(a) inb(a) 17477957Sbenno#define inwrb(a) (__inwrb((volatile u_int16_t *)(a))) 17577957Sbenno#define in16rb(a) inwrb(a) 17677957Sbenno#define inlrb(a) (__inlrb((volatile u_int32_t *)(a))) 17777957Sbenno#define in32rb(a) inlrb(a) 17877957Sbenno 17977957Sbenno 18077957Sbennostatic __inline void 18177957Sbenno__outsb(volatile u_int8_t *a, const u_int8_t *s, size_t c) 18277957Sbenno{ 18377957Sbenno while (c--) 18477957Sbenno *a = *s++; 185234579Snwhitehorn powerpc_iomb(); 18677957Sbenno} 18777957Sbenno 18877957Sbennostatic __inline void 18977957Sbenno__outsw(volatile u_int16_t *a, const u_int16_t *s, size_t c) 19077957Sbenno{ 19177957Sbenno while (c--) 19277957Sbenno *a = *s++; 193234579Snwhitehorn powerpc_iomb(); 19477957Sbenno} 19577957Sbenno 19677957Sbennostatic __inline void 19777957Sbenno__outsl(volatile u_int32_t *a, const u_int32_t *s, size_t c) 19877957Sbenno{ 19977957Sbenno while (c--) 20077957Sbenno *a = *s++; 201234579Snwhitehorn powerpc_iomb(); 20277957Sbenno} 20377957Sbenno 20477957Sbennostatic __inline void 205193578Sraj__outsll(volatile u_int64_t *a, const u_int64_t *s, size_t c) 206193578Sraj{ 207193578Sraj while (c--) 208193578Sraj *a = *s++; 209234579Snwhitehorn powerpc_iomb(); 210193578Sraj} 211193578Sraj 212193578Srajstatic __inline void 21377957Sbenno__outswrb(volatile u_int16_t *a, const u_int16_t *s, size_t c) 21477957Sbenno{ 21577957Sbenno while (c--) 21677957Sbenno __asm__ volatile("sthbrx %0, 0, %1" :: "r"(*s++), "r"(a)); 217234579Snwhitehorn powerpc_iomb(); 21877957Sbenno} 21977957Sbenno 22077957Sbennostatic __inline void 22177957Sbenno__outslrb(volatile u_int32_t *a, const u_int32_t *s, size_t c) 22277957Sbenno{ 22377957Sbenno while (c--) 22477957Sbenno __asm__ volatile("stwbrx %0, 0, %1" :: "r"(*s++), "r"(a)); 225234579Snwhitehorn powerpc_iomb(); 22677957Sbenno} 22777957Sbenno 22877957Sbennostatic __inline void 22977957Sbenno__insb(volatile u_int8_t *a, u_int8_t *d, size_t c) 23077957Sbenno{ 23177957Sbenno while (c--) 23277957Sbenno *d++ = *a; 233234579Snwhitehorn powerpc_iomb(); 23477957Sbenno} 23577957Sbenno 23677957Sbennostatic __inline void 23777957Sbenno__insw(volatile u_int16_t *a, u_int16_t *d, size_t c) 23877957Sbenno{ 23977957Sbenno while (c--) 24077957Sbenno *d++ = *a; 241234579Snwhitehorn powerpc_iomb(); 24277957Sbenno} 24377957Sbenno 24477957Sbennostatic __inline void 24577957Sbenno__insl(volatile u_int32_t *a, u_int32_t *d, size_t c) 24677957Sbenno{ 24777957Sbenno while (c--) 24877957Sbenno *d++ = *a; 249234579Snwhitehorn powerpc_iomb(); 25077957Sbenno} 25177957Sbenno 25277957Sbennostatic __inline void 253193578Sraj__insll(volatile u_int64_t *a, u_int64_t *d, size_t c) 254193578Sraj{ 255193578Sraj while (c--) 256193578Sraj *d++ = *a; 257234579Snwhitehorn powerpc_iomb(); 258193578Sraj} 259193578Sraj 260193578Srajstatic __inline void 26177957Sbenno__inswrb(volatile u_int16_t *a, u_int16_t *d, size_t c) 26277957Sbenno{ 26377957Sbenno while (c--) 26477957Sbenno __asm__ volatile("lhbrx %0, 0, %1" : "=r"(*d++) : "r"(a)); 265234579Snwhitehorn powerpc_iomb(); 26677957Sbenno} 26777957Sbenno 26877957Sbennostatic __inline void 26977957Sbenno__inslrb(volatile u_int32_t *a, u_int32_t *d, size_t c) 27077957Sbenno{ 27177957Sbenno while (c--) 27277957Sbenno __asm__ volatile("lwbrx %0, 0, %1" : "=r"(*d++) : "r"(a)); 273234579Snwhitehorn powerpc_iomb(); 27477957Sbenno} 27577957Sbenno 27677957Sbenno#define outsb(a,s,c) (__outsb((volatile u_int8_t *)(a), s, c)) 27777957Sbenno#define outs8(a,s,c) outsb(a,s,c) 27877957Sbenno#define outsw(a,s,c) (__outsw((volatile u_int16_t *)(a), s, c)) 27977957Sbenno#define outs16(a,s,c) outsw(a,s,c) 28077957Sbenno#define outsl(a,s,c) (__outsl((volatile u_int32_t *)(a), s, c)) 28177957Sbenno#define outs32(a,s,c) outsl(a,s,c) 282193578Sraj#define outsll(a,s,c) (__outsll((volatile u_int64_t *)(a), s, c)) 283193578Sraj#define outs64(a,s,c) outsll(a,s,c) 28477957Sbenno#define insb(a,d,c) (__insb((volatile u_int8_t *)(a), d, c)) 28577957Sbenno#define ins8(a,d,c) insb(a,d,c) 28677957Sbenno#define insw(a,d,c) (__insw((volatile u_int16_t *)(a), d, c)) 28777957Sbenno#define ins16(a,d,c) insw(a,d,c) 28877957Sbenno#define insl(a,d,c) (__insl((volatile u_int32_t *)(a), d, c)) 28977957Sbenno#define ins32(a,d,c) insl(a,d,c) 290193578Sraj#define insll(a,d,c) (__insll((volatile u_int64_t *)(a), d, c)) 291193578Sraj#define ins64(a,d,c) insll(a,d,c) 29277957Sbenno 29377957Sbenno#define outs8rb(a,s,c) outsb(a,s,c) 29477957Sbenno#define outswrb(a,s,c) (__outswrb((volatile u_int16_t *)(a), s, c)) 29577957Sbenno#define outs16rb(a,s,c) outswrb(a,s,c) 29677957Sbenno#define outslrb(a,s,c) (__outslrb((volatile u_int32_t *)(a), s, c)) 29777957Sbenno#define outs32rb(a,s,c) outslrb(a,s,c) 29877957Sbenno#define ins8rb(a,d,c) insb(a,d,c) 29977957Sbenno#define inswrb(a,d,c) (__inswrb((volatile u_int16_t *)(a), d, c)) 30077957Sbenno#define ins16rb(a,d,c) inswrb(a,d,c) 30177957Sbenno#define inslrb(a,d,c) (__inslrb((volatile u_int32_t *)(a), d, c)) 30277957Sbenno#define ins32rb(a,d,c) inslrb(a,d,c) 30377957Sbenno 30477957Sbenno#endif /*_MACHINE_PIO_H_*/ 305