openpicreg.h revision 99654
179037Sbenno/*- 279037Sbenno * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 379037Sbenno * 479037Sbenno * Redistribution and use in source and binary forms, with or without 579037Sbenno * modification, are permitted provided that the following conditions 679037Sbenno * are met: 779037Sbenno * 1. Redistributions of source code must retain the above copyright 879037Sbenno * notice, this list of conditions and the following disclaimer. 979037Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1079037Sbenno * notice, this list of conditions and the following disclaimer in the 1179037Sbenno * documentation and/or other materials provided with the distribution. 1279037Sbenno * 3. The name of the author may not be used to endorse or promote products 1379037Sbenno * derived from this software without specific prior written permission. 1479037Sbenno * 1579037Sbenno * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1679037Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1779037Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1879037Sbenno * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1979037Sbenno * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2079037Sbenno * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2179037Sbenno * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2279037Sbenno * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2379037Sbenno * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2479037Sbenno * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2579037Sbenno * 2699654Sbenno * from NetBSD: openpicreg.h,v 1.3 2001/08/30 03:08:52 briggs Exp 2779037Sbenno * $FreeBSD: head/sys/powerpc/include/openpicreg.h 99654 2002-07-09 11:26:10Z benno $ 2879037Sbenno */ 2979037Sbenno 3079037Sbenno/* 3199654Sbenno * Size of OpenPIC register space 3299654Sbenno */ 3399654Sbenno#define OPENPIC_SIZE 0x40000 3499654Sbenno 3599654Sbenno/* 3679037Sbenno * GLOBAL/TIMER register (IDU base + 0x1000) 3779037Sbenno */ 3879037Sbenno 3979037Sbenno/* feature reporting reg 0 */ 4099654Sbenno#define OPENPIC_FEATURE 0x1000 4199654Sbenno#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff 4299654Sbenno#define OPENPIC_FEATURE_LAST_CPU_MASK 0x00001f00 4399654Sbenno#define OPENPIC_FEATURE_LAST_CPU_SHIFT 8 4499654Sbenno#define OPENPIC_FEATURE_LAST_IRQ_MASK 0x07ff0000 4599654Sbenno#define OPENPIC_FEATURE_LAST_IRQ_SHIFT 16 4679037Sbenno 4779037Sbenno/* global config reg 0 */ 4899654Sbenno#define OPENPIC_CONFIG 0x1020 4999654Sbenno#define OPENPIC_CONFIG_RESET 0x80000000 5099654Sbenno#define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000 5179037Sbenno 5299654Sbenno/* interrupt configuration mode (direct or serial) */ 5399654Sbenno#define OPENPIC_ICR 0x1030 5499654Sbenno#define OPENPIC_ICR_SERIAL_MODE (1 << 27) 5599654Sbenno#define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28) 5699654Sbenno#define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28 5799654Sbenno 5879037Sbenno/* vendor ID */ 5999654Sbenno#define OPENPIC_VENDOR_ID 0x1080 6079037Sbenno 6179037Sbenno/* processor initialization reg */ 6299654Sbenno#define OPENPIC_PROC_INIT 0x1090 6379037Sbenno 6479037Sbenno/* IPI vector/priority reg */ 6599654Sbenno#define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10) 6679037Sbenno 6779037Sbenno/* spurious intr. vector */ 6899654Sbenno#define OPENPIC_SPURIOUS_VECTOR 0x10e0 6979037Sbenno 7079037Sbenno 7179037Sbenno/* 7279037Sbenno * INTERRUPT SOURCE register (IDU base + 0x10000) 7379037Sbenno */ 7479037Sbenno 7579037Sbenno/* interrupt vector/priority reg */ 7699654Sbenno#ifndef OPENPIC_SRC_VECTOR 7799654Sbenno#define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20) 7879037Sbenno#endif 7999654Sbenno#define OPENPIC_SENSE_LEVEL 0x00400000 8099654Sbenno#define OPENPIC_SENSE_EDGE 0x00000000 8199654Sbenno#define OPENPIC_POLARITY_POSITIVE 0x00800000 8299654Sbenno#define OPENPIC_POLARITY_NEGATIVE 0x00000000 8399654Sbenno#define OPENPIC_IMASK 0x80000000 8499654Sbenno#define OPENPIC_ACTIVITY 0x40000000 8599654Sbenno#define OPENPIC_PRIORITY_MASK 0x000f0000 8699654Sbenno#define OPENPIC_PRIORITY_SHIFT 16 8799654Sbenno#define OPENPIC_VECTOR_MASK 0x000000ff 8879037Sbenno 8979037Sbenno/* interrupt destination cpu */ 9099654Sbenno#ifndef OPENPIC_IDEST 9199654Sbenno#define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20) 9279037Sbenno#endif 9379037Sbenno 9479037Sbenno/* 9579037Sbenno * PROCESSOR register (IDU base + 0x20000) 9679037Sbenno */ 9779037Sbenno 9879037Sbenno/* IPI command reg */ 9999654Sbenno#define OPENPIC_IPI(cpu, ipi) (0x20040 + (cpu) * 0x1000 + (ipi)) 10079037Sbenno 10179037Sbenno/* current task priority reg */ 10299654Sbenno#define OPENPIC_CPU_PRIORITY(cpu) (0x20080 + (cpu) * 0x1000) 10399654Sbenno#define OPENPIC_CPU_PRIORITY_MASK 0x0000000f 10479037Sbenno 10579037Sbenno/* interrupt acknowledge reg */ 10699654Sbenno#define OPENPIC_IACK(cpu) (0x200a0 + (cpu) * 0x1000) 10779037Sbenno 10879037Sbenno/* end of interrupt reg */ 10999654Sbenno#define OPENPIC_EOI(cpu) (0x200b0 + (cpu) * 0x1000) 110