openpicreg.h revision 79037
179037Sbenno/*- 279037Sbenno * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 379037Sbenno * 479037Sbenno * Redistribution and use in source and binary forms, with or without 579037Sbenno * modification, are permitted provided that the following conditions 679037Sbenno * are met: 779037Sbenno * 1. Redistributions of source code must retain the above copyright 879037Sbenno * notice, this list of conditions and the following disclaimer. 979037Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1079037Sbenno * notice, this list of conditions and the following disclaimer in the 1179037Sbenno * documentation and/or other materials provided with the distribution. 1279037Sbenno * 3. The name of the author may not be used to endorse or promote products 1379037Sbenno * derived from this software without specific prior written permission. 1479037Sbenno * 1579037Sbenno * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1679037Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1779037Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1879037Sbenno * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1979037Sbenno * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2079037Sbenno * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2179037Sbenno * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2279037Sbenno * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2379037Sbenno * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2479037Sbenno * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2579037Sbenno * 2679037Sbenno * $NetBSD: openpicreg.h,v 1.2 2001/02/05 19:22:23 briggs Exp $ 2779037Sbenno * $FreeBSD: head/sys/powerpc/include/openpicreg.h 79037 2001-07-01 02:43:38Z benno $ 2879037Sbenno */ 2979037Sbenno 3079037Sbenno/* 3179037Sbenno * GLOBAL/TIMER register (IDU base + 0x1000) 3279037Sbenno */ 3379037Sbenno 3479037Sbenno/* feature reporting reg 0 */ 3579037Sbenno#define OPENPIC_FEATURE 0x1000 3679037Sbenno 3779037Sbenno/* global config reg 0 */ 3879037Sbenno#define OPENPIC_CONFIG 0x1020 3979037Sbenno#define OPENPIC_CONFIG_RESET 0x80000000 4079037Sbenno#define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000 4179037Sbenno 4279037Sbenno/* vendor ID */ 4379037Sbenno#define OPENPIC_VENDOR_ID 0x1080 4479037Sbenno 4579037Sbenno/* processor initialization reg */ 4679037Sbenno#define OPENPIC_PROC_INIT 0x1090 4779037Sbenno 4879037Sbenno/* IPI vector/priority reg */ 4979037Sbenno#define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10) 5079037Sbenno 5179037Sbenno/* spurious intr. vector */ 5279037Sbenno#define OPENPIC_SPURIOUS_VECTOR 0x10e0 5379037Sbenno 5479037Sbenno 5579037Sbenno/* 5679037Sbenno * INTERRUPT SOURCE register (IDU base + 0x10000) 5779037Sbenno */ 5879037Sbenno 5979037Sbenno/* interrupt vector/priority reg */ 6079037Sbenno#ifndef OPENPIC_SRC_VECTOR 6179037Sbenno#define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20) 6279037Sbenno#endif 6379037Sbenno#define OPENPIC_SENSE_LEVEL 0x00400000 6479037Sbenno#define OPENPIC_SENSE_EDGE 0x00000000 6579037Sbenno#define OPENPIC_POLARITY_POSITIVE 0x00800000 6679037Sbenno#define OPENPIC_POLARITY_NEGATIVE 0x00000000 6779037Sbenno#define OPENPIC_IMASK 0x80000000 6879037Sbenno#define OPENPIC_ACTIVITY 0x40000000 6979037Sbenno#define OPENPIC_PRIORITY_MASK 0x000f0000 7079037Sbenno#define OPENPIC_PRIORITY_SHIFT 16 7179037Sbenno#define OPENPIC_VECTOR_MASK 0x000000ff 7279037Sbenno 7379037Sbenno/* interrupt destination cpu */ 7479037Sbenno#ifndef OPENPIC_IDEST 7579037Sbenno#define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20) 7679037Sbenno#endif 7779037Sbenno 7879037Sbenno/* 7979037Sbenno * PROCESSOR register (IDU base + 0x20000) 8079037Sbenno */ 8179037Sbenno 8279037Sbenno/* IPI command reg */ 8379037Sbenno#define OPENPIC_IPI(cpu, ipi) (0x20040 + (cpu) * 0x1000 + (ipi)) 8479037Sbenno 8579037Sbenno/* current task priority reg */ 8679037Sbenno#define OPENPIC_CPU_PRIORITY(cpu) (0x20080 + (cpu) * 0x1000) 8779037Sbenno#define OPENPIC_CPU_PRIORITY_MASK 0x0000000f 8879037Sbenno 8979037Sbenno/* interrupt acknowledge reg */ 9079037Sbenno#define OPENPIC_IACK(cpu) (0x200a0 + (cpu) * 0x1000) 9179037Sbenno 9279037Sbenno/* end of interrupt reg */ 9379037Sbenno#define OPENPIC_EOI(cpu) (0x200b0 + (cpu) * 0x1000) 94