openpicreg.h revision 259676
179037Sbenno/*- 279037Sbenno * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 379037Sbenno * 479037Sbenno * Redistribution and use in source and binary forms, with or without 579037Sbenno * modification, are permitted provided that the following conditions 679037Sbenno * are met: 779037Sbenno * 1. Redistributions of source code must retain the above copyright 879037Sbenno * notice, this list of conditions and the following disclaimer. 979037Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1079037Sbenno * notice, this list of conditions and the following disclaimer in the 1179037Sbenno * documentation and/or other materials provided with the distribution. 1279037Sbenno * 3. The name of the author may not be used to endorse or promote products 1379037Sbenno * derived from this software without specific prior written permission. 1479037Sbenno * 1579037Sbenno * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1679037Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1779037Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1879037Sbenno * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1979037Sbenno * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2079037Sbenno * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2179037Sbenno * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2279037Sbenno * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2379037Sbenno * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2479037Sbenno * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2579037Sbenno * 2699654Sbenno * from NetBSD: openpicreg.h,v 1.3 2001/08/30 03:08:52 briggs Exp 2779037Sbenno * $FreeBSD: head/sys/powerpc/include/openpicreg.h 259676 2013-12-21 04:31:54Z jhibbits $ 2879037Sbenno */ 2979037Sbenno 3079037Sbenno/* 3199654Sbenno * Size of OpenPIC register space 3299654Sbenno */ 3399654Sbenno#define OPENPIC_SIZE 0x40000 3499654Sbenno 3599654Sbenno/* 36176208Smarcel * Per Processor Registers [private access] (0x00000 - 0x00fff) 3779037Sbenno */ 3879037Sbenno 39176208Smarcel/* IPI dispatch command reg */ 40176208Smarcel#define OPENPIC_IPI_DISPATCH(ipi) (0x40 + (ipi) * 0x10) 41176208Smarcel 42176208Smarcel/* current task priority reg */ 43176208Smarcel#define OPENPIC_TPR 0x80 44176208Smarcel#define OPENPIC_TPR_MASK 0x0000000f 45176208Smarcel 46176208Smarcel#define OPENPIC_WHOAMI 0x90 47176208Smarcel 48176208Smarcel/* interrupt acknowledge reg */ 49176208Smarcel#define OPENPIC_IACK 0xa0 50176208Smarcel 51176208Smarcel/* end of interrupt reg */ 52176208Smarcel#define OPENPIC_EOI 0xb0 53176208Smarcel 54176208Smarcel/* 55176208Smarcel * Global registers (0x01000-0x0ffff) 56176208Smarcel */ 57176208Smarcel 5879037Sbenno/* feature reporting reg 0 */ 5999654Sbenno#define OPENPIC_FEATURE 0x1000 60176208Smarcel#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff 61176208Smarcel#define OPENPIC_FEATURE_LAST_CPU_MASK 0x00001f00 62176208Smarcel#define OPENPIC_FEATURE_LAST_CPU_SHIFT 8 63176208Smarcel#define OPENPIC_FEATURE_LAST_IRQ_MASK 0x07ff0000 64176208Smarcel#define OPENPIC_FEATURE_LAST_IRQ_SHIFT 16 6579037Sbenno 6679037Sbenno/* global config reg 0 */ 6799654Sbenno#define OPENPIC_CONFIG 0x1020 6899654Sbenno#define OPENPIC_CONFIG_RESET 0x80000000 6999654Sbenno#define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000 7079037Sbenno 7199654Sbenno/* interrupt configuration mode (direct or serial) */ 7299654Sbenno#define OPENPIC_ICR 0x1030 73176208Smarcel#define OPENPIC_ICR_SERIAL_MODE (1 << 27) 74176208Smarcel#define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28) 75176208Smarcel#define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28 7699654Sbenno 7779037Sbenno/* vendor ID */ 7899654Sbenno#define OPENPIC_VENDOR_ID 0x1080 7979037Sbenno 8079037Sbenno/* processor initialization reg */ 8199654Sbenno#define OPENPIC_PROC_INIT 0x1090 8279037Sbenno 8379037Sbenno/* IPI vector/priority reg */ 8499654Sbenno#define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10) 8579037Sbenno 8679037Sbenno/* spurious intr. vector */ 8799654Sbenno#define OPENPIC_SPURIOUS_VECTOR 0x10e0 8879037Sbenno 89176208Smarcel/* Timer registers */ 90176208Smarcel#define OPENPIC_TIMERS 4 91176208Smarcel#define OPENPIC_TFREQ 0x10f0 92176208Smarcel#define OPENPIC_TCNT(t) (0x1100 + (t) * 0x40) 93176208Smarcel#define OPENPIC_TBASE(t) (0x1110 + (t) * 0x40) 94176208Smarcel#define OPENPIC_TVEC(t) (0x1120 + (t) * 0x40) 95176208Smarcel#define OPENPIC_TDST(t) (0x1130 + (t) * 0x40) 9679037Sbenno 9779037Sbenno/* 98176208Smarcel * Interrupt Source Configuration Registers (0x10000 - 0x1ffff) 9979037Sbenno */ 10079037Sbenno 10179037Sbenno/* interrupt vector/priority reg */ 102259676Sjhibbits#define OPENPIC_SRC_VECTOR_COUNT 64 10399654Sbenno#ifndef OPENPIC_SRC_VECTOR 10499654Sbenno#define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20) 10579037Sbenno#endif 10699654Sbenno#define OPENPIC_SENSE_LEVEL 0x00400000 10799654Sbenno#define OPENPIC_SENSE_EDGE 0x00000000 10899654Sbenno#define OPENPIC_POLARITY_POSITIVE 0x00800000 10999654Sbenno#define OPENPIC_POLARITY_NEGATIVE 0x00000000 11099654Sbenno#define OPENPIC_IMASK 0x80000000 11199654Sbenno#define OPENPIC_ACTIVITY 0x40000000 11299654Sbenno#define OPENPIC_PRIORITY_MASK 0x000f0000 11399654Sbenno#define OPENPIC_PRIORITY_SHIFT 16 11499654Sbenno#define OPENPIC_VECTOR_MASK 0x000000ff 11579037Sbenno 11679037Sbenno/* interrupt destination cpu */ 11799654Sbenno#ifndef OPENPIC_IDEST 11899654Sbenno#define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20) 11979037Sbenno#endif 12079037Sbenno 12179037Sbenno/* 122176208Smarcel * Per Processor Registers [global access] (0x20000 - 0x3ffff) 12379037Sbenno */ 12479037Sbenno 125176208Smarcel#define OPENPIC_PCPU_BASE(cpu) (0x20000 + (cpu) * 0x1000) 12679037Sbenno 127176208Smarcel#define OPENPIC_PCPU_IPI_DISPATCH(cpu, ipi) \ 128176208Smarcel (OPENPIC_PCPU_BASE(cpu) + OPENPIC_IPI_DISPATCH(ipi)) 12979037Sbenno 130176208Smarcel#define OPENPIC_PCPU_TPR(cpu) \ 131176208Smarcel (OPENPIC_PCPU_BASE(cpu) + OPENPIC_TPR) 13279037Sbenno 133176208Smarcel#define OPENPIC_PCPU_WHOAMI(cpu) \ 134176208Smarcel (OPENPIC_PCPU_BASE(cpu) + OPENPIC_WHOAMI) 135176208Smarcel 136176208Smarcel#define OPENPIC_PCPU_IACK(cpu) \ 137176208Smarcel (OPENPIC_PCPU_BASE(cpu) + OPENPIC_IACK) 138176208Smarcel 139176208Smarcel#define OPENPIC_PCPU_EOI(cpu) \ 140176208Smarcel (OPENPIC_PCPU_BASE(cpu) + OPENPIC_EOI) 141176208Smarcel 142