mmu_oea64.c revision 277157
182899Sjake/*- 282899Sjake * Copyright (c) 2001 The NetBSD Foundation, Inc. 380708Sjake * All rights reserved. 480708Sjake * 582899Sjake * This code is derived from software contributed to The NetBSD Foundation 682899Sjake * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 782899Sjake * 882899Sjake * Redistribution and use in source and binary forms, with or without 980708Sjake * modification, are permitted provided that the following conditions 1080708Sjake * are met: 1180708Sjake * 1. Redistributions of source code must retain the above copyright 1280708Sjake * notice, this list of conditions and the following disclaimer. 1380708Sjake * 2. Redistributions in binary form must reproduce the above copyright 1480708Sjake * notice, this list of conditions and the following disclaimer in the 1580708Sjake * documentation and/or other materials provided with the distribution. 1680708Sjake * 1782899Sjake * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 1882899Sjake * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 1982899Sjake * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2082899Sjake * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2182899Sjake * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2282899Sjake * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2382899Sjake * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2480708Sjake * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2582899Sjake * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2680708Sjake * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2780708Sjake * POSSIBILITY OF SUCH DAMAGE. 2882899Sjake */ 2980708Sjake/*- 3080708Sjake * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3180708Sjake * Copyright (C) 1995, 1996 TooLs GmbH. 3280708Sjake * All rights reserved. 3380708Sjake * 3480708Sjake * Redistribution and use in source and binary forms, with or without 3580708Sjake * modification, are permitted provided that the following conditions 3680708Sjake * are met: 3782899Sjake * 1. Redistributions of source code must retain the above copyright 3882899Sjake * notice, this list of conditions and the following disclaimer. 3982899Sjake * 2. Redistributions in binary form must reproduce the above copyright 4080708Sjake * notice, this list of conditions and the following disclaimer in the 4180708Sjake * documentation and/or other materials provided with the distribution. 4280708Sjake * 3. All advertising materials mentioning features or use of this software 4380708Sjake * must display the following acknowledgement: 4480708Sjake * This product includes software developed by TooLs GmbH. 4580708Sjake * 4. The name of TooLs GmbH may not be used to endorse or promote products 4680709Sjake * derived from this software without specific prior written permission. 4780709Sjake * 4888651Sjake * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 4988651Sjake * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 5088651Sjake * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 5188651Sjake * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 5288651Sjake * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 5380709Sjake * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 5480709Sjake * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 5580709Sjake * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 5680709Sjake * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 5788651Sjake * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 5888651Sjake * 5980709Sjake * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 6088651Sjake */ 6180709Sjake/*- 6283053Sobrien * Copyright (C) 2001 Benno Rice. 6388651Sjake * All rights reserved. 6488651Sjake * 6588651Sjake * Redistribution and use in source and binary forms, with or without 6680708Sjake * modification, are permitted provided that the following conditions 6780708Sjake * are met: 6883053Sobrien * 1. Redistributions of source code must retain the above copyright 6988651Sjake * notice, this list of conditions and the following disclaimer. 7088651Sjake * 2. Redistributions in binary form must reproduce the above copyright 7188651Sjake * notice, this list of conditions and the following disclaimer in the 7288651Sjake * documentation and/or other materials provided with the distribution. 7380709Sjake * 7480709Sjake * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 7580709Sjake * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 7680709Sjake * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 7780708Sjake * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 7880708Sjake * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 7988651Sjake * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 8088651Sjake * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 8188651Sjake * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 8288651Sjake * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 8388651Sjake * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8488651Sjake */ 8588651Sjake 8688651Sjake#include <sys/cdefs.h> 8785241Sjake__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea64.c 277157 2015-01-14 02:18:29Z nwhitehorn $"); 8880708Sjake 8984844Stmm/* 9088826Stmm * Manages physical address maps. 9180708Sjake * 9288651Sjake * Since the information managed by this module is also stored by the 9388651Sjake * logical address mapping module, this module may throw away valid virtual 9488651Sjake * to physical mappings at almost any time. However, invalidations of 9589041Sjake * mappings must be done as requested. 9689041Sjake * 9784844Stmm * In order to cope with hardware architectures which make virtual to 9884844Stmm * physical map invalidates expensive, this module may delay invalidate 9980708Sjake * reduced protection operations until such time as they are actually 10080708Sjake * necessary. This module is given full information as to which processors 10188651Sjake * are currently using which maps, and to when physical maps must be made 10288651Sjake * correct. 10380708Sjake */ 10480708Sjake 10580708Sjake#include "opt_compat.h" 10688651Sjake#include "opt_kstack_pages.h" 10780708Sjake 10888651Sjake#include <sys/param.h> 10988651Sjake#include <sys/kernel.h> 11085241Sjake#include <sys/conf.h> 11185241Sjake#include <sys/queue.h> 11281087Sjake#include <sys/cpuset.h> 11388651Sjake#include <sys/kerneldump.h> 11481087Sjake#include <sys/ktr.h> 11588651Sjake#include <sys/lock.h> 11688651Sjake#include <sys/msgbuf.h> 11788651Sjake#include <sys/malloc.h> 11888651Sjake#include <sys/mutex.h> 11981087Sjake#include <sys/proc.h> 12081087Sjake#include <sys/rwlock.h> 12180708Sjake#include <sys/sched.h> 122#include <sys/sysctl.h> 123#include <sys/systm.h> 124#include <sys/vmmeter.h> 125 126#include <sys/kdb.h> 127 128#include <dev/ofw/openfirm.h> 129 130#include <vm/vm.h> 131#include <vm/vm_param.h> 132#include <vm/vm_kern.h> 133#include <vm/vm_page.h> 134#include <vm/vm_map.h> 135#include <vm/vm_object.h> 136#include <vm/vm_extern.h> 137#include <vm/vm_pageout.h> 138#include <vm/uma.h> 139 140#include <machine/_inttypes.h> 141#include <machine/cpu.h> 142#include <machine/platform.h> 143#include <machine/frame.h> 144#include <machine/md_var.h> 145#include <machine/psl.h> 146#include <machine/bat.h> 147#include <machine/hid.h> 148#include <machine/pte.h> 149#include <machine/sr.h> 150#include <machine/trap.h> 151#include <machine/mmuvar.h> 152 153#include "mmu_oea64.h" 154#include "mmu_if.h" 155#include "moea64_if.h" 156 157void moea64_release_vsid(uint64_t vsid); 158uintptr_t moea64_get_unique_vsid(void); 159 160#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 161#define ENABLE_TRANS(msr) mtmsr(msr) 162 163#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 164#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 165#define VSID_HASH_MASK 0x0000007fffffffffULL 166 167/* 168 * Locking semantics: 169 * -- Read lock: if no modifications are being made to either the PVO lists 170 * or page table or if any modifications being made result in internal 171 * changes (e.g. wiring, protection) such that the existence of the PVOs 172 * is unchanged and they remain associated with the same pmap (in which 173 * case the changes should be protected by the pmap lock) 174 * -- Write lock: required if PTEs/PVOs are being inserted or removed. 175 */ 176 177#define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock) 178#define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock) 179#define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock) 180#define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock) 181 182struct ofw_map { 183 cell_t om_va; 184 cell_t om_len; 185 uint64_t om_pa; 186 cell_t om_mode; 187}; 188 189extern unsigned char _etext[]; 190extern unsigned char _end[]; 191 192extern int ofw_real_mode; 193 194/* 195 * Map of physical memory regions. 196 */ 197static struct mem_region *regions; 198static struct mem_region *pregions; 199static u_int phys_avail_count; 200static int regions_sz, pregions_sz; 201 202extern void bs_remap_earlyboot(void); 203 204/* 205 * Lock for the pteg and pvo tables. 206 */ 207struct rwlock moea64_table_lock; 208struct mtx moea64_slb_mutex; 209 210/* 211 * PTEG data. 212 */ 213u_int moea64_pteg_count; 214u_int moea64_pteg_mask; 215 216/* 217 * PVO data. 218 */ 219struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 220 221uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 222uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 223 224#define BPVO_POOL_SIZE 327680 225static struct pvo_entry *moea64_bpvo_pool; 226static int moea64_bpvo_pool_index = 0; 227SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 228 &moea64_bpvo_pool_index, 0, ""); 229 230#define VSID_NBPW (sizeof(u_int32_t) * 8) 231#ifdef __powerpc64__ 232#define NVSIDS (NPMAPS * 16) 233#define VSID_HASHMASK 0xffffffffUL 234#else 235#define NVSIDS NPMAPS 236#define VSID_HASHMASK 0xfffffUL 237#endif 238static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 239 240static boolean_t moea64_initialized = FALSE; 241 242/* 243 * Statistics. 244 */ 245u_int moea64_pte_valid = 0; 246u_int moea64_pte_overflow = 0; 247u_int moea64_pvo_entries = 0; 248u_int moea64_pvo_enter_calls = 0; 249u_int moea64_pvo_remove_calls = 0; 250SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 251 &moea64_pte_valid, 0, ""); 252SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 253 &moea64_pte_overflow, 0, ""); 254SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 255 &moea64_pvo_entries, 0, ""); 256SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 257 &moea64_pvo_enter_calls, 0, ""); 258SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 259 &moea64_pvo_remove_calls, 0, ""); 260 261vm_offset_t moea64_scratchpage_va[2]; 262struct pvo_entry *moea64_scratchpage_pvo[2]; 263uintptr_t moea64_scratchpage_pte[2]; 264struct mtx moea64_scratchpage_mtx; 265 266uint64_t moea64_large_page_mask = 0; 267uint64_t moea64_large_page_size = 0; 268int moea64_large_page_shift = 0; 269 270/* 271 * PVO calls. 272 */ 273static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 274 vm_offset_t, vm_offset_t, uint64_t, int, int8_t); 275static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 276static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 277 278/* 279 * Utility routines. 280 */ 281static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 282static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 283static void moea64_kremove(mmu_t, vm_offset_t); 284static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 285 vm_offset_t pa, vm_size_t sz); 286 287/* 288 * Kernel MMU interface 289 */ 290void moea64_clear_modify(mmu_t, vm_page_t); 291void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 292void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 293 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 294int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 295 u_int flags, int8_t psind); 296void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 297 vm_prot_t); 298void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 299vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 300vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 301void moea64_init(mmu_t); 302boolean_t moea64_is_modified(mmu_t, vm_page_t); 303boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 304boolean_t moea64_is_referenced(mmu_t, vm_page_t); 305int moea64_ts_referenced(mmu_t, vm_page_t); 306vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 307boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 308int moea64_page_wired_mappings(mmu_t, vm_page_t); 309void moea64_pinit(mmu_t, pmap_t); 310void moea64_pinit0(mmu_t, pmap_t); 311void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 312void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 313void moea64_qremove(mmu_t, vm_offset_t, int); 314void moea64_release(mmu_t, pmap_t); 315void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 316void moea64_remove_pages(mmu_t, pmap_t); 317void moea64_remove_all(mmu_t, vm_page_t); 318void moea64_remove_write(mmu_t, vm_page_t); 319void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 320void moea64_zero_page(mmu_t, vm_page_t); 321void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 322void moea64_zero_page_idle(mmu_t, vm_page_t); 323void moea64_activate(mmu_t, struct thread *); 324void moea64_deactivate(mmu_t, struct thread *); 325void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 326void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 327void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 328vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 329void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 330void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 331void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 332boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 333static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 334void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 335 void **va); 336void moea64_scan_init(mmu_t mmu); 337 338static mmu_method_t moea64_methods[] = { 339 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 340 MMUMETHOD(mmu_copy_page, moea64_copy_page), 341 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 342 MMUMETHOD(mmu_enter, moea64_enter), 343 MMUMETHOD(mmu_enter_object, moea64_enter_object), 344 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 345 MMUMETHOD(mmu_extract, moea64_extract), 346 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 347 MMUMETHOD(mmu_init, moea64_init), 348 MMUMETHOD(mmu_is_modified, moea64_is_modified), 349 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 350 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 351 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 352 MMUMETHOD(mmu_map, moea64_map), 353 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 354 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 355 MMUMETHOD(mmu_pinit, moea64_pinit), 356 MMUMETHOD(mmu_pinit0, moea64_pinit0), 357 MMUMETHOD(mmu_protect, moea64_protect), 358 MMUMETHOD(mmu_qenter, moea64_qenter), 359 MMUMETHOD(mmu_qremove, moea64_qremove), 360 MMUMETHOD(mmu_release, moea64_release), 361 MMUMETHOD(mmu_remove, moea64_remove), 362 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 363 MMUMETHOD(mmu_remove_all, moea64_remove_all), 364 MMUMETHOD(mmu_remove_write, moea64_remove_write), 365 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 366 MMUMETHOD(mmu_unwire, moea64_unwire), 367 MMUMETHOD(mmu_zero_page, moea64_zero_page), 368 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 369 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 370 MMUMETHOD(mmu_activate, moea64_activate), 371 MMUMETHOD(mmu_deactivate, moea64_deactivate), 372 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 373 374 /* Internal interfaces */ 375 MMUMETHOD(mmu_mapdev, moea64_mapdev), 376 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 377 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 378 MMUMETHOD(mmu_kextract, moea64_kextract), 379 MMUMETHOD(mmu_kenter, moea64_kenter), 380 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 381 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 382 MMUMETHOD(mmu_scan_init, moea64_scan_init), 383 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 384 385 { 0, 0 } 386}; 387 388MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 389 390static __inline u_int 391va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 392{ 393 uint64_t hash; 394 int shift; 395 396 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 397 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 398 shift); 399 return (hash & moea64_pteg_mask); 400} 401 402static __inline struct pvo_head * 403vm_page_to_pvoh(vm_page_t m) 404{ 405 406 return (&m->md.mdpg_pvoh); 407} 408 409static __inline void 410moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 411 uint64_t pte_lo, int flags) 412{ 413 414 /* 415 * Construct a PTE. Default to IMB initially. Valid bit only gets 416 * set when the real pte is set in memory. 417 * 418 * Note: Don't set the valid bit for correct operation of tlb update. 419 */ 420 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 421 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 422 423 if (flags & PVO_LARGE) 424 pt->pte_hi |= LPTE_BIG; 425 426 pt->pte_lo = pte_lo; 427} 428 429static __inline uint64_t 430moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 431{ 432 uint64_t pte_lo; 433 int i; 434 435 if (ma != VM_MEMATTR_DEFAULT) { 436 switch (ma) { 437 case VM_MEMATTR_UNCACHEABLE: 438 return (LPTE_I | LPTE_G); 439 case VM_MEMATTR_WRITE_COMBINING: 440 case VM_MEMATTR_WRITE_BACK: 441 case VM_MEMATTR_PREFETCHABLE: 442 return (LPTE_I); 443 case VM_MEMATTR_WRITE_THROUGH: 444 return (LPTE_W | LPTE_M); 445 } 446 } 447 448 /* 449 * Assume the page is cache inhibited and access is guarded unless 450 * it's in our available memory array. 451 */ 452 pte_lo = LPTE_I | LPTE_G; 453 for (i = 0; i < pregions_sz; i++) { 454 if ((pa >= pregions[i].mr_start) && 455 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 456 pte_lo &= ~(LPTE_I | LPTE_G); 457 pte_lo |= LPTE_M; 458 break; 459 } 460 } 461 462 return pte_lo; 463} 464 465/* 466 * Quick sort callout for comparing memory regions. 467 */ 468static int om_cmp(const void *a, const void *b); 469 470static int 471om_cmp(const void *a, const void *b) 472{ 473 const struct ofw_map *mapa; 474 const struct ofw_map *mapb; 475 476 mapa = a; 477 mapb = b; 478 if (mapa->om_pa < mapb->om_pa) 479 return (-1); 480 else if (mapa->om_pa > mapb->om_pa) 481 return (1); 482 else 483 return (0); 484} 485 486static void 487moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 488{ 489 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 490 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 491 register_t msr; 492 vm_offset_t off; 493 vm_paddr_t pa_base; 494 int i, j; 495 496 bzero(translations, sz); 497 OF_getprop(OF_finddevice("/"), "#address-cells", &acells, 498 sizeof(acells)); 499 if (OF_getprop(mmu, "translations", trans_cells, sz) == -1) 500 panic("moea64_bootstrap: can't get ofw translations"); 501 502 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 503 sz /= sizeof(cell_t); 504 for (i = 0, j = 0; i < sz; j++) { 505 translations[j].om_va = trans_cells[i++]; 506 translations[j].om_len = trans_cells[i++]; 507 translations[j].om_pa = trans_cells[i++]; 508 if (acells == 2) { 509 translations[j].om_pa <<= 32; 510 translations[j].om_pa |= trans_cells[i++]; 511 } 512 translations[j].om_mode = trans_cells[i++]; 513 } 514 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 515 i, sz)); 516 517 sz = j; 518 qsort(translations, sz, sizeof (*translations), om_cmp); 519 520 for (i = 0; i < sz; i++) { 521 pa_base = translations[i].om_pa; 522 #ifndef __powerpc64__ 523 if ((translations[i].om_pa >> 32) != 0) 524 panic("OFW translations above 32-bit boundary!"); 525 #endif 526 527 if (pa_base % PAGE_SIZE) 528 panic("OFW translation not page-aligned (phys)!"); 529 if (translations[i].om_va % PAGE_SIZE) 530 panic("OFW translation not page-aligned (virt)!"); 531 532 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 533 pa_base, translations[i].om_va, translations[i].om_len); 534 535 /* Now enter the pages for this mapping */ 536 537 DISABLE_TRANS(msr); 538 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 539 /* If this address is direct-mapped, skip remapping */ 540 if (hw_direct_map && translations[i].om_va == pa_base && 541 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) == LPTE_M) 542 continue; 543 544 if (moea64_pvo_find_va(kernel_pmap, 545 translations[i].om_va + off) != NULL) 546 continue; 547 548 moea64_kenter(mmup, translations[i].om_va + off, 549 pa_base + off); 550 } 551 ENABLE_TRANS(msr); 552 } 553} 554 555#ifdef __powerpc64__ 556static void 557moea64_probe_large_page(void) 558{ 559 uint16_t pvr = mfpvr() >> 16; 560 561 switch (pvr) { 562 case IBM970: 563 case IBM970FX: 564 case IBM970MP: 565 powerpc_sync(); isync(); 566 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 567 powerpc_sync(); isync(); 568 569 /* FALLTHROUGH */ 570 default: 571 moea64_large_page_size = 0x1000000; /* 16 MB */ 572 moea64_large_page_shift = 24; 573 } 574 575 moea64_large_page_mask = moea64_large_page_size - 1; 576} 577 578static void 579moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 580{ 581 struct slb *cache; 582 struct slb entry; 583 uint64_t esid, slbe; 584 uint64_t i; 585 586 cache = PCPU_GET(slb); 587 esid = va >> ADDR_SR_SHFT; 588 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 589 590 for (i = 0; i < 64; i++) { 591 if (cache[i].slbe == (slbe | i)) 592 return; 593 } 594 595 entry.slbe = slbe; 596 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 597 if (large) 598 entry.slbv |= SLBV_L; 599 600 slb_insert_kernel(entry.slbe, entry.slbv); 601} 602#endif 603 604static void 605moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 606 vm_offset_t kernelend) 607{ 608 register_t msr; 609 vm_paddr_t pa; 610 vm_offset_t size, off; 611 uint64_t pte_lo; 612 int i; 613 614 if (moea64_large_page_size == 0) 615 hw_direct_map = 0; 616 617 DISABLE_TRANS(msr); 618 if (hw_direct_map) { 619 LOCK_TABLE_WR(); 620 PMAP_LOCK(kernel_pmap); 621 for (i = 0; i < pregions_sz; i++) { 622 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 623 pregions[i].mr_size; pa += moea64_large_page_size) { 624 pte_lo = LPTE_M; 625 626 /* 627 * Set memory access as guarded if prefetch within 628 * the page could exit the available physmem area. 629 */ 630 if (pa & moea64_large_page_mask) { 631 pa &= moea64_large_page_mask; 632 pte_lo |= LPTE_G; 633 } 634 if (pa + moea64_large_page_size > 635 pregions[i].mr_start + pregions[i].mr_size) 636 pte_lo |= LPTE_G; 637 638 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 639 NULL, pa, pa, pte_lo, 640 PVO_WIRED | PVO_LARGE, 0); 641 } 642 } 643 PMAP_UNLOCK(kernel_pmap); 644 UNLOCK_TABLE_WR(); 645 } else { 646 size = sizeof(struct pvo_head) * moea64_pteg_count; 647 off = (vm_offset_t)(moea64_pvo_table); 648 for (pa = off; pa < off + size; pa += PAGE_SIZE) 649 moea64_kenter(mmup, pa, pa); 650 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 651 off = (vm_offset_t)(moea64_bpvo_pool); 652 for (pa = off; pa < off + size; pa += PAGE_SIZE) 653 moea64_kenter(mmup, pa, pa); 654 655 /* 656 * Map certain important things, like ourselves. 657 * 658 * NOTE: We do not map the exception vector space. That code is 659 * used only in real mode, and leaving it unmapped allows us to 660 * catch NULL pointer deferences, instead of making NULL a valid 661 * address. 662 */ 663 664 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 665 pa += PAGE_SIZE) 666 moea64_kenter(mmup, pa, pa); 667 } 668 ENABLE_TRANS(msr); 669 670 /* 671 * Allow user to override unmapped_buf_allowed for testing. 672 * XXXKIB Only direct map implementation was tested. 673 */ 674 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 675 &unmapped_buf_allowed)) 676 unmapped_buf_allowed = hw_direct_map; 677} 678 679void 680moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 681{ 682 int i, j; 683 vm_size_t physsz, hwphyssz; 684 685#ifndef __powerpc64__ 686 /* We don't have a direct map since there is no BAT */ 687 hw_direct_map = 0; 688 689 /* Make sure battable is zero, since we have no BAT */ 690 for (i = 0; i < 16; i++) { 691 battable[i].batu = 0; 692 battable[i].batl = 0; 693 } 694#else 695 moea64_probe_large_page(); 696 697 /* Use a direct map if we have large page support */ 698 if (moea64_large_page_size > 0) 699 hw_direct_map = 1; 700 else 701 hw_direct_map = 0; 702#endif 703 704 /* Get physical memory regions from firmware */ 705 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 706 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 707 708 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 709 panic("moea64_bootstrap: phys_avail too small"); 710 711 phys_avail_count = 0; 712 physsz = 0; 713 hwphyssz = 0; 714 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 715 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 716 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 717 regions[i].mr_start, regions[i].mr_start + 718 regions[i].mr_size, regions[i].mr_size); 719 if (hwphyssz != 0 && 720 (physsz + regions[i].mr_size) >= hwphyssz) { 721 if (physsz < hwphyssz) { 722 phys_avail[j] = regions[i].mr_start; 723 phys_avail[j + 1] = regions[i].mr_start + 724 hwphyssz - physsz; 725 physsz = hwphyssz; 726 phys_avail_count++; 727 } 728 break; 729 } 730 phys_avail[j] = regions[i].mr_start; 731 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 732 phys_avail_count++; 733 physsz += regions[i].mr_size; 734 } 735 736 /* Check for overlap with the kernel and exception vectors */ 737 for (j = 0; j < 2*phys_avail_count; j+=2) { 738 if (phys_avail[j] < EXC_LAST) 739 phys_avail[j] += EXC_LAST; 740 741 if (kernelstart >= phys_avail[j] && 742 kernelstart < phys_avail[j+1]) { 743 if (kernelend < phys_avail[j+1]) { 744 phys_avail[2*phys_avail_count] = 745 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 746 phys_avail[2*phys_avail_count + 1] = 747 phys_avail[j+1]; 748 phys_avail_count++; 749 } 750 751 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 752 } 753 754 if (kernelend >= phys_avail[j] && 755 kernelend < phys_avail[j+1]) { 756 if (kernelstart > phys_avail[j]) { 757 phys_avail[2*phys_avail_count] = phys_avail[j]; 758 phys_avail[2*phys_avail_count + 1] = 759 kernelstart & ~PAGE_MASK; 760 phys_avail_count++; 761 } 762 763 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 764 } 765 } 766 767 physmem = btoc(physsz); 768 769#ifdef PTEGCOUNT 770 moea64_pteg_count = PTEGCOUNT; 771#else 772 moea64_pteg_count = 0x1000; 773 774 while (moea64_pteg_count < physmem) 775 moea64_pteg_count <<= 1; 776 777 moea64_pteg_count >>= 1; 778#endif /* PTEGCOUNT */ 779} 780 781void 782moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 783{ 784 vm_size_t size; 785 register_t msr; 786 int i; 787 788 /* 789 * Set PTEG mask 790 */ 791 moea64_pteg_mask = moea64_pteg_count - 1; 792 793 /* 794 * Allocate pv/overflow lists. 795 */ 796 size = sizeof(struct pvo_head) * moea64_pteg_count; 797 798 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 799 PAGE_SIZE); 800 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 801 802 DISABLE_TRANS(msr); 803 for (i = 0; i < moea64_pteg_count; i++) 804 LIST_INIT(&moea64_pvo_table[i]); 805 ENABLE_TRANS(msr); 806 807 /* 808 * Initialize the lock that synchronizes access to the pteg and pvo 809 * tables. 810 */ 811 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE); 812 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 813 814 /* 815 * Initialise the unmanaged pvo pool. 816 */ 817 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 818 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 819 moea64_bpvo_pool_index = 0; 820 821 /* 822 * Make sure kernel vsid is allocated as well as VSID 0. 823 */ 824 #ifndef __powerpc64__ 825 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 826 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 827 moea64_vsid_bitmap[0] |= 1; 828 #endif 829 830 /* 831 * Initialize the kernel pmap (which is statically allocated). 832 */ 833 #ifdef __powerpc64__ 834 for (i = 0; i < 64; i++) { 835 pcpup->pc_slb[i].slbv = 0; 836 pcpup->pc_slb[i].slbe = 0; 837 } 838 #else 839 for (i = 0; i < 16; i++) 840 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 841 #endif 842 843 kernel_pmap->pmap_phys = kernel_pmap; 844 CPU_FILL(&kernel_pmap->pm_active); 845 RB_INIT(&kernel_pmap->pmap_pvo); 846 847 PMAP_LOCK_INIT(kernel_pmap); 848 849 /* 850 * Now map in all the other buffers we allocated earlier 851 */ 852 853 moea64_setup_direct_map(mmup, kernelstart, kernelend); 854} 855 856void 857moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 858{ 859 ihandle_t mmui; 860 phandle_t chosen; 861 phandle_t mmu; 862 ssize_t sz; 863 int i; 864 vm_offset_t pa, va; 865 void *dpcpu; 866 867 /* 868 * Set up the Open Firmware pmap and add its mappings if not in real 869 * mode. 870 */ 871 872 chosen = OF_finddevice("/chosen"); 873 if (!ofw_real_mode && chosen != -1 && 874 OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 875 mmu = OF_instance_to_package(mmui); 876 if (mmu == -1 || 877 (sz = OF_getproplen(mmu, "translations")) == -1) 878 sz = 0; 879 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 880 panic("moea64_bootstrap: too many ofw translations"); 881 882 if (sz > 0) 883 moea64_add_ofw_mappings(mmup, mmu, sz); 884 } 885 886 /* 887 * Calculate the last available physical address. 888 */ 889 for (i = 0; phys_avail[i + 2] != 0; i += 2) 890 ; 891 Maxmem = powerpc_btop(phys_avail[i + 1]); 892 893 /* 894 * Initialize MMU and remap early physical mappings 895 */ 896 MMU_CPU_BOOTSTRAP(mmup,0); 897 mtmsr(mfmsr() | PSL_DR | PSL_IR); 898 pmap_bootstrapped++; 899 bs_remap_earlyboot(); 900 901 /* 902 * Set the start and end of kva. 903 */ 904 virtual_avail = VM_MIN_KERNEL_ADDRESS; 905 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 906 907 /* 908 * Map the entire KVA range into the SLB. We must not fault there. 909 */ 910 #ifdef __powerpc64__ 911 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 912 moea64_bootstrap_slb_prefault(va, 0); 913 #endif 914 915 /* 916 * Figure out how far we can extend virtual_end into segment 16 917 * without running into existing mappings. Segment 16 is guaranteed 918 * to contain neither RAM nor devices (at least on Apple hardware), 919 * but will generally contain some OFW mappings we should not 920 * step on. 921 */ 922 923 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 924 PMAP_LOCK(kernel_pmap); 925 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 926 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 927 virtual_end += PAGE_SIZE; 928 PMAP_UNLOCK(kernel_pmap); 929 #endif 930 931 /* 932 * Allocate a kernel stack with a guard page for thread0 and map it 933 * into the kernel page map. 934 */ 935 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 936 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 937 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 938 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 939 thread0.td_kstack = va; 940 thread0.td_kstack_pages = KSTACK_PAGES; 941 for (i = 0; i < KSTACK_PAGES; i++) { 942 moea64_kenter(mmup, va, pa); 943 pa += PAGE_SIZE; 944 va += PAGE_SIZE; 945 } 946 947 /* 948 * Allocate virtual address space for the message buffer. 949 */ 950 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 951 msgbufp = (struct msgbuf *)virtual_avail; 952 va = virtual_avail; 953 virtual_avail += round_page(msgbufsize); 954 while (va < virtual_avail) { 955 moea64_kenter(mmup, va, pa); 956 pa += PAGE_SIZE; 957 va += PAGE_SIZE; 958 } 959 960 /* 961 * Allocate virtual address space for the dynamic percpu area. 962 */ 963 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 964 dpcpu = (void *)virtual_avail; 965 va = virtual_avail; 966 virtual_avail += DPCPU_SIZE; 967 while (va < virtual_avail) { 968 moea64_kenter(mmup, va, pa); 969 pa += PAGE_SIZE; 970 va += PAGE_SIZE; 971 } 972 dpcpu_init(dpcpu, 0); 973 974 /* 975 * Allocate some things for page zeroing. We put this directly 976 * in the page table, marked with LPTE_LOCKED, to avoid any 977 * of the PVO book-keeping or other parts of the VM system 978 * from even knowing that this hack exists. 979 */ 980 981 if (!hw_direct_map) { 982 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 983 MTX_DEF); 984 for (i = 0; i < 2; i++) { 985 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 986 virtual_end -= PAGE_SIZE; 987 988 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 989 990 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 991 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 992 LOCK_TABLE_RD(); 993 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 994 mmup, moea64_scratchpage_pvo[i]); 995 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 996 |= LPTE_LOCKED; 997 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 998 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 999 moea64_scratchpage_pvo[i]->pvo_vpn); 1000 UNLOCK_TABLE_RD(); 1001 } 1002 } 1003} 1004 1005/* 1006 * Activate a user pmap. The pmap must be activated before its address 1007 * space can be accessed in any way. 1008 */ 1009void 1010moea64_activate(mmu_t mmu, struct thread *td) 1011{ 1012 pmap_t pm; 1013 1014 pm = &td->td_proc->p_vmspace->vm_pmap; 1015 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1016 1017 #ifdef __powerpc64__ 1018 PCPU_SET(userslb, pm->pm_slb); 1019 #else 1020 PCPU_SET(curpmap, pm->pmap_phys); 1021 #endif 1022} 1023 1024void 1025moea64_deactivate(mmu_t mmu, struct thread *td) 1026{ 1027 pmap_t pm; 1028 1029 pm = &td->td_proc->p_vmspace->vm_pmap; 1030 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1031 #ifdef __powerpc64__ 1032 PCPU_SET(userslb, NULL); 1033 #else 1034 PCPU_SET(curpmap, NULL); 1035 #endif 1036} 1037 1038void 1039moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1040{ 1041 struct pvo_entry key, *pvo; 1042 uintptr_t pt; 1043 1044 LOCK_TABLE_RD(); 1045 PMAP_LOCK(pm); 1046 key.pvo_vaddr = sva; 1047 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1048 pvo != NULL && PVO_VADDR(pvo) < eva; 1049 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1050 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1051 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1052 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1053 pvo); 1054 pvo->pvo_vaddr &= ~PVO_WIRED; 1055 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_WIRED) == 0) 1056 panic("moea64_unwire: pte %p is missing LPTE_WIRED", 1057 &pvo->pvo_pte.lpte); 1058 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1059 if (pt != -1) { 1060 /* 1061 * The PTE's wired attribute is not a hardware 1062 * feature, so there is no need to invalidate any TLB 1063 * entries. 1064 */ 1065 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1066 pvo->pvo_vpn); 1067 } 1068 pm->pm_stats.wired_count--; 1069 } 1070 UNLOCK_TABLE_RD(); 1071 PMAP_UNLOCK(pm); 1072} 1073 1074/* 1075 * This goes through and sets the physical address of our 1076 * special scratch PTE to the PA we want to zero or copy. Because 1077 * of locking issues (this can get called in pvo_enter() by 1078 * the UMA allocator), we can't use most other utility functions here 1079 */ 1080 1081static __inline 1082void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1083 1084 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1085 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1086 1087 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1088 ~(LPTE_WIMG | LPTE_RPGN); 1089 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1090 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1091 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1092 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1093 moea64_scratchpage_pvo[which]->pvo_vpn); 1094 isync(); 1095} 1096 1097void 1098moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1099{ 1100 vm_offset_t dst; 1101 vm_offset_t src; 1102 1103 dst = VM_PAGE_TO_PHYS(mdst); 1104 src = VM_PAGE_TO_PHYS(msrc); 1105 1106 if (hw_direct_map) { 1107 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1108 } else { 1109 mtx_lock(&moea64_scratchpage_mtx); 1110 1111 moea64_set_scratchpage_pa(mmu, 0, src); 1112 moea64_set_scratchpage_pa(mmu, 1, dst); 1113 1114 bcopy((void *)moea64_scratchpage_va[0], 1115 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1116 1117 mtx_unlock(&moea64_scratchpage_mtx); 1118 } 1119} 1120 1121static inline void 1122moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1123 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1124{ 1125 void *a_cp, *b_cp; 1126 vm_offset_t a_pg_offset, b_pg_offset; 1127 int cnt; 1128 1129 while (xfersize > 0) { 1130 a_pg_offset = a_offset & PAGE_MASK; 1131 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1132 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1133 a_pg_offset; 1134 b_pg_offset = b_offset & PAGE_MASK; 1135 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1136 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1137 b_pg_offset; 1138 bcopy(a_cp, b_cp, cnt); 1139 a_offset += cnt; 1140 b_offset += cnt; 1141 xfersize -= cnt; 1142 } 1143} 1144 1145static inline void 1146moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1147 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1148{ 1149 void *a_cp, *b_cp; 1150 vm_offset_t a_pg_offset, b_pg_offset; 1151 int cnt; 1152 1153 mtx_lock(&moea64_scratchpage_mtx); 1154 while (xfersize > 0) { 1155 a_pg_offset = a_offset & PAGE_MASK; 1156 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1157 moea64_set_scratchpage_pa(mmu, 0, 1158 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1159 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1160 b_pg_offset = b_offset & PAGE_MASK; 1161 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1162 moea64_set_scratchpage_pa(mmu, 1, 1163 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1164 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1165 bcopy(a_cp, b_cp, cnt); 1166 a_offset += cnt; 1167 b_offset += cnt; 1168 xfersize -= cnt; 1169 } 1170 mtx_unlock(&moea64_scratchpage_mtx); 1171} 1172 1173void 1174moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1175 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1176{ 1177 1178 if (hw_direct_map) { 1179 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1180 xfersize); 1181 } else { 1182 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1183 xfersize); 1184 } 1185} 1186 1187void 1188moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1189{ 1190 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1191 1192 if (size + off > PAGE_SIZE) 1193 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1194 1195 if (hw_direct_map) { 1196 bzero((caddr_t)pa + off, size); 1197 } else { 1198 mtx_lock(&moea64_scratchpage_mtx); 1199 moea64_set_scratchpage_pa(mmu, 0, pa); 1200 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1201 mtx_unlock(&moea64_scratchpage_mtx); 1202 } 1203} 1204 1205/* 1206 * Zero a page of physical memory by temporarily mapping it 1207 */ 1208void 1209moea64_zero_page(mmu_t mmu, vm_page_t m) 1210{ 1211 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1212 vm_offset_t va, off; 1213 1214 if (!hw_direct_map) { 1215 mtx_lock(&moea64_scratchpage_mtx); 1216 1217 moea64_set_scratchpage_pa(mmu, 0, pa); 1218 va = moea64_scratchpage_va[0]; 1219 } else { 1220 va = pa; 1221 } 1222 1223 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1224 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1225 1226 if (!hw_direct_map) 1227 mtx_unlock(&moea64_scratchpage_mtx); 1228} 1229 1230void 1231moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1232{ 1233 1234 moea64_zero_page(mmu, m); 1235} 1236 1237/* 1238 * Map the given physical page at the specified virtual address in the 1239 * target pmap with the protection requested. If specified the page 1240 * will be wired down. 1241 */ 1242 1243int 1244moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1245 vm_prot_t prot, u_int flags, int8_t psind) 1246{ 1247 struct pvo_head *pvo_head; 1248 uma_zone_t zone; 1249 uint64_t pte_lo; 1250 u_int pvo_flags; 1251 int error; 1252 1253 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1254 VM_OBJECT_ASSERT_LOCKED(m->object); 1255 1256 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1257 pvo_head = NULL; 1258 zone = moea64_upvo_zone; 1259 pvo_flags = 0; 1260 } else { 1261 pvo_head = vm_page_to_pvoh(m); 1262 zone = moea64_mpvo_zone; 1263 pvo_flags = PVO_MANAGED; 1264 } 1265 1266 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1267 1268 if (prot & VM_PROT_WRITE) { 1269 pte_lo |= LPTE_BW; 1270 if (pmap_bootstrapped && 1271 (m->oflags & VPO_UNMANAGED) == 0) 1272 vm_page_aflag_set(m, PGA_WRITEABLE); 1273 } else 1274 pte_lo |= LPTE_BR; 1275 1276 if ((prot & VM_PROT_EXECUTE) == 0) 1277 pte_lo |= LPTE_NOEXEC; 1278 1279 if ((flags & PMAP_ENTER_WIRED) != 0) 1280 pvo_flags |= PVO_WIRED; 1281 1282 for (;;) { 1283 LOCK_TABLE_WR(); 1284 PMAP_LOCK(pmap); 1285 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1286 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags, psind); 1287 PMAP_UNLOCK(pmap); 1288 UNLOCK_TABLE_WR(); 1289 if (error != ENOMEM) 1290 break; 1291 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1292 return (KERN_RESOURCE_SHORTAGE); 1293 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1294 VM_WAIT; 1295 } 1296 1297 /* 1298 * Flush the page from the instruction cache if this page is 1299 * mapped executable and cacheable. 1300 */ 1301 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1302 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1303 vm_page_aflag_set(m, PGA_EXECUTABLE); 1304 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1305 } 1306 return (KERN_SUCCESS); 1307} 1308 1309static void 1310moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1311 vm_size_t sz) 1312{ 1313 1314 /* 1315 * This is much trickier than on older systems because 1316 * we can't sync the icache on physical addresses directly 1317 * without a direct map. Instead we check a couple of cases 1318 * where the memory is already mapped in and, failing that, 1319 * use the same trick we use for page zeroing to create 1320 * a temporary mapping for this physical address. 1321 */ 1322 1323 if (!pmap_bootstrapped) { 1324 /* 1325 * If PMAP is not bootstrapped, we are likely to be 1326 * in real mode. 1327 */ 1328 __syncicache((void *)pa, sz); 1329 } else if (pmap == kernel_pmap) { 1330 __syncicache((void *)va, sz); 1331 } else if (hw_direct_map) { 1332 __syncicache((void *)pa, sz); 1333 } else { 1334 /* Use the scratch page to set up a temp mapping */ 1335 1336 mtx_lock(&moea64_scratchpage_mtx); 1337 1338 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1339 __syncicache((void *)(moea64_scratchpage_va[1] + 1340 (va & ADDR_POFF)), sz); 1341 1342 mtx_unlock(&moea64_scratchpage_mtx); 1343 } 1344} 1345 1346/* 1347 * Maps a sequence of resident pages belonging to the same object. 1348 * The sequence begins with the given page m_start. This page is 1349 * mapped at the given virtual address start. Each subsequent page is 1350 * mapped at a virtual address that is offset from start by the same 1351 * amount as the page is offset from m_start within the object. The 1352 * last page in the sequence is the page with the largest offset from 1353 * m_start that can be mapped at a virtual address less than the given 1354 * virtual address end. Not every virtual page between start and end 1355 * is mapped; only those for which a resident page exists with the 1356 * corresponding offset from m_start are mapped. 1357 */ 1358void 1359moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1360 vm_page_t m_start, vm_prot_t prot) 1361{ 1362 vm_page_t m; 1363 vm_pindex_t diff, psize; 1364 1365 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1366 1367 psize = atop(end - start); 1368 m = m_start; 1369 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1370 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1371 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1372 m = TAILQ_NEXT(m, listq); 1373 } 1374} 1375 1376void 1377moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1378 vm_prot_t prot) 1379{ 1380 1381 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1382 PMAP_ENTER_NOSLEEP, 0); 1383} 1384 1385vm_paddr_t 1386moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1387{ 1388 struct pvo_entry *pvo; 1389 vm_paddr_t pa; 1390 1391 PMAP_LOCK(pm); 1392 pvo = moea64_pvo_find_va(pm, va); 1393 if (pvo == NULL) 1394 pa = 0; 1395 else 1396 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1397 (va - PVO_VADDR(pvo)); 1398 PMAP_UNLOCK(pm); 1399 return (pa); 1400} 1401 1402/* 1403 * Atomically extract and hold the physical page with the given 1404 * pmap and virtual address pair if that mapping permits the given 1405 * protection. 1406 */ 1407vm_page_t 1408moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1409{ 1410 struct pvo_entry *pvo; 1411 vm_page_t m; 1412 vm_paddr_t pa; 1413 1414 m = NULL; 1415 pa = 0; 1416 PMAP_LOCK(pmap); 1417retry: 1418 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1419 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1420 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1421 (prot & VM_PROT_WRITE) == 0)) { 1422 if (vm_page_pa_tryrelock(pmap, 1423 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1424 goto retry; 1425 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1426 vm_page_hold(m); 1427 } 1428 PA_UNLOCK_COND(pa); 1429 PMAP_UNLOCK(pmap); 1430 return (m); 1431} 1432 1433static mmu_t installed_mmu; 1434 1435static void * 1436moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1437{ 1438 /* 1439 * This entire routine is a horrible hack to avoid bothering kmem 1440 * for new KVA addresses. Because this can get called from inside 1441 * kmem allocation routines, calling kmem for a new address here 1442 * can lead to multiply locking non-recursive mutexes. 1443 */ 1444 vm_offset_t va; 1445 1446 vm_page_t m; 1447 int pflags, needed_lock; 1448 1449 *flags = UMA_SLAB_PRIV; 1450 needed_lock = !PMAP_LOCKED(kernel_pmap); 1451 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED; 1452 1453 for (;;) { 1454 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1455 if (m == NULL) { 1456 if (wait & M_NOWAIT) 1457 return (NULL); 1458 VM_WAIT; 1459 } else 1460 break; 1461 } 1462 1463 va = VM_PAGE_TO_PHYS(m); 1464 1465 LOCK_TABLE_WR(); 1466 if (needed_lock) 1467 PMAP_LOCK(kernel_pmap); 1468 1469 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1470 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP, 1471 0); 1472 1473 if (needed_lock) 1474 PMAP_UNLOCK(kernel_pmap); 1475 UNLOCK_TABLE_WR(); 1476 1477 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1478 bzero((void *)va, PAGE_SIZE); 1479 1480 return (void *)va; 1481} 1482 1483extern int elf32_nxstack; 1484 1485void 1486moea64_init(mmu_t mmu) 1487{ 1488 1489 CTR0(KTR_PMAP, "moea64_init"); 1490 1491 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1492 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1493 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1494 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1495 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1496 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1497 1498 if (!hw_direct_map) { 1499 installed_mmu = mmu; 1500 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1501 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1502 } 1503 1504#ifdef COMPAT_FREEBSD32 1505 elf32_nxstack = 1; 1506#endif 1507 1508 moea64_initialized = TRUE; 1509} 1510 1511boolean_t 1512moea64_is_referenced(mmu_t mmu, vm_page_t m) 1513{ 1514 1515 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1516 ("moea64_is_referenced: page %p is not managed", m)); 1517 return (moea64_query_bit(mmu, m, PTE_REF)); 1518} 1519 1520boolean_t 1521moea64_is_modified(mmu_t mmu, vm_page_t m) 1522{ 1523 1524 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1525 ("moea64_is_modified: page %p is not managed", m)); 1526 1527 /* 1528 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1529 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1530 * is clear, no PTEs can have LPTE_CHG set. 1531 */ 1532 VM_OBJECT_ASSERT_LOCKED(m->object); 1533 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1534 return (FALSE); 1535 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1536} 1537 1538boolean_t 1539moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1540{ 1541 struct pvo_entry *pvo; 1542 boolean_t rv; 1543 1544 PMAP_LOCK(pmap); 1545 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1546 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1547 PMAP_UNLOCK(pmap); 1548 return (rv); 1549} 1550 1551void 1552moea64_clear_modify(mmu_t mmu, vm_page_t m) 1553{ 1554 1555 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1556 ("moea64_clear_modify: page %p is not managed", m)); 1557 VM_OBJECT_ASSERT_WLOCKED(m->object); 1558 KASSERT(!vm_page_xbusied(m), 1559 ("moea64_clear_modify: page %p is exclusive busied", m)); 1560 1561 /* 1562 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1563 * set. If the object containing the page is locked and the page is 1564 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1565 */ 1566 if ((m->aflags & PGA_WRITEABLE) == 0) 1567 return; 1568 moea64_clear_bit(mmu, m, LPTE_CHG); 1569} 1570 1571/* 1572 * Clear the write and modified bits in each of the given page's mappings. 1573 */ 1574void 1575moea64_remove_write(mmu_t mmu, vm_page_t m) 1576{ 1577 struct pvo_entry *pvo; 1578 uintptr_t pt; 1579 pmap_t pmap; 1580 uint64_t lo = 0; 1581 1582 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1583 ("moea64_remove_write: page %p is not managed", m)); 1584 1585 /* 1586 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1587 * set by another thread while the object is locked. Thus, 1588 * if PGA_WRITEABLE is clear, no page table entries need updating. 1589 */ 1590 VM_OBJECT_ASSERT_WLOCKED(m->object); 1591 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1592 return; 1593 powerpc_sync(); 1594 LOCK_TABLE_RD(); 1595 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1596 pmap = pvo->pvo_pmap; 1597 PMAP_LOCK(pmap); 1598 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1599 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1600 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1601 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1602 if (pt != -1) { 1603 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1604 lo |= pvo->pvo_pte.lpte.pte_lo; 1605 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1606 MOEA64_PTE_CHANGE(mmu, pt, 1607 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1608 if (pvo->pvo_pmap == kernel_pmap) 1609 isync(); 1610 } 1611 } 1612 if ((lo & LPTE_CHG) != 0) 1613 vm_page_dirty(m); 1614 PMAP_UNLOCK(pmap); 1615 } 1616 UNLOCK_TABLE_RD(); 1617 vm_page_aflag_clear(m, PGA_WRITEABLE); 1618} 1619 1620/* 1621 * moea64_ts_referenced: 1622 * 1623 * Return a count of reference bits for a page, clearing those bits. 1624 * It is not necessary for every reference bit to be cleared, but it 1625 * is necessary that 0 only be returned when there are truly no 1626 * reference bits set. 1627 * 1628 * XXX: The exact number of bits to check and clear is a matter that 1629 * should be tested and standardized at some point in the future for 1630 * optimal aging of shared pages. 1631 */ 1632int 1633moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1634{ 1635 1636 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1637 ("moea64_ts_referenced: page %p is not managed", m)); 1638 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1639} 1640 1641/* 1642 * Modify the WIMG settings of all mappings for a page. 1643 */ 1644void 1645moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1646{ 1647 struct pvo_entry *pvo; 1648 struct pvo_head *pvo_head; 1649 uintptr_t pt; 1650 pmap_t pmap; 1651 uint64_t lo; 1652 1653 if ((m->oflags & VPO_UNMANAGED) != 0) { 1654 m->md.mdpg_cache_attrs = ma; 1655 return; 1656 } 1657 1658 pvo_head = vm_page_to_pvoh(m); 1659 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1660 LOCK_TABLE_RD(); 1661 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1662 pmap = pvo->pvo_pmap; 1663 PMAP_LOCK(pmap); 1664 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1665 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1666 pvo->pvo_pte.lpte.pte_lo |= lo; 1667 if (pt != -1) { 1668 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1669 pvo->pvo_vpn); 1670 if (pvo->pvo_pmap == kernel_pmap) 1671 isync(); 1672 } 1673 PMAP_UNLOCK(pmap); 1674 } 1675 UNLOCK_TABLE_RD(); 1676 m->md.mdpg_cache_attrs = ma; 1677} 1678 1679/* 1680 * Map a wired page into kernel virtual address space. 1681 */ 1682void 1683moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1684{ 1685 uint64_t pte_lo; 1686 int error; 1687 1688 pte_lo = moea64_calc_wimg(pa, ma); 1689 1690 LOCK_TABLE_WR(); 1691 PMAP_LOCK(kernel_pmap); 1692 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1693 NULL, va, pa, pte_lo, PVO_WIRED, 0); 1694 PMAP_UNLOCK(kernel_pmap); 1695 UNLOCK_TABLE_WR(); 1696 1697 if (error != 0 && error != ENOENT) 1698 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1699 pa, error); 1700} 1701 1702void 1703moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1704{ 1705 1706 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1707} 1708 1709/* 1710 * Extract the physical page address associated with the given kernel virtual 1711 * address. 1712 */ 1713vm_paddr_t 1714moea64_kextract(mmu_t mmu, vm_offset_t va) 1715{ 1716 struct pvo_entry *pvo; 1717 vm_paddr_t pa; 1718 1719 /* 1720 * Shortcut the direct-mapped case when applicable. We never put 1721 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1722 */ 1723 if (va < VM_MIN_KERNEL_ADDRESS) 1724 return (va); 1725 1726 PMAP_LOCK(kernel_pmap); 1727 pvo = moea64_pvo_find_va(kernel_pmap, va); 1728 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1729 va)); 1730 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1731 PMAP_UNLOCK(kernel_pmap); 1732 return (pa); 1733} 1734 1735/* 1736 * Remove a wired page from kernel virtual address space. 1737 */ 1738void 1739moea64_kremove(mmu_t mmu, vm_offset_t va) 1740{ 1741 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1742} 1743 1744/* 1745 * Map a range of physical addresses into kernel virtual address space. 1746 * 1747 * The value passed in *virt is a suggested virtual address for the mapping. 1748 * Architectures which can support a direct-mapped physical to virtual region 1749 * can return the appropriate address within that region, leaving '*virt' 1750 * unchanged. We cannot and therefore do not; *virt is updated with the 1751 * first usable address after the mapped region. 1752 */ 1753vm_offset_t 1754moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1755 vm_paddr_t pa_end, int prot) 1756{ 1757 vm_offset_t sva, va; 1758 1759 sva = *virt; 1760 va = sva; 1761 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1762 moea64_kenter(mmu, va, pa_start); 1763 *virt = va; 1764 1765 return (sva); 1766} 1767 1768/* 1769 * Returns true if the pmap's pv is one of the first 1770 * 16 pvs linked to from this page. This count may 1771 * be changed upwards or downwards in the future; it 1772 * is only necessary that true be returned for a small 1773 * subset of pmaps for proper page aging. 1774 */ 1775boolean_t 1776moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1777{ 1778 int loops; 1779 struct pvo_entry *pvo; 1780 boolean_t rv; 1781 1782 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1783 ("moea64_page_exists_quick: page %p is not managed", m)); 1784 loops = 0; 1785 rv = FALSE; 1786 LOCK_TABLE_RD(); 1787 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1788 if (pvo->pvo_pmap == pmap) { 1789 rv = TRUE; 1790 break; 1791 } 1792 if (++loops >= 16) 1793 break; 1794 } 1795 UNLOCK_TABLE_RD(); 1796 return (rv); 1797} 1798 1799/* 1800 * Return the number of managed mappings to the given physical page 1801 * that are wired. 1802 */ 1803int 1804moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1805{ 1806 struct pvo_entry *pvo; 1807 int count; 1808 1809 count = 0; 1810 if ((m->oflags & VPO_UNMANAGED) != 0) 1811 return (count); 1812 LOCK_TABLE_RD(); 1813 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1814 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1815 count++; 1816 UNLOCK_TABLE_RD(); 1817 return (count); 1818} 1819 1820static uintptr_t moea64_vsidcontext; 1821 1822uintptr_t 1823moea64_get_unique_vsid(void) { 1824 u_int entropy; 1825 register_t hash; 1826 uint32_t mask; 1827 int i; 1828 1829 entropy = 0; 1830 __asm __volatile("mftb %0" : "=r"(entropy)); 1831 1832 mtx_lock(&moea64_slb_mutex); 1833 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1834 u_int n; 1835 1836 /* 1837 * Create a new value by mutiplying by a prime and adding in 1838 * entropy from the timebase register. This is to make the 1839 * VSID more random so that the PT hash function collides 1840 * less often. (Note that the prime casues gcc to do shifts 1841 * instead of a multiply.) 1842 */ 1843 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1844 hash = moea64_vsidcontext & (NVSIDS - 1); 1845 if (hash == 0) /* 0 is special, avoid it */ 1846 continue; 1847 n = hash >> 5; 1848 mask = 1 << (hash & (VSID_NBPW - 1)); 1849 hash = (moea64_vsidcontext & VSID_HASHMASK); 1850 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1851 /* anything free in this bucket? */ 1852 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1853 entropy = (moea64_vsidcontext >> 20); 1854 continue; 1855 } 1856 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1857 mask = 1 << i; 1858 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1859 hash |= i; 1860 } 1861 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1862 ("Allocating in-use VSID %#zx\n", hash)); 1863 moea64_vsid_bitmap[n] |= mask; 1864 mtx_unlock(&moea64_slb_mutex); 1865 return (hash); 1866 } 1867 1868 mtx_unlock(&moea64_slb_mutex); 1869 panic("%s: out of segments",__func__); 1870} 1871 1872#ifdef __powerpc64__ 1873void 1874moea64_pinit(mmu_t mmu, pmap_t pmap) 1875{ 1876 1877 RB_INIT(&pmap->pmap_pvo); 1878 1879 pmap->pm_slb_tree_root = slb_alloc_tree(); 1880 pmap->pm_slb = slb_alloc_user_cache(); 1881 pmap->pm_slb_len = 0; 1882} 1883#else 1884void 1885moea64_pinit(mmu_t mmu, pmap_t pmap) 1886{ 1887 int i; 1888 uint32_t hash; 1889 1890 RB_INIT(&pmap->pmap_pvo); 1891 1892 if (pmap_bootstrapped) 1893 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1894 (vm_offset_t)pmap); 1895 else 1896 pmap->pmap_phys = pmap; 1897 1898 /* 1899 * Allocate some segment registers for this pmap. 1900 */ 1901 hash = moea64_get_unique_vsid(); 1902 1903 for (i = 0; i < 16; i++) 1904 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1905 1906 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1907} 1908#endif 1909 1910/* 1911 * Initialize the pmap associated with process 0. 1912 */ 1913void 1914moea64_pinit0(mmu_t mmu, pmap_t pm) 1915{ 1916 1917 PMAP_LOCK_INIT(pm); 1918 moea64_pinit(mmu, pm); 1919 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1920} 1921 1922/* 1923 * Set the physical protection on the specified range of this map as requested. 1924 */ 1925static void 1926moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 1927{ 1928 uintptr_t pt; 1929 struct vm_page *pg; 1930 uint64_t oldlo; 1931 1932 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1933 1934 /* 1935 * Grab the PTE pointer before we diddle with the cached PTE 1936 * copy. 1937 */ 1938 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1939 1940 /* 1941 * Change the protection of the page. 1942 */ 1943 oldlo = pvo->pvo_pte.lpte.pte_lo; 1944 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1945 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1946 if ((prot & VM_PROT_EXECUTE) == 0) 1947 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1948 if (prot & VM_PROT_WRITE) 1949 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW; 1950 else 1951 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1952 1953 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1954 1955 /* 1956 * If the PVO is in the page table, update that pte as well. 1957 */ 1958 if (pt != -1) 1959 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1960 pvo->pvo_vpn); 1961 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 1962 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1963 if ((pg->oflags & VPO_UNMANAGED) == 0) 1964 vm_page_aflag_set(pg, PGA_EXECUTABLE); 1965 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 1966 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE); 1967 } 1968 1969 /* 1970 * Update vm about the REF/CHG bits if the page is managed and we have 1971 * removed write access. 1972 */ 1973 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && 1974 (oldlo & LPTE_PP) != LPTE_BR && !(prot & VM_PROT_WRITE)) { 1975 if (pg != NULL) { 1976 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 1977 vm_page_dirty(pg); 1978 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 1979 vm_page_aflag_set(pg, PGA_REFERENCED); 1980 } 1981 } 1982} 1983 1984void 1985moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1986 vm_prot_t prot) 1987{ 1988 struct pvo_entry *pvo, *tpvo, key; 1989 1990 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 1991 sva, eva, prot); 1992 1993 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1994 ("moea64_protect: non current pmap")); 1995 1996 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1997 moea64_remove(mmu, pm, sva, eva); 1998 return; 1999 } 2000 2001 LOCK_TABLE_RD(); 2002 PMAP_LOCK(pm); 2003 key.pvo_vaddr = sva; 2004 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2005 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2006 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2007 moea64_pvo_protect(mmu, pm, pvo, prot); 2008 } 2009 UNLOCK_TABLE_RD(); 2010 PMAP_UNLOCK(pm); 2011} 2012 2013/* 2014 * Map a list of wired pages into kernel virtual address space. This is 2015 * intended for temporary mappings which do not need page modification or 2016 * references recorded. Existing mappings in the region are overwritten. 2017 */ 2018void 2019moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2020{ 2021 while (count-- > 0) { 2022 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2023 va += PAGE_SIZE; 2024 m++; 2025 } 2026} 2027 2028/* 2029 * Remove page mappings from kernel virtual address space. Intended for 2030 * temporary mappings entered by moea64_qenter. 2031 */ 2032void 2033moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2034{ 2035 while (count-- > 0) { 2036 moea64_kremove(mmu, va); 2037 va += PAGE_SIZE; 2038 } 2039} 2040 2041void 2042moea64_release_vsid(uint64_t vsid) 2043{ 2044 int idx, mask; 2045 2046 mtx_lock(&moea64_slb_mutex); 2047 idx = vsid & (NVSIDS-1); 2048 mask = 1 << (idx % VSID_NBPW); 2049 idx /= VSID_NBPW; 2050 KASSERT(moea64_vsid_bitmap[idx] & mask, 2051 ("Freeing unallocated VSID %#jx", vsid)); 2052 moea64_vsid_bitmap[idx] &= ~mask; 2053 mtx_unlock(&moea64_slb_mutex); 2054} 2055 2056 2057void 2058moea64_release(mmu_t mmu, pmap_t pmap) 2059{ 2060 2061 /* 2062 * Free segment registers' VSIDs 2063 */ 2064 #ifdef __powerpc64__ 2065 slb_free_tree(pmap); 2066 slb_free_user_cache(pmap->pm_slb); 2067 #else 2068 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2069 2070 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2071 #endif 2072} 2073 2074/* 2075 * Remove all pages mapped by the specified pmap 2076 */ 2077void 2078moea64_remove_pages(mmu_t mmu, pmap_t pm) 2079{ 2080 struct pvo_entry *pvo, *tpvo; 2081 2082 LOCK_TABLE_WR(); 2083 PMAP_LOCK(pm); 2084 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2085 if (!(pvo->pvo_vaddr & PVO_WIRED)) 2086 moea64_pvo_remove(mmu, pvo); 2087 } 2088 UNLOCK_TABLE_WR(); 2089 PMAP_UNLOCK(pm); 2090} 2091 2092/* 2093 * Remove the given range of addresses from the specified map. 2094 */ 2095void 2096moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2097{ 2098 struct pvo_entry *pvo, *tpvo, key; 2099 2100 /* 2101 * Perform an unsynchronized read. This is, however, safe. 2102 */ 2103 if (pm->pm_stats.resident_count == 0) 2104 return; 2105 2106 LOCK_TABLE_WR(); 2107 PMAP_LOCK(pm); 2108 key.pvo_vaddr = sva; 2109 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2110 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2111 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2112 moea64_pvo_remove(mmu, pvo); 2113 } 2114 UNLOCK_TABLE_WR(); 2115 PMAP_UNLOCK(pm); 2116} 2117 2118/* 2119 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2120 * will reflect changes in pte's back to the vm_page. 2121 */ 2122void 2123moea64_remove_all(mmu_t mmu, vm_page_t m) 2124{ 2125 struct pvo_entry *pvo, *next_pvo; 2126 pmap_t pmap; 2127 2128 LOCK_TABLE_WR(); 2129 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2130 pmap = pvo->pvo_pmap; 2131 PMAP_LOCK(pmap); 2132 moea64_pvo_remove(mmu, pvo); 2133 PMAP_UNLOCK(pmap); 2134 } 2135 UNLOCK_TABLE_WR(); 2136 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m)) 2137 vm_page_dirty(m); 2138 vm_page_aflag_clear(m, PGA_WRITEABLE); 2139 vm_page_aflag_clear(m, PGA_EXECUTABLE); 2140} 2141 2142/* 2143 * Allocate a physical page of memory directly from the phys_avail map. 2144 * Can only be called from moea64_bootstrap before avail start and end are 2145 * calculated. 2146 */ 2147vm_offset_t 2148moea64_bootstrap_alloc(vm_size_t size, u_int align) 2149{ 2150 vm_offset_t s, e; 2151 int i, j; 2152 2153 size = round_page(size); 2154 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2155 if (align != 0) 2156 s = (phys_avail[i] + align - 1) & ~(align - 1); 2157 else 2158 s = phys_avail[i]; 2159 e = s + size; 2160 2161 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2162 continue; 2163 2164 if (s + size > platform_real_maxaddr()) 2165 continue; 2166 2167 if (s == phys_avail[i]) { 2168 phys_avail[i] += size; 2169 } else if (e == phys_avail[i + 1]) { 2170 phys_avail[i + 1] -= size; 2171 } else { 2172 for (j = phys_avail_count * 2; j > i; j -= 2) { 2173 phys_avail[j] = phys_avail[j - 2]; 2174 phys_avail[j + 1] = phys_avail[j - 1]; 2175 } 2176 2177 phys_avail[i + 3] = phys_avail[i + 1]; 2178 phys_avail[i + 1] = s; 2179 phys_avail[i + 2] = e; 2180 phys_avail_count++; 2181 } 2182 2183 return (s); 2184 } 2185 panic("moea64_bootstrap_alloc: could not allocate memory"); 2186} 2187 2188static int 2189moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2190 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2191 uint64_t pte_lo, int flags, int8_t psind __unused) 2192{ 2193 struct pvo_entry *pvo; 2194 uintptr_t pt; 2195 uint64_t vsid; 2196 int first; 2197 u_int ptegidx; 2198 int i; 2199 int bootstrap; 2200 2201 /* 2202 * One nasty thing that can happen here is that the UMA calls to 2203 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2204 * which calls UMA... 2205 * 2206 * We break the loop by detecting recursion and allocating out of 2207 * the bootstrap pool. 2208 */ 2209 2210 first = 0; 2211 bootstrap = (flags & PVO_BOOTSTRAP); 2212 2213 if (!moea64_initialized) 2214 bootstrap = 1; 2215 2216 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2217 rw_assert(&moea64_table_lock, RA_WLOCKED); 2218 2219 /* 2220 * Compute the PTE Group index. 2221 */ 2222 va &= ~ADDR_POFF; 2223 vsid = va_to_vsid(pm, va); 2224 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2225 2226 /* 2227 * Remove any existing mapping for this page. Reuse the pvo entry if 2228 * there is a mapping. 2229 */ 2230 moea64_pvo_enter_calls++; 2231 2232 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2233 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2234 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2235 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2236 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2237 /* 2238 * The physical page and protection are not 2239 * changing. Instead, this may be a request 2240 * to change the mapping's wired attribute. 2241 */ 2242 pt = -1; 2243 if ((flags & PVO_WIRED) != 0 && 2244 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2245 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2246 pvo->pvo_vaddr |= PVO_WIRED; 2247 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2248 pm->pm_stats.wired_count++; 2249 } else if ((flags & PVO_WIRED) == 0 && 2250 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2251 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2252 pvo->pvo_vaddr &= ~PVO_WIRED; 2253 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 2254 pm->pm_stats.wired_count--; 2255 } 2256 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2257 KASSERT(pt == -1, 2258 ("moea64_pvo_enter: valid pt")); 2259 /* Re-insert if spilled */ 2260 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2261 &pvo->pvo_pte.lpte); 2262 if (i >= 0) 2263 PVO_PTEGIDX_SET(pvo, i); 2264 moea64_pte_overflow--; 2265 } else if (pt != -1) { 2266 /* 2267 * The PTE's wired attribute is not a 2268 * hardware feature, so there is no 2269 * need to invalidate any TLB entries. 2270 */ 2271 MOEA64_PTE_CHANGE(mmu, pt, 2272 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2273 } 2274 return (0); 2275 } 2276 moea64_pvo_remove(mmu, pvo); 2277 break; 2278 } 2279 } 2280 2281 /* 2282 * If we aren't overwriting a mapping, try to allocate. 2283 */ 2284 if (bootstrap) { 2285 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2286 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2287 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2288 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2289 } 2290 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2291 moea64_bpvo_pool_index++; 2292 bootstrap = 1; 2293 } else { 2294 pvo = uma_zalloc(zone, M_NOWAIT); 2295 } 2296 2297 if (pvo == NULL) 2298 return (ENOMEM); 2299 2300 moea64_pvo_entries++; 2301 pvo->pvo_vaddr = va; 2302 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2303 | (vsid << 16); 2304 pvo->pvo_pmap = pm; 2305 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2306 pvo->pvo_vaddr &= ~ADDR_POFF; 2307 2308 if (flags & PVO_WIRED) 2309 pvo->pvo_vaddr |= PVO_WIRED; 2310 if (pvo_head != NULL) 2311 pvo->pvo_vaddr |= PVO_MANAGED; 2312 if (bootstrap) 2313 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2314 if (flags & PVO_LARGE) 2315 pvo->pvo_vaddr |= PVO_LARGE; 2316 2317 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2318 (uint64_t)(pa) | pte_lo, flags); 2319 2320 /* 2321 * Add to pmap list 2322 */ 2323 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2324 2325 /* 2326 * Remember if the list was empty and therefore will be the first 2327 * item. 2328 */ 2329 if (pvo_head != NULL) { 2330 if (LIST_FIRST(pvo_head) == NULL) 2331 first = 1; 2332 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2333 } 2334 2335 if (pvo->pvo_vaddr & PVO_WIRED) { 2336 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2337 pm->pm_stats.wired_count++; 2338 } 2339 pm->pm_stats.resident_count++; 2340 2341 /* 2342 * We hope this succeeds but it isn't required. 2343 */ 2344 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2345 if (i >= 0) { 2346 PVO_PTEGIDX_SET(pvo, i); 2347 } else { 2348 panic("moea64_pvo_enter: overflow"); 2349 moea64_pte_overflow++; 2350 } 2351 2352 if (pm == kernel_pmap) 2353 isync(); 2354 2355#ifdef __powerpc64__ 2356 /* 2357 * Make sure all our bootstrap mappings are in the SLB as soon 2358 * as virtual memory is switched on. 2359 */ 2360 if (!pmap_bootstrapped) 2361 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2362#endif 2363 2364 return (first ? ENOENT : 0); 2365} 2366 2367static void 2368moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2369{ 2370 struct vm_page *pg; 2371 uintptr_t pt; 2372 2373 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2374 rw_assert(&moea64_table_lock, RA_WLOCKED); 2375 2376 /* 2377 * If there is an active pte entry, we need to deactivate it (and 2378 * save the ref & cfg bits). 2379 */ 2380 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2381 if (pt != -1) { 2382 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2383 PVO_PTEGIDX_CLR(pvo); 2384 } else { 2385 moea64_pte_overflow--; 2386 } 2387 2388 /* 2389 * Update our statistics. 2390 */ 2391 pvo->pvo_pmap->pm_stats.resident_count--; 2392 if (pvo->pvo_vaddr & PVO_WIRED) 2393 pvo->pvo_pmap->pm_stats.wired_count--; 2394 2395 /* 2396 * Remove this PVO from the pmap list. 2397 */ 2398 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2399 2400 /* 2401 * Remove this from the overflow list and return it to the pool 2402 * if we aren't going to reuse it. 2403 */ 2404 LIST_REMOVE(pvo, pvo_olink); 2405 2406 /* 2407 * Update vm about the REF/CHG bits if the page is managed. 2408 */ 2409 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2410 2411 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) { 2412 LIST_REMOVE(pvo, pvo_vlink); 2413 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 2414 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 2415 vm_page_dirty(pg); 2416 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 2417 vm_page_aflag_set(pg, PGA_REFERENCED); 2418 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2419 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2420 } 2421 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2422 vm_page_aflag_clear(pg, PGA_EXECUTABLE); 2423 } 2424 2425 moea64_pvo_entries--; 2426 moea64_pvo_remove_calls++; 2427 2428 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2429 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2430 moea64_upvo_zone, pvo); 2431} 2432 2433static struct pvo_entry * 2434moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2435{ 2436 struct pvo_entry key; 2437 2438 key.pvo_vaddr = va & ~ADDR_POFF; 2439 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2440} 2441 2442static boolean_t 2443moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2444{ 2445 struct pvo_entry *pvo; 2446 uintptr_t pt; 2447 2448 LOCK_TABLE_RD(); 2449 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2450 /* 2451 * See if we saved the bit off. If so, return success. 2452 */ 2453 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2454 UNLOCK_TABLE_RD(); 2455 return (TRUE); 2456 } 2457 } 2458 2459 /* 2460 * No luck, now go through the hard part of looking at the PTEs 2461 * themselves. Sync so that any pending REF/CHG bits are flushed to 2462 * the PTEs. 2463 */ 2464 powerpc_sync(); 2465 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2466 2467 /* 2468 * See if this pvo has a valid PTE. if so, fetch the 2469 * REF/CHG bits from the valid PTE. If the appropriate 2470 * ptebit is set, return success. 2471 */ 2472 PMAP_LOCK(pvo->pvo_pmap); 2473 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2474 if (pt != -1) { 2475 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2476 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2477 PMAP_UNLOCK(pvo->pvo_pmap); 2478 UNLOCK_TABLE_RD(); 2479 return (TRUE); 2480 } 2481 } 2482 PMAP_UNLOCK(pvo->pvo_pmap); 2483 } 2484 2485 UNLOCK_TABLE_RD(); 2486 return (FALSE); 2487} 2488 2489static u_int 2490moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2491{ 2492 u_int count; 2493 struct pvo_entry *pvo; 2494 uintptr_t pt; 2495 2496 /* 2497 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2498 * we can reset the right ones). note that since the pvo entries and 2499 * list heads are accessed via BAT0 and are never placed in the page 2500 * table, we don't have to worry about further accesses setting the 2501 * REF/CHG bits. 2502 */ 2503 powerpc_sync(); 2504 2505 /* 2506 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2507 * valid pte clear the ptebit from the valid pte. 2508 */ 2509 count = 0; 2510 LOCK_TABLE_RD(); 2511 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2512 PMAP_LOCK(pvo->pvo_pmap); 2513 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2514 if (pt != -1) { 2515 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2516 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2517 count++; 2518 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2519 pvo->pvo_vpn, ptebit); 2520 } 2521 } 2522 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2523 PMAP_UNLOCK(pvo->pvo_pmap); 2524 } 2525 2526 UNLOCK_TABLE_RD(); 2527 return (count); 2528} 2529 2530boolean_t 2531moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2532{ 2533 struct pvo_entry *pvo, key; 2534 vm_offset_t ppa; 2535 int error = 0; 2536 2537 PMAP_LOCK(kernel_pmap); 2538 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2539 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2540 ppa < pa + size; ppa += PAGE_SIZE, 2541 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2542 if (pvo == NULL || 2543 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2544 error = EFAULT; 2545 break; 2546 } 2547 } 2548 PMAP_UNLOCK(kernel_pmap); 2549 2550 return (error); 2551} 2552 2553/* 2554 * Map a set of physical memory pages into the kernel virtual 2555 * address space. Return a pointer to where it is mapped. This 2556 * routine is intended to be used for mapping device memory, 2557 * NOT real memory. 2558 */ 2559void * 2560moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2561{ 2562 vm_offset_t va, tmpva, ppa, offset; 2563 2564 ppa = trunc_page(pa); 2565 offset = pa & PAGE_MASK; 2566 size = roundup2(offset + size, PAGE_SIZE); 2567 2568 va = kva_alloc(size); 2569 2570 if (!va) 2571 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2572 2573 for (tmpva = va; size > 0;) { 2574 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2575 size -= PAGE_SIZE; 2576 tmpva += PAGE_SIZE; 2577 ppa += PAGE_SIZE; 2578 } 2579 2580 return ((void *)(va + offset)); 2581} 2582 2583void * 2584moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2585{ 2586 2587 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2588} 2589 2590void 2591moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2592{ 2593 vm_offset_t base, offset; 2594 2595 base = trunc_page(va); 2596 offset = va & PAGE_MASK; 2597 size = roundup2(offset + size, PAGE_SIZE); 2598 2599 kva_free(base, size); 2600} 2601 2602void 2603moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2604{ 2605 struct pvo_entry *pvo; 2606 vm_offset_t lim; 2607 vm_paddr_t pa; 2608 vm_size_t len; 2609 2610 PMAP_LOCK(pm); 2611 while (sz > 0) { 2612 lim = round_page(va); 2613 len = MIN(lim - va, sz); 2614 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2615 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) { 2616 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 2617 (va & ADDR_POFF); 2618 moea64_syncicache(mmu, pm, va, pa, len); 2619 } 2620 va += len; 2621 sz -= len; 2622 } 2623 PMAP_UNLOCK(pm); 2624} 2625 2626void 2627moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2628{ 2629 2630 *va = (void *)pa; 2631} 2632 2633extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2634 2635void 2636moea64_scan_init(mmu_t mmu) 2637{ 2638 struct pvo_entry *pvo; 2639 vm_offset_t va; 2640 int i; 2641 2642 if (!do_minidump) { 2643 /* Initialize phys. segments for dumpsys(). */ 2644 memset(&dump_map, 0, sizeof(dump_map)); 2645 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2646 for (i = 0; i < pregions_sz; i++) { 2647 dump_map[i].pa_start = pregions[i].mr_start; 2648 dump_map[i].pa_size = pregions[i].mr_size; 2649 } 2650 return; 2651 } 2652 2653 /* Virtual segments for minidumps: */ 2654 memset(&dump_map, 0, sizeof(dump_map)); 2655 2656 /* 1st: kernel .data and .bss. */ 2657 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2658 dump_map[0].pa_size = round_page((uintptr_t)_end) - dump_map[0].pa_start; 2659 2660 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2661 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2662 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2663 2664 /* 3rd: kernel VM. */ 2665 va = dump_map[1].pa_start + dump_map[1].pa_size; 2666 /* Find start of next chunk (from va). */ 2667 while (va < virtual_end) { 2668 /* Don't dump the buffer cache. */ 2669 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2670 va = kmi.buffer_eva; 2671 continue; 2672 } 2673 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2674 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) 2675 break; 2676 va += PAGE_SIZE; 2677 } 2678 if (va < virtual_end) { 2679 dump_map[2].pa_start = va; 2680 va += PAGE_SIZE; 2681 /* Find last page in chunk. */ 2682 while (va < virtual_end) { 2683 /* Don't run into the buffer cache. */ 2684 if (va == kmi.buffer_sva) 2685 break; 2686 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2687 if (pvo == NULL || 2688 !(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) 2689 break; 2690 va += PAGE_SIZE; 2691 } 2692 dump_map[2].pa_size = va - dump_map[2].pa_start; 2693 } 2694} 2695