mmu_oea64.c revision 276515
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29/*- 30 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 31 * Copyright (C) 1995, 1996 TooLs GmbH. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by TooLs GmbH. 45 * 4. The name of TooLs GmbH may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 60 */ 61/*- 62 * Copyright (C) 2001 Benno Rice. 63 * All rights reserved. 64 * 65 * Redistribution and use in source and binary forms, with or without 66 * modification, are permitted provided that the following conditions 67 * are met: 68 * 1. Redistributions of source code must retain the above copyright 69 * notice, this list of conditions and the following disclaimer. 70 * 2. Redistributions in binary form must reproduce the above copyright 71 * notice, this list of conditions and the following disclaimer in the 72 * documentation and/or other materials provided with the distribution. 73 * 74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 84 */ 85 86#include <sys/cdefs.h> 87__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea64.c 276515 2015-01-01 22:26:12Z nwhitehorn $"); 88 89/* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is also stored by the 93 * logical address mapping module, this module may throw away valid virtual 94 * to physical mappings at almost any time. However, invalidations of 95 * mappings must be done as requested. 96 * 97 * In order to cope with hardware architectures which make virtual to 98 * physical map invalidates expensive, this module may delay invalidate 99 * reduced protection operations until such time as they are actually 100 * necessary. This module is given full information as to which processors 101 * are currently using which maps, and to when physical maps must be made 102 * correct. 103 */ 104 105#include "opt_compat.h" 106#include "opt_kstack_pages.h" 107 108#include <sys/param.h> 109#include <sys/kernel.h> 110#include <sys/queue.h> 111#include <sys/cpuset.h> 112#include <sys/ktr.h> 113#include <sys/lock.h> 114#include <sys/msgbuf.h> 115#include <sys/malloc.h> 116#include <sys/mutex.h> 117#include <sys/proc.h> 118#include <sys/rwlock.h> 119#include <sys/sched.h> 120#include <sys/sysctl.h> 121#include <sys/systm.h> 122#include <sys/vmmeter.h> 123 124#include <sys/kdb.h> 125 126#include <dev/ofw/openfirm.h> 127 128#include <vm/vm.h> 129#include <vm/vm_param.h> 130#include <vm/vm_kern.h> 131#include <vm/vm_page.h> 132#include <vm/vm_map.h> 133#include <vm/vm_object.h> 134#include <vm/vm_extern.h> 135#include <vm/vm_pageout.h> 136#include <vm/uma.h> 137 138#include <machine/_inttypes.h> 139#include <machine/cpu.h> 140#include <machine/platform.h> 141#include <machine/frame.h> 142#include <machine/md_var.h> 143#include <machine/psl.h> 144#include <machine/bat.h> 145#include <machine/hid.h> 146#include <machine/pte.h> 147#include <machine/sr.h> 148#include <machine/trap.h> 149#include <machine/mmuvar.h> 150 151#include "mmu_oea64.h" 152#include "mmu_if.h" 153#include "moea64_if.h" 154 155void moea64_release_vsid(uint64_t vsid); 156uintptr_t moea64_get_unique_vsid(void); 157 158#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 159#define ENABLE_TRANS(msr) mtmsr(msr) 160 161#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 162#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 163#define VSID_HASH_MASK 0x0000007fffffffffULL 164 165/* 166 * Locking semantics: 167 * -- Read lock: if no modifications are being made to either the PVO lists 168 * or page table or if any modifications being made result in internal 169 * changes (e.g. wiring, protection) such that the existence of the PVOs 170 * is unchanged and they remain associated with the same pmap (in which 171 * case the changes should be protected by the pmap lock) 172 * -- Write lock: required if PTEs/PVOs are being inserted or removed. 173 */ 174 175#define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock) 176#define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock) 177#define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock) 178#define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock) 179 180struct ofw_map { 181 cell_t om_va; 182 cell_t om_len; 183 uint64_t om_pa; 184 cell_t om_mode; 185}; 186 187extern unsigned char _etext[]; 188extern unsigned char _end[]; 189 190extern int dumpsys_minidump; 191extern int ofw_real_mode; 192 193/* 194 * Map of physical memory regions. 195 */ 196static struct mem_region *regions; 197static struct mem_region *pregions; 198static u_int phys_avail_count; 199static int regions_sz, pregions_sz; 200 201extern void bs_remap_earlyboot(void); 202 203/* 204 * Lock for the pteg and pvo tables. 205 */ 206struct rwlock moea64_table_lock; 207struct mtx moea64_slb_mutex; 208 209/* 210 * PTEG data. 211 */ 212u_int moea64_pteg_count; 213u_int moea64_pteg_mask; 214 215/* 216 * PVO data. 217 */ 218struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 219 220uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 221uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 222 223#define BPVO_POOL_SIZE 327680 224static struct pvo_entry *moea64_bpvo_pool; 225static int moea64_bpvo_pool_index = 0; 226 227#define VSID_NBPW (sizeof(u_int32_t) * 8) 228#ifdef __powerpc64__ 229#define NVSIDS (NPMAPS * 16) 230#define VSID_HASHMASK 0xffffffffUL 231#else 232#define NVSIDS NPMAPS 233#define VSID_HASHMASK 0xfffffUL 234#endif 235static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 236 237static boolean_t moea64_initialized = FALSE; 238 239/* 240 * Statistics. 241 */ 242u_int moea64_pte_valid = 0; 243u_int moea64_pte_overflow = 0; 244u_int moea64_pvo_entries = 0; 245u_int moea64_pvo_enter_calls = 0; 246u_int moea64_pvo_remove_calls = 0; 247SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 248 &moea64_pte_valid, 0, ""); 249SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 250 &moea64_pte_overflow, 0, ""); 251SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 252 &moea64_pvo_entries, 0, ""); 253SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 254 &moea64_pvo_enter_calls, 0, ""); 255SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 256 &moea64_pvo_remove_calls, 0, ""); 257 258vm_offset_t moea64_scratchpage_va[2]; 259struct pvo_entry *moea64_scratchpage_pvo[2]; 260uintptr_t moea64_scratchpage_pte[2]; 261struct mtx moea64_scratchpage_mtx; 262 263uint64_t moea64_large_page_mask = 0; 264uint64_t moea64_large_page_size = 0; 265int moea64_large_page_shift = 0; 266 267/* 268 * PVO calls. 269 */ 270static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 271 vm_offset_t, vm_offset_t, uint64_t, int, int8_t); 272static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 273static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 274 275/* 276 * Utility routines. 277 */ 278static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 279static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 280static void moea64_kremove(mmu_t, vm_offset_t); 281static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 282 vm_offset_t pa, vm_size_t sz); 283 284/* 285 * Kernel MMU interface 286 */ 287void moea64_clear_modify(mmu_t, vm_page_t); 288void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 289void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 290 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 291int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 292 u_int flags, int8_t psind); 293void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 294 vm_prot_t); 295void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 296vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 297vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 298void moea64_init(mmu_t); 299boolean_t moea64_is_modified(mmu_t, vm_page_t); 300boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 301boolean_t moea64_is_referenced(mmu_t, vm_page_t); 302int moea64_ts_referenced(mmu_t, vm_page_t); 303vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 304boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 305int moea64_page_wired_mappings(mmu_t, vm_page_t); 306void moea64_pinit(mmu_t, pmap_t); 307void moea64_pinit0(mmu_t, pmap_t); 308void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 309void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 310void moea64_qremove(mmu_t, vm_offset_t, int); 311void moea64_release(mmu_t, pmap_t); 312void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 313void moea64_remove_pages(mmu_t, pmap_t); 314void moea64_remove_all(mmu_t, vm_page_t); 315void moea64_remove_write(mmu_t, vm_page_t); 316void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 317void moea64_zero_page(mmu_t, vm_page_t); 318void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 319void moea64_zero_page_idle(mmu_t, vm_page_t); 320void moea64_activate(mmu_t, struct thread *); 321void moea64_deactivate(mmu_t, struct thread *); 322void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 323void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 324void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 325vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 326void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 327void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 328void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 329boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 330static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 331vm_offset_t moea64_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 332 vm_size_t *sz); 333struct pmap_md * moea64_scan_md(mmu_t mmu, struct pmap_md *prev); 334 335static mmu_method_t moea64_methods[] = { 336 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 337 MMUMETHOD(mmu_copy_page, moea64_copy_page), 338 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 339 MMUMETHOD(mmu_enter, moea64_enter), 340 MMUMETHOD(mmu_enter_object, moea64_enter_object), 341 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 342 MMUMETHOD(mmu_extract, moea64_extract), 343 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 344 MMUMETHOD(mmu_init, moea64_init), 345 MMUMETHOD(mmu_is_modified, moea64_is_modified), 346 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 347 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 348 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 349 MMUMETHOD(mmu_map, moea64_map), 350 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 351 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 352 MMUMETHOD(mmu_pinit, moea64_pinit), 353 MMUMETHOD(mmu_pinit0, moea64_pinit0), 354 MMUMETHOD(mmu_protect, moea64_protect), 355 MMUMETHOD(mmu_qenter, moea64_qenter), 356 MMUMETHOD(mmu_qremove, moea64_qremove), 357 MMUMETHOD(mmu_release, moea64_release), 358 MMUMETHOD(mmu_remove, moea64_remove), 359 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 360 MMUMETHOD(mmu_remove_all, moea64_remove_all), 361 MMUMETHOD(mmu_remove_write, moea64_remove_write), 362 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 363 MMUMETHOD(mmu_unwire, moea64_unwire), 364 MMUMETHOD(mmu_zero_page, moea64_zero_page), 365 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 366 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 367 MMUMETHOD(mmu_activate, moea64_activate), 368 MMUMETHOD(mmu_deactivate, moea64_deactivate), 369 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 370 371 /* Internal interfaces */ 372 MMUMETHOD(mmu_mapdev, moea64_mapdev), 373 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 374 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 375 MMUMETHOD(mmu_kextract, moea64_kextract), 376 MMUMETHOD(mmu_kenter, moea64_kenter), 377 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 378 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 379 MMUMETHOD(mmu_scan_md, moea64_scan_md), 380 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 381 382 { 0, 0 } 383}; 384 385MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 386 387static __inline u_int 388va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 389{ 390 uint64_t hash; 391 int shift; 392 393 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 394 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 395 shift); 396 return (hash & moea64_pteg_mask); 397} 398 399static __inline struct pvo_head * 400vm_page_to_pvoh(vm_page_t m) 401{ 402 403 return (&m->md.mdpg_pvoh); 404} 405 406static __inline void 407moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 408 uint64_t pte_lo, int flags) 409{ 410 411 /* 412 * Construct a PTE. Default to IMB initially. Valid bit only gets 413 * set when the real pte is set in memory. 414 * 415 * Note: Don't set the valid bit for correct operation of tlb update. 416 */ 417 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 418 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 419 420 if (flags & PVO_LARGE) 421 pt->pte_hi |= LPTE_BIG; 422 423 pt->pte_lo = pte_lo; 424} 425 426static __inline uint64_t 427moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 428{ 429 uint64_t pte_lo; 430 int i; 431 432 if (ma != VM_MEMATTR_DEFAULT) { 433 switch (ma) { 434 case VM_MEMATTR_UNCACHEABLE: 435 return (LPTE_I | LPTE_G); 436 case VM_MEMATTR_WRITE_COMBINING: 437 case VM_MEMATTR_WRITE_BACK: 438 case VM_MEMATTR_PREFETCHABLE: 439 return (LPTE_I); 440 case VM_MEMATTR_WRITE_THROUGH: 441 return (LPTE_W | LPTE_M); 442 } 443 } 444 445 /* 446 * Assume the page is cache inhibited and access is guarded unless 447 * it's in our available memory array. 448 */ 449 pte_lo = LPTE_I | LPTE_G; 450 for (i = 0; i < pregions_sz; i++) { 451 if ((pa >= pregions[i].mr_start) && 452 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 453 pte_lo &= ~(LPTE_I | LPTE_G); 454 pte_lo |= LPTE_M; 455 break; 456 } 457 } 458 459 return pte_lo; 460} 461 462/* 463 * Quick sort callout for comparing memory regions. 464 */ 465static int om_cmp(const void *a, const void *b); 466 467static int 468om_cmp(const void *a, const void *b) 469{ 470 const struct ofw_map *mapa; 471 const struct ofw_map *mapb; 472 473 mapa = a; 474 mapb = b; 475 if (mapa->om_pa < mapb->om_pa) 476 return (-1); 477 else if (mapa->om_pa > mapb->om_pa) 478 return (1); 479 else 480 return (0); 481} 482 483static void 484moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 485{ 486 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 487 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 488 register_t msr; 489 vm_offset_t off; 490 vm_paddr_t pa_base; 491 int i, j; 492 493 bzero(translations, sz); 494 OF_getprop(OF_finddevice("/"), "#address-cells", &acells, 495 sizeof(acells)); 496 if (OF_getprop(mmu, "translations", trans_cells, sz) == -1) 497 panic("moea64_bootstrap: can't get ofw translations"); 498 499 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 500 sz /= sizeof(cell_t); 501 for (i = 0, j = 0; i < sz; j++) { 502 translations[j].om_va = trans_cells[i++]; 503 translations[j].om_len = trans_cells[i++]; 504 translations[j].om_pa = trans_cells[i++]; 505 if (acells == 2) { 506 translations[j].om_pa <<= 32; 507 translations[j].om_pa |= trans_cells[i++]; 508 } 509 translations[j].om_mode = trans_cells[i++]; 510 } 511 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 512 i, sz)); 513 514 sz = j; 515 qsort(translations, sz, sizeof (*translations), om_cmp); 516 517 for (i = 0; i < sz; i++) { 518 pa_base = translations[i].om_pa; 519 #ifndef __powerpc64__ 520 if ((translations[i].om_pa >> 32) != 0) 521 panic("OFW translations above 32-bit boundary!"); 522 #endif 523 524 if (pa_base % PAGE_SIZE) 525 panic("OFW translation not page-aligned (phys)!"); 526 if (translations[i].om_va % PAGE_SIZE) 527 panic("OFW translation not page-aligned (virt)!"); 528 529 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 530 pa_base, translations[i].om_va, translations[i].om_len); 531 532 /* Now enter the pages for this mapping */ 533 534 DISABLE_TRANS(msr); 535 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 536 if (moea64_pvo_find_va(kernel_pmap, 537 translations[i].om_va + off) != NULL) 538 continue; 539 540 moea64_kenter(mmup, translations[i].om_va + off, 541 pa_base + off); 542 } 543 ENABLE_TRANS(msr); 544 } 545} 546 547#ifdef __powerpc64__ 548static void 549moea64_probe_large_page(void) 550{ 551 uint16_t pvr = mfpvr() >> 16; 552 553 switch (pvr) { 554 case IBM970: 555 case IBM970FX: 556 case IBM970MP: 557 powerpc_sync(); isync(); 558 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 559 powerpc_sync(); isync(); 560 561 /* FALLTHROUGH */ 562 default: 563 moea64_large_page_size = 0x1000000; /* 16 MB */ 564 moea64_large_page_shift = 24; 565 } 566 567 moea64_large_page_mask = moea64_large_page_size - 1; 568} 569 570static void 571moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 572{ 573 struct slb *cache; 574 struct slb entry; 575 uint64_t esid, slbe; 576 uint64_t i; 577 578 cache = PCPU_GET(slb); 579 esid = va >> ADDR_SR_SHFT; 580 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 581 582 for (i = 0; i < 64; i++) { 583 if (cache[i].slbe == (slbe | i)) 584 return; 585 } 586 587 entry.slbe = slbe; 588 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 589 if (large) 590 entry.slbv |= SLBV_L; 591 592 slb_insert_kernel(entry.slbe, entry.slbv); 593} 594#endif 595 596static void 597moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 598 vm_offset_t kernelend) 599{ 600 register_t msr; 601 vm_paddr_t pa; 602 vm_offset_t size, off; 603 uint64_t pte_lo; 604 int i; 605 606 if (moea64_large_page_size == 0) 607 hw_direct_map = 0; 608 609 DISABLE_TRANS(msr); 610 if (hw_direct_map) { 611 LOCK_TABLE_WR(); 612 PMAP_LOCK(kernel_pmap); 613 for (i = 0; i < pregions_sz; i++) { 614 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 615 pregions[i].mr_size; pa += moea64_large_page_size) { 616 pte_lo = LPTE_M; 617 618 /* 619 * Set memory access as guarded if prefetch within 620 * the page could exit the available physmem area. 621 */ 622 if (pa & moea64_large_page_mask) { 623 pa &= moea64_large_page_mask; 624 pte_lo |= LPTE_G; 625 } 626 if (pa + moea64_large_page_size > 627 pregions[i].mr_start + pregions[i].mr_size) 628 pte_lo |= LPTE_G; 629 630 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 631 NULL, pa, pa, pte_lo, 632 PVO_WIRED | PVO_LARGE, 0); 633 } 634 } 635 PMAP_UNLOCK(kernel_pmap); 636 UNLOCK_TABLE_WR(); 637 } else { 638 size = sizeof(struct pvo_head) * moea64_pteg_count; 639 off = (vm_offset_t)(moea64_pvo_table); 640 for (pa = off; pa < off + size; pa += PAGE_SIZE) 641 moea64_kenter(mmup, pa, pa); 642 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 643 off = (vm_offset_t)(moea64_bpvo_pool); 644 for (pa = off; pa < off + size; pa += PAGE_SIZE) 645 moea64_kenter(mmup, pa, pa); 646 647 /* 648 * Map certain important things, like ourselves. 649 * 650 * NOTE: We do not map the exception vector space. That code is 651 * used only in real mode, and leaving it unmapped allows us to 652 * catch NULL pointer deferences, instead of making NULL a valid 653 * address. 654 */ 655 656 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 657 pa += PAGE_SIZE) 658 moea64_kenter(mmup, pa, pa); 659 } 660 ENABLE_TRANS(msr); 661 662 /* 663 * Allow user to override unmapped_buf_allowed for testing. 664 * XXXKIB Only direct map implementation was tested. 665 */ 666 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 667 &unmapped_buf_allowed)) 668 unmapped_buf_allowed = hw_direct_map; 669} 670 671void 672moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 673{ 674 int i, j; 675 vm_size_t physsz, hwphyssz; 676 677#ifndef __powerpc64__ 678 /* We don't have a direct map since there is no BAT */ 679 hw_direct_map = 0; 680 681 /* Make sure battable is zero, since we have no BAT */ 682 for (i = 0; i < 16; i++) { 683 battable[i].batu = 0; 684 battable[i].batl = 0; 685 } 686#else 687 moea64_probe_large_page(); 688 689 /* Use a direct map if we have large page support */ 690 if (moea64_large_page_size > 0) 691 hw_direct_map = 1; 692 else 693 hw_direct_map = 0; 694#endif 695 696 /* Get physical memory regions from firmware */ 697 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 698 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 699 700 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 701 panic("moea64_bootstrap: phys_avail too small"); 702 703 phys_avail_count = 0; 704 physsz = 0; 705 hwphyssz = 0; 706 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 707 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 708 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 709 regions[i].mr_start, regions[i].mr_start + 710 regions[i].mr_size, regions[i].mr_size); 711 if (hwphyssz != 0 && 712 (physsz + regions[i].mr_size) >= hwphyssz) { 713 if (physsz < hwphyssz) { 714 phys_avail[j] = regions[i].mr_start; 715 phys_avail[j + 1] = regions[i].mr_start + 716 hwphyssz - physsz; 717 physsz = hwphyssz; 718 phys_avail_count++; 719 } 720 break; 721 } 722 phys_avail[j] = regions[i].mr_start; 723 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 724 phys_avail_count++; 725 physsz += regions[i].mr_size; 726 } 727 728 /* Check for overlap with the kernel and exception vectors */ 729 for (j = 0; j < 2*phys_avail_count; j+=2) { 730 if (phys_avail[j] < EXC_LAST) 731 phys_avail[j] += EXC_LAST; 732 733 if (kernelstart >= phys_avail[j] && 734 kernelstart < phys_avail[j+1]) { 735 if (kernelend < phys_avail[j+1]) { 736 phys_avail[2*phys_avail_count] = 737 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 738 phys_avail[2*phys_avail_count + 1] = 739 phys_avail[j+1]; 740 phys_avail_count++; 741 } 742 743 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 744 } 745 746 if (kernelend >= phys_avail[j] && 747 kernelend < phys_avail[j+1]) { 748 if (kernelstart > phys_avail[j]) { 749 phys_avail[2*phys_avail_count] = phys_avail[j]; 750 phys_avail[2*phys_avail_count + 1] = 751 kernelstart & ~PAGE_MASK; 752 phys_avail_count++; 753 } 754 755 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 756 } 757 } 758 759 physmem = btoc(physsz); 760 761#ifdef PTEGCOUNT 762 moea64_pteg_count = PTEGCOUNT; 763#else 764 moea64_pteg_count = 0x1000; 765 766 while (moea64_pteg_count < physmem) 767 moea64_pteg_count <<= 1; 768 769 moea64_pteg_count >>= 1; 770#endif /* PTEGCOUNT */ 771} 772 773void 774moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 775{ 776 vm_size_t size; 777 register_t msr; 778 int i; 779 780 /* 781 * Set PTEG mask 782 */ 783 moea64_pteg_mask = moea64_pteg_count - 1; 784 785 /* 786 * Allocate pv/overflow lists. 787 */ 788 size = sizeof(struct pvo_head) * moea64_pteg_count; 789 790 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 791 PAGE_SIZE); 792 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 793 794 DISABLE_TRANS(msr); 795 for (i = 0; i < moea64_pteg_count; i++) 796 LIST_INIT(&moea64_pvo_table[i]); 797 ENABLE_TRANS(msr); 798 799 /* 800 * Initialize the lock that synchronizes access to the pteg and pvo 801 * tables. 802 */ 803 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE); 804 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 805 806 /* 807 * Initialise the unmanaged pvo pool. 808 */ 809 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 810 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 811 moea64_bpvo_pool_index = 0; 812 813 /* 814 * Make sure kernel vsid is allocated as well as VSID 0. 815 */ 816 #ifndef __powerpc64__ 817 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 818 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 819 moea64_vsid_bitmap[0] |= 1; 820 #endif 821 822 /* 823 * Initialize the kernel pmap (which is statically allocated). 824 */ 825 #ifdef __powerpc64__ 826 for (i = 0; i < 64; i++) { 827 pcpup->pc_slb[i].slbv = 0; 828 pcpup->pc_slb[i].slbe = 0; 829 } 830 #else 831 for (i = 0; i < 16; i++) 832 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 833 #endif 834 835 kernel_pmap->pmap_phys = kernel_pmap; 836 CPU_FILL(&kernel_pmap->pm_active); 837 RB_INIT(&kernel_pmap->pmap_pvo); 838 839 PMAP_LOCK_INIT(kernel_pmap); 840 841 /* 842 * Now map in all the other buffers we allocated earlier 843 */ 844 845 moea64_setup_direct_map(mmup, kernelstart, kernelend); 846} 847 848void 849moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 850{ 851 ihandle_t mmui; 852 phandle_t chosen; 853 phandle_t mmu; 854 ssize_t sz; 855 int i; 856 vm_offset_t pa, va; 857 void *dpcpu; 858 859 /* 860 * Set up the Open Firmware pmap and add its mappings if not in real 861 * mode. 862 */ 863 864 chosen = OF_finddevice("/chosen"); 865 if (!ofw_real_mode && chosen != -1 && 866 OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 867 mmu = OF_instance_to_package(mmui); 868 if (mmu == -1 || 869 (sz = OF_getproplen(mmu, "translations")) == -1) 870 sz = 0; 871 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 872 panic("moea64_bootstrap: too many ofw translations"); 873 874 if (sz > 0) 875 moea64_add_ofw_mappings(mmup, mmu, sz); 876 } 877 878 /* 879 * Calculate the last available physical address. 880 */ 881 for (i = 0; phys_avail[i + 2] != 0; i += 2) 882 ; 883 Maxmem = powerpc_btop(phys_avail[i + 1]); 884 885 /* 886 * Initialize MMU and remap early physical mappings 887 */ 888 MMU_CPU_BOOTSTRAP(mmup,0); 889 mtmsr(mfmsr() | PSL_DR | PSL_IR); 890 pmap_bootstrapped++; 891 bs_remap_earlyboot(); 892 893 /* 894 * Set the start and end of kva. 895 */ 896 virtual_avail = VM_MIN_KERNEL_ADDRESS; 897 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 898 899 /* 900 * Map the entire KVA range into the SLB. We must not fault there. 901 */ 902 #ifdef __powerpc64__ 903 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 904 moea64_bootstrap_slb_prefault(va, 0); 905 #endif 906 907 /* 908 * Figure out how far we can extend virtual_end into segment 16 909 * without running into existing mappings. Segment 16 is guaranteed 910 * to contain neither RAM nor devices (at least on Apple hardware), 911 * but will generally contain some OFW mappings we should not 912 * step on. 913 */ 914 915 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 916 PMAP_LOCK(kernel_pmap); 917 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 918 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 919 virtual_end += PAGE_SIZE; 920 PMAP_UNLOCK(kernel_pmap); 921 #endif 922 923 /* 924 * Allocate a kernel stack with a guard page for thread0 and map it 925 * into the kernel page map. 926 */ 927 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 928 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 929 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 930 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 931 thread0.td_kstack = va; 932 thread0.td_kstack_pages = KSTACK_PAGES; 933 for (i = 0; i < KSTACK_PAGES; i++) { 934 moea64_kenter(mmup, va, pa); 935 pa += PAGE_SIZE; 936 va += PAGE_SIZE; 937 } 938 939 /* 940 * Allocate virtual address space for the message buffer. 941 */ 942 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 943 msgbufp = (struct msgbuf *)virtual_avail; 944 va = virtual_avail; 945 virtual_avail += round_page(msgbufsize); 946 while (va < virtual_avail) { 947 moea64_kenter(mmup, va, pa); 948 pa += PAGE_SIZE; 949 va += PAGE_SIZE; 950 } 951 952 /* 953 * Allocate virtual address space for the dynamic percpu area. 954 */ 955 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 956 dpcpu = (void *)virtual_avail; 957 va = virtual_avail; 958 virtual_avail += DPCPU_SIZE; 959 while (va < virtual_avail) { 960 moea64_kenter(mmup, va, pa); 961 pa += PAGE_SIZE; 962 va += PAGE_SIZE; 963 } 964 dpcpu_init(dpcpu, 0); 965 966 /* 967 * Allocate some things for page zeroing. We put this directly 968 * in the page table, marked with LPTE_LOCKED, to avoid any 969 * of the PVO book-keeping or other parts of the VM system 970 * from even knowing that this hack exists. 971 */ 972 973 if (!hw_direct_map) { 974 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 975 MTX_DEF); 976 for (i = 0; i < 2; i++) { 977 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 978 virtual_end -= PAGE_SIZE; 979 980 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 981 982 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 983 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 984 LOCK_TABLE_RD(); 985 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 986 mmup, moea64_scratchpage_pvo[i]); 987 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 988 |= LPTE_LOCKED; 989 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 990 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 991 moea64_scratchpage_pvo[i]->pvo_vpn); 992 UNLOCK_TABLE_RD(); 993 } 994 } 995} 996 997/* 998 * Activate a user pmap. The pmap must be activated before its address 999 * space can be accessed in any way. 1000 */ 1001void 1002moea64_activate(mmu_t mmu, struct thread *td) 1003{ 1004 pmap_t pm; 1005 1006 pm = &td->td_proc->p_vmspace->vm_pmap; 1007 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1008 1009 #ifdef __powerpc64__ 1010 PCPU_SET(userslb, pm->pm_slb); 1011 #else 1012 PCPU_SET(curpmap, pm->pmap_phys); 1013 #endif 1014} 1015 1016void 1017moea64_deactivate(mmu_t mmu, struct thread *td) 1018{ 1019 pmap_t pm; 1020 1021 pm = &td->td_proc->p_vmspace->vm_pmap; 1022 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1023 #ifdef __powerpc64__ 1024 PCPU_SET(userslb, NULL); 1025 #else 1026 PCPU_SET(curpmap, NULL); 1027 #endif 1028} 1029 1030void 1031moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1032{ 1033 struct pvo_entry key, *pvo; 1034 uintptr_t pt; 1035 1036 LOCK_TABLE_RD(); 1037 PMAP_LOCK(pm); 1038 key.pvo_vaddr = sva; 1039 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1040 pvo != NULL && PVO_VADDR(pvo) < eva; 1041 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1042 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1043 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1044 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1045 pvo); 1046 pvo->pvo_vaddr &= ~PVO_WIRED; 1047 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_WIRED) == 0) 1048 panic("moea64_unwire: pte %p is missing LPTE_WIRED", 1049 &pvo->pvo_pte.lpte); 1050 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1051 if (pt != -1) { 1052 /* 1053 * The PTE's wired attribute is not a hardware 1054 * feature, so there is no need to invalidate any TLB 1055 * entries. 1056 */ 1057 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1058 pvo->pvo_vpn); 1059 } 1060 pm->pm_stats.wired_count--; 1061 } 1062 UNLOCK_TABLE_RD(); 1063 PMAP_UNLOCK(pm); 1064} 1065 1066/* 1067 * This goes through and sets the physical address of our 1068 * special scratch PTE to the PA we want to zero or copy. Because 1069 * of locking issues (this can get called in pvo_enter() by 1070 * the UMA allocator), we can't use most other utility functions here 1071 */ 1072 1073static __inline 1074void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1075 1076 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1077 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1078 1079 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1080 ~(LPTE_WIMG | LPTE_RPGN); 1081 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1082 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1083 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1084 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1085 moea64_scratchpage_pvo[which]->pvo_vpn); 1086 isync(); 1087} 1088 1089void 1090moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1091{ 1092 vm_offset_t dst; 1093 vm_offset_t src; 1094 1095 dst = VM_PAGE_TO_PHYS(mdst); 1096 src = VM_PAGE_TO_PHYS(msrc); 1097 1098 if (hw_direct_map) { 1099 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1100 } else { 1101 mtx_lock(&moea64_scratchpage_mtx); 1102 1103 moea64_set_scratchpage_pa(mmu, 0, src); 1104 moea64_set_scratchpage_pa(mmu, 1, dst); 1105 1106 bcopy((void *)moea64_scratchpage_va[0], 1107 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1108 1109 mtx_unlock(&moea64_scratchpage_mtx); 1110 } 1111} 1112 1113static inline void 1114moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1115 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1116{ 1117 void *a_cp, *b_cp; 1118 vm_offset_t a_pg_offset, b_pg_offset; 1119 int cnt; 1120 1121 while (xfersize > 0) { 1122 a_pg_offset = a_offset & PAGE_MASK; 1123 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1124 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1125 a_pg_offset; 1126 b_pg_offset = b_offset & PAGE_MASK; 1127 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1128 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1129 b_pg_offset; 1130 bcopy(a_cp, b_cp, cnt); 1131 a_offset += cnt; 1132 b_offset += cnt; 1133 xfersize -= cnt; 1134 } 1135} 1136 1137static inline void 1138moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1139 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1140{ 1141 void *a_cp, *b_cp; 1142 vm_offset_t a_pg_offset, b_pg_offset; 1143 int cnt; 1144 1145 mtx_lock(&moea64_scratchpage_mtx); 1146 while (xfersize > 0) { 1147 a_pg_offset = a_offset & PAGE_MASK; 1148 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1149 moea64_set_scratchpage_pa(mmu, 0, 1150 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1151 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1152 b_pg_offset = b_offset & PAGE_MASK; 1153 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1154 moea64_set_scratchpage_pa(mmu, 1, 1155 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1156 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1157 bcopy(a_cp, b_cp, cnt); 1158 a_offset += cnt; 1159 b_offset += cnt; 1160 xfersize -= cnt; 1161 } 1162 mtx_unlock(&moea64_scratchpage_mtx); 1163} 1164 1165void 1166moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1167 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1168{ 1169 1170 if (hw_direct_map) { 1171 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1172 xfersize); 1173 } else { 1174 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1175 xfersize); 1176 } 1177} 1178 1179void 1180moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1181{ 1182 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1183 1184 if (size + off > PAGE_SIZE) 1185 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1186 1187 if (hw_direct_map) { 1188 bzero((caddr_t)pa + off, size); 1189 } else { 1190 mtx_lock(&moea64_scratchpage_mtx); 1191 moea64_set_scratchpage_pa(mmu, 0, pa); 1192 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1193 mtx_unlock(&moea64_scratchpage_mtx); 1194 } 1195} 1196 1197/* 1198 * Zero a page of physical memory by temporarily mapping it 1199 */ 1200void 1201moea64_zero_page(mmu_t mmu, vm_page_t m) 1202{ 1203 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1204 vm_offset_t va, off; 1205 1206 if (!hw_direct_map) { 1207 mtx_lock(&moea64_scratchpage_mtx); 1208 1209 moea64_set_scratchpage_pa(mmu, 0, pa); 1210 va = moea64_scratchpage_va[0]; 1211 } else { 1212 va = pa; 1213 } 1214 1215 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1216 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1217 1218 if (!hw_direct_map) 1219 mtx_unlock(&moea64_scratchpage_mtx); 1220} 1221 1222void 1223moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1224{ 1225 1226 moea64_zero_page(mmu, m); 1227} 1228 1229/* 1230 * Map the given physical page at the specified virtual address in the 1231 * target pmap with the protection requested. If specified the page 1232 * will be wired down. 1233 */ 1234 1235int 1236moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1237 vm_prot_t prot, u_int flags, int8_t psind) 1238{ 1239 struct pvo_head *pvo_head; 1240 uma_zone_t zone; 1241 uint64_t pte_lo; 1242 u_int pvo_flags; 1243 int error; 1244 1245 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1246 VM_OBJECT_ASSERT_LOCKED(m->object); 1247 1248 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1249 pvo_head = NULL; 1250 zone = moea64_upvo_zone; 1251 pvo_flags = 0; 1252 } else { 1253 pvo_head = vm_page_to_pvoh(m); 1254 zone = moea64_mpvo_zone; 1255 pvo_flags = PVO_MANAGED; 1256 } 1257 1258 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1259 1260 if (prot & VM_PROT_WRITE) { 1261 pte_lo |= LPTE_BW; 1262 if (pmap_bootstrapped && 1263 (m->oflags & VPO_UNMANAGED) == 0) 1264 vm_page_aflag_set(m, PGA_WRITEABLE); 1265 } else 1266 pte_lo |= LPTE_BR; 1267 1268 if ((prot & VM_PROT_EXECUTE) == 0) 1269 pte_lo |= LPTE_NOEXEC; 1270 1271 if ((flags & PMAP_ENTER_WIRED) != 0) 1272 pvo_flags |= PVO_WIRED; 1273 1274 for (;;) { 1275 LOCK_TABLE_WR(); 1276 PMAP_LOCK(pmap); 1277 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1278 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags, psind); 1279 PMAP_UNLOCK(pmap); 1280 UNLOCK_TABLE_WR(); 1281 if (error != ENOMEM) 1282 break; 1283 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1284 return (KERN_RESOURCE_SHORTAGE); 1285 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1286 VM_WAIT; 1287 } 1288 1289 /* 1290 * Flush the page from the instruction cache if this page is 1291 * mapped executable and cacheable. 1292 */ 1293 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1294 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1295 vm_page_aflag_set(m, PGA_EXECUTABLE); 1296 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1297 } 1298 return (KERN_SUCCESS); 1299} 1300 1301static void 1302moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1303 vm_size_t sz) 1304{ 1305 1306 /* 1307 * This is much trickier than on older systems because 1308 * we can't sync the icache on physical addresses directly 1309 * without a direct map. Instead we check a couple of cases 1310 * where the memory is already mapped in and, failing that, 1311 * use the same trick we use for page zeroing to create 1312 * a temporary mapping for this physical address. 1313 */ 1314 1315 if (!pmap_bootstrapped) { 1316 /* 1317 * If PMAP is not bootstrapped, we are likely to be 1318 * in real mode. 1319 */ 1320 __syncicache((void *)pa, sz); 1321 } else if (pmap == kernel_pmap) { 1322 __syncicache((void *)va, sz); 1323 } else if (hw_direct_map) { 1324 __syncicache((void *)pa, sz); 1325 } else { 1326 /* Use the scratch page to set up a temp mapping */ 1327 1328 mtx_lock(&moea64_scratchpage_mtx); 1329 1330 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1331 __syncicache((void *)(moea64_scratchpage_va[1] + 1332 (va & ADDR_POFF)), sz); 1333 1334 mtx_unlock(&moea64_scratchpage_mtx); 1335 } 1336} 1337 1338/* 1339 * Maps a sequence of resident pages belonging to the same object. 1340 * The sequence begins with the given page m_start. This page is 1341 * mapped at the given virtual address start. Each subsequent page is 1342 * mapped at a virtual address that is offset from start by the same 1343 * amount as the page is offset from m_start within the object. The 1344 * last page in the sequence is the page with the largest offset from 1345 * m_start that can be mapped at a virtual address less than the given 1346 * virtual address end. Not every virtual page between start and end 1347 * is mapped; only those for which a resident page exists with the 1348 * corresponding offset from m_start are mapped. 1349 */ 1350void 1351moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1352 vm_page_t m_start, vm_prot_t prot) 1353{ 1354 vm_page_t m; 1355 vm_pindex_t diff, psize; 1356 1357 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1358 1359 psize = atop(end - start); 1360 m = m_start; 1361 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1362 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1363 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1364 m = TAILQ_NEXT(m, listq); 1365 } 1366} 1367 1368void 1369moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1370 vm_prot_t prot) 1371{ 1372 1373 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1374 PMAP_ENTER_NOSLEEP, 0); 1375} 1376 1377vm_paddr_t 1378moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1379{ 1380 struct pvo_entry *pvo; 1381 vm_paddr_t pa; 1382 1383 PMAP_LOCK(pm); 1384 pvo = moea64_pvo_find_va(pm, va); 1385 if (pvo == NULL) 1386 pa = 0; 1387 else 1388 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1389 (va - PVO_VADDR(pvo)); 1390 PMAP_UNLOCK(pm); 1391 return (pa); 1392} 1393 1394/* 1395 * Atomically extract and hold the physical page with the given 1396 * pmap and virtual address pair if that mapping permits the given 1397 * protection. 1398 */ 1399vm_page_t 1400moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1401{ 1402 struct pvo_entry *pvo; 1403 vm_page_t m; 1404 vm_paddr_t pa; 1405 1406 m = NULL; 1407 pa = 0; 1408 PMAP_LOCK(pmap); 1409retry: 1410 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1411 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1412 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1413 (prot & VM_PROT_WRITE) == 0)) { 1414 if (vm_page_pa_tryrelock(pmap, 1415 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1416 goto retry; 1417 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1418 vm_page_hold(m); 1419 } 1420 PA_UNLOCK_COND(pa); 1421 PMAP_UNLOCK(pmap); 1422 return (m); 1423} 1424 1425static mmu_t installed_mmu; 1426 1427static void * 1428moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1429{ 1430 /* 1431 * This entire routine is a horrible hack to avoid bothering kmem 1432 * for new KVA addresses. Because this can get called from inside 1433 * kmem allocation routines, calling kmem for a new address here 1434 * can lead to multiply locking non-recursive mutexes. 1435 */ 1436 vm_offset_t va; 1437 1438 vm_page_t m; 1439 int pflags, needed_lock; 1440 1441 *flags = UMA_SLAB_PRIV; 1442 needed_lock = !PMAP_LOCKED(kernel_pmap); 1443 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED; 1444 1445 for (;;) { 1446 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1447 if (m == NULL) { 1448 if (wait & M_NOWAIT) 1449 return (NULL); 1450 VM_WAIT; 1451 } else 1452 break; 1453 } 1454 1455 va = VM_PAGE_TO_PHYS(m); 1456 1457 LOCK_TABLE_WR(); 1458 if (needed_lock) 1459 PMAP_LOCK(kernel_pmap); 1460 1461 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1462 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP, 1463 0); 1464 1465 if (needed_lock) 1466 PMAP_UNLOCK(kernel_pmap); 1467 UNLOCK_TABLE_WR(); 1468 1469 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1470 bzero((void *)va, PAGE_SIZE); 1471 1472 return (void *)va; 1473} 1474 1475extern int elf32_nxstack; 1476 1477void 1478moea64_init(mmu_t mmu) 1479{ 1480 1481 CTR0(KTR_PMAP, "moea64_init"); 1482 1483 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1484 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1485 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1486 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1487 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1488 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1489 1490 if (!hw_direct_map) { 1491 installed_mmu = mmu; 1492 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1493 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1494 } 1495 1496#ifdef COMPAT_FREEBSD32 1497 elf32_nxstack = 1; 1498#endif 1499 1500 moea64_initialized = TRUE; 1501} 1502 1503boolean_t 1504moea64_is_referenced(mmu_t mmu, vm_page_t m) 1505{ 1506 1507 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1508 ("moea64_is_referenced: page %p is not managed", m)); 1509 return (moea64_query_bit(mmu, m, PTE_REF)); 1510} 1511 1512boolean_t 1513moea64_is_modified(mmu_t mmu, vm_page_t m) 1514{ 1515 1516 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1517 ("moea64_is_modified: page %p is not managed", m)); 1518 1519 /* 1520 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1521 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1522 * is clear, no PTEs can have LPTE_CHG set. 1523 */ 1524 VM_OBJECT_ASSERT_LOCKED(m->object); 1525 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1526 return (FALSE); 1527 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1528} 1529 1530boolean_t 1531moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1532{ 1533 struct pvo_entry *pvo; 1534 boolean_t rv; 1535 1536 PMAP_LOCK(pmap); 1537 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1538 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1539 PMAP_UNLOCK(pmap); 1540 return (rv); 1541} 1542 1543void 1544moea64_clear_modify(mmu_t mmu, vm_page_t m) 1545{ 1546 1547 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1548 ("moea64_clear_modify: page %p is not managed", m)); 1549 VM_OBJECT_ASSERT_WLOCKED(m->object); 1550 KASSERT(!vm_page_xbusied(m), 1551 ("moea64_clear_modify: page %p is exclusive busied", m)); 1552 1553 /* 1554 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1555 * set. If the object containing the page is locked and the page is 1556 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1557 */ 1558 if ((m->aflags & PGA_WRITEABLE) == 0) 1559 return; 1560 moea64_clear_bit(mmu, m, LPTE_CHG); 1561} 1562 1563/* 1564 * Clear the write and modified bits in each of the given page's mappings. 1565 */ 1566void 1567moea64_remove_write(mmu_t mmu, vm_page_t m) 1568{ 1569 struct pvo_entry *pvo; 1570 uintptr_t pt; 1571 pmap_t pmap; 1572 uint64_t lo = 0; 1573 1574 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1575 ("moea64_remove_write: page %p is not managed", m)); 1576 1577 /* 1578 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1579 * set by another thread while the object is locked. Thus, 1580 * if PGA_WRITEABLE is clear, no page table entries need updating. 1581 */ 1582 VM_OBJECT_ASSERT_WLOCKED(m->object); 1583 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1584 return; 1585 powerpc_sync(); 1586 LOCK_TABLE_RD(); 1587 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1588 pmap = pvo->pvo_pmap; 1589 PMAP_LOCK(pmap); 1590 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1591 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1592 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1593 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1594 if (pt != -1) { 1595 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1596 lo |= pvo->pvo_pte.lpte.pte_lo; 1597 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1598 MOEA64_PTE_CHANGE(mmu, pt, 1599 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1600 if (pvo->pvo_pmap == kernel_pmap) 1601 isync(); 1602 } 1603 } 1604 if ((lo & LPTE_CHG) != 0) 1605 vm_page_dirty(m); 1606 PMAP_UNLOCK(pmap); 1607 } 1608 UNLOCK_TABLE_RD(); 1609 vm_page_aflag_clear(m, PGA_WRITEABLE); 1610} 1611 1612/* 1613 * moea64_ts_referenced: 1614 * 1615 * Return a count of reference bits for a page, clearing those bits. 1616 * It is not necessary for every reference bit to be cleared, but it 1617 * is necessary that 0 only be returned when there are truly no 1618 * reference bits set. 1619 * 1620 * XXX: The exact number of bits to check and clear is a matter that 1621 * should be tested and standardized at some point in the future for 1622 * optimal aging of shared pages. 1623 */ 1624int 1625moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1626{ 1627 1628 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1629 ("moea64_ts_referenced: page %p is not managed", m)); 1630 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1631} 1632 1633/* 1634 * Modify the WIMG settings of all mappings for a page. 1635 */ 1636void 1637moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1638{ 1639 struct pvo_entry *pvo; 1640 struct pvo_head *pvo_head; 1641 uintptr_t pt; 1642 pmap_t pmap; 1643 uint64_t lo; 1644 1645 if ((m->oflags & VPO_UNMANAGED) != 0) { 1646 m->md.mdpg_cache_attrs = ma; 1647 return; 1648 } 1649 1650 pvo_head = vm_page_to_pvoh(m); 1651 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1652 LOCK_TABLE_RD(); 1653 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1654 pmap = pvo->pvo_pmap; 1655 PMAP_LOCK(pmap); 1656 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1657 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1658 pvo->pvo_pte.lpte.pte_lo |= lo; 1659 if (pt != -1) { 1660 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1661 pvo->pvo_vpn); 1662 if (pvo->pvo_pmap == kernel_pmap) 1663 isync(); 1664 } 1665 PMAP_UNLOCK(pmap); 1666 } 1667 UNLOCK_TABLE_RD(); 1668 m->md.mdpg_cache_attrs = ma; 1669} 1670 1671/* 1672 * Map a wired page into kernel virtual address space. 1673 */ 1674void 1675moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1676{ 1677 uint64_t pte_lo; 1678 int error; 1679 1680 pte_lo = moea64_calc_wimg(pa, ma); 1681 1682 LOCK_TABLE_WR(); 1683 PMAP_LOCK(kernel_pmap); 1684 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1685 NULL, va, pa, pte_lo, PVO_WIRED, 0); 1686 PMAP_UNLOCK(kernel_pmap); 1687 UNLOCK_TABLE_WR(); 1688 1689 if (error != 0 && error != ENOENT) 1690 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1691 pa, error); 1692} 1693 1694void 1695moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1696{ 1697 1698 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1699} 1700 1701/* 1702 * Extract the physical page address associated with the given kernel virtual 1703 * address. 1704 */ 1705vm_paddr_t 1706moea64_kextract(mmu_t mmu, vm_offset_t va) 1707{ 1708 struct pvo_entry *pvo; 1709 vm_paddr_t pa; 1710 1711 /* 1712 * Shortcut the direct-mapped case when applicable. We never put 1713 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1714 */ 1715 if (va < VM_MIN_KERNEL_ADDRESS) 1716 return (va); 1717 1718 PMAP_LOCK(kernel_pmap); 1719 pvo = moea64_pvo_find_va(kernel_pmap, va); 1720 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1721 va)); 1722 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1723 PMAP_UNLOCK(kernel_pmap); 1724 return (pa); 1725} 1726 1727/* 1728 * Remove a wired page from kernel virtual address space. 1729 */ 1730void 1731moea64_kremove(mmu_t mmu, vm_offset_t va) 1732{ 1733 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1734} 1735 1736/* 1737 * Map a range of physical addresses into kernel virtual address space. 1738 * 1739 * The value passed in *virt is a suggested virtual address for the mapping. 1740 * Architectures which can support a direct-mapped physical to virtual region 1741 * can return the appropriate address within that region, leaving '*virt' 1742 * unchanged. We cannot and therefore do not; *virt is updated with the 1743 * first usable address after the mapped region. 1744 */ 1745vm_offset_t 1746moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1747 vm_paddr_t pa_end, int prot) 1748{ 1749 vm_offset_t sva, va; 1750 1751 sva = *virt; 1752 va = sva; 1753 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1754 moea64_kenter(mmu, va, pa_start); 1755 *virt = va; 1756 1757 return (sva); 1758} 1759 1760/* 1761 * Returns true if the pmap's pv is one of the first 1762 * 16 pvs linked to from this page. This count may 1763 * be changed upwards or downwards in the future; it 1764 * is only necessary that true be returned for a small 1765 * subset of pmaps for proper page aging. 1766 */ 1767boolean_t 1768moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1769{ 1770 int loops; 1771 struct pvo_entry *pvo; 1772 boolean_t rv; 1773 1774 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1775 ("moea64_page_exists_quick: page %p is not managed", m)); 1776 loops = 0; 1777 rv = FALSE; 1778 LOCK_TABLE_RD(); 1779 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1780 if (pvo->pvo_pmap == pmap) { 1781 rv = TRUE; 1782 break; 1783 } 1784 if (++loops >= 16) 1785 break; 1786 } 1787 UNLOCK_TABLE_RD(); 1788 return (rv); 1789} 1790 1791/* 1792 * Return the number of managed mappings to the given physical page 1793 * that are wired. 1794 */ 1795int 1796moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1797{ 1798 struct pvo_entry *pvo; 1799 int count; 1800 1801 count = 0; 1802 if ((m->oflags & VPO_UNMANAGED) != 0) 1803 return (count); 1804 LOCK_TABLE_RD(); 1805 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1806 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1807 count++; 1808 UNLOCK_TABLE_RD(); 1809 return (count); 1810} 1811 1812static uintptr_t moea64_vsidcontext; 1813 1814uintptr_t 1815moea64_get_unique_vsid(void) { 1816 u_int entropy; 1817 register_t hash; 1818 uint32_t mask; 1819 int i; 1820 1821 entropy = 0; 1822 __asm __volatile("mftb %0" : "=r"(entropy)); 1823 1824 mtx_lock(&moea64_slb_mutex); 1825 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1826 u_int n; 1827 1828 /* 1829 * Create a new value by mutiplying by a prime and adding in 1830 * entropy from the timebase register. This is to make the 1831 * VSID more random so that the PT hash function collides 1832 * less often. (Note that the prime casues gcc to do shifts 1833 * instead of a multiply.) 1834 */ 1835 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1836 hash = moea64_vsidcontext & (NVSIDS - 1); 1837 if (hash == 0) /* 0 is special, avoid it */ 1838 continue; 1839 n = hash >> 5; 1840 mask = 1 << (hash & (VSID_NBPW - 1)); 1841 hash = (moea64_vsidcontext & VSID_HASHMASK); 1842 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1843 /* anything free in this bucket? */ 1844 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1845 entropy = (moea64_vsidcontext >> 20); 1846 continue; 1847 } 1848 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1849 mask = 1 << i; 1850 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1851 hash |= i; 1852 } 1853 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1854 ("Allocating in-use VSID %#zx\n", hash)); 1855 moea64_vsid_bitmap[n] |= mask; 1856 mtx_unlock(&moea64_slb_mutex); 1857 return (hash); 1858 } 1859 1860 mtx_unlock(&moea64_slb_mutex); 1861 panic("%s: out of segments",__func__); 1862} 1863 1864#ifdef __powerpc64__ 1865void 1866moea64_pinit(mmu_t mmu, pmap_t pmap) 1867{ 1868 1869 RB_INIT(&pmap->pmap_pvo); 1870 1871 pmap->pm_slb_tree_root = slb_alloc_tree(); 1872 pmap->pm_slb = slb_alloc_user_cache(); 1873 pmap->pm_slb_len = 0; 1874} 1875#else 1876void 1877moea64_pinit(mmu_t mmu, pmap_t pmap) 1878{ 1879 int i; 1880 uint32_t hash; 1881 1882 RB_INIT(&pmap->pmap_pvo); 1883 1884 if (pmap_bootstrapped) 1885 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1886 (vm_offset_t)pmap); 1887 else 1888 pmap->pmap_phys = pmap; 1889 1890 /* 1891 * Allocate some segment registers for this pmap. 1892 */ 1893 hash = moea64_get_unique_vsid(); 1894 1895 for (i = 0; i < 16; i++) 1896 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1897 1898 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1899} 1900#endif 1901 1902/* 1903 * Initialize the pmap associated with process 0. 1904 */ 1905void 1906moea64_pinit0(mmu_t mmu, pmap_t pm) 1907{ 1908 1909 PMAP_LOCK_INIT(pm); 1910 moea64_pinit(mmu, pm); 1911 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1912} 1913 1914/* 1915 * Set the physical protection on the specified range of this map as requested. 1916 */ 1917static void 1918moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 1919{ 1920 uintptr_t pt; 1921 struct vm_page *pg; 1922 uint64_t oldlo; 1923 1924 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1925 1926 /* 1927 * Grab the PTE pointer before we diddle with the cached PTE 1928 * copy. 1929 */ 1930 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1931 1932 /* 1933 * Change the protection of the page. 1934 */ 1935 oldlo = pvo->pvo_pte.lpte.pte_lo; 1936 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1937 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1938 if ((prot & VM_PROT_EXECUTE) == 0) 1939 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1940 if (prot & VM_PROT_WRITE) 1941 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW; 1942 else 1943 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1944 1945 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1946 1947 /* 1948 * If the PVO is in the page table, update that pte as well. 1949 */ 1950 if (pt != -1) 1951 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1952 pvo->pvo_vpn); 1953 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 1954 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1955 if ((pg->oflags & VPO_UNMANAGED) == 0) 1956 vm_page_aflag_set(pg, PGA_EXECUTABLE); 1957 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 1958 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE); 1959 } 1960 1961 /* 1962 * Update vm about the REF/CHG bits if the page is managed and we have 1963 * removed write access. 1964 */ 1965 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && 1966 (oldlo & LPTE_PP) != LPTE_BR && !(prot & VM_PROT_WRITE)) { 1967 if (pg != NULL) { 1968 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 1969 vm_page_dirty(pg); 1970 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 1971 vm_page_aflag_set(pg, PGA_REFERENCED); 1972 } 1973 } 1974} 1975 1976void 1977moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1978 vm_prot_t prot) 1979{ 1980 struct pvo_entry *pvo, *tpvo, key; 1981 1982 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 1983 sva, eva, prot); 1984 1985 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1986 ("moea64_protect: non current pmap")); 1987 1988 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1989 moea64_remove(mmu, pm, sva, eva); 1990 return; 1991 } 1992 1993 LOCK_TABLE_RD(); 1994 PMAP_LOCK(pm); 1995 key.pvo_vaddr = sva; 1996 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1997 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1998 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1999 moea64_pvo_protect(mmu, pm, pvo, prot); 2000 } 2001 UNLOCK_TABLE_RD(); 2002 PMAP_UNLOCK(pm); 2003} 2004 2005/* 2006 * Map a list of wired pages into kernel virtual address space. This is 2007 * intended for temporary mappings which do not need page modification or 2008 * references recorded. Existing mappings in the region are overwritten. 2009 */ 2010void 2011moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2012{ 2013 while (count-- > 0) { 2014 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2015 va += PAGE_SIZE; 2016 m++; 2017 } 2018} 2019 2020/* 2021 * Remove page mappings from kernel virtual address space. Intended for 2022 * temporary mappings entered by moea64_qenter. 2023 */ 2024void 2025moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2026{ 2027 while (count-- > 0) { 2028 moea64_kremove(mmu, va); 2029 va += PAGE_SIZE; 2030 } 2031} 2032 2033void 2034moea64_release_vsid(uint64_t vsid) 2035{ 2036 int idx, mask; 2037 2038 mtx_lock(&moea64_slb_mutex); 2039 idx = vsid & (NVSIDS-1); 2040 mask = 1 << (idx % VSID_NBPW); 2041 idx /= VSID_NBPW; 2042 KASSERT(moea64_vsid_bitmap[idx] & mask, 2043 ("Freeing unallocated VSID %#jx", vsid)); 2044 moea64_vsid_bitmap[idx] &= ~mask; 2045 mtx_unlock(&moea64_slb_mutex); 2046} 2047 2048 2049void 2050moea64_release(mmu_t mmu, pmap_t pmap) 2051{ 2052 2053 /* 2054 * Free segment registers' VSIDs 2055 */ 2056 #ifdef __powerpc64__ 2057 slb_free_tree(pmap); 2058 slb_free_user_cache(pmap->pm_slb); 2059 #else 2060 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2061 2062 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2063 #endif 2064} 2065 2066/* 2067 * Remove all pages mapped by the specified pmap 2068 */ 2069void 2070moea64_remove_pages(mmu_t mmu, pmap_t pm) 2071{ 2072 struct pvo_entry *pvo, *tpvo; 2073 2074 LOCK_TABLE_WR(); 2075 PMAP_LOCK(pm); 2076 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2077 if (!(pvo->pvo_vaddr & PVO_WIRED)) 2078 moea64_pvo_remove(mmu, pvo); 2079 } 2080 UNLOCK_TABLE_WR(); 2081 PMAP_UNLOCK(pm); 2082} 2083 2084/* 2085 * Remove the given range of addresses from the specified map. 2086 */ 2087void 2088moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2089{ 2090 struct pvo_entry *pvo, *tpvo, key; 2091 2092 /* 2093 * Perform an unsynchronized read. This is, however, safe. 2094 */ 2095 if (pm->pm_stats.resident_count == 0) 2096 return; 2097 2098 LOCK_TABLE_WR(); 2099 PMAP_LOCK(pm); 2100 key.pvo_vaddr = sva; 2101 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2102 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2103 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2104 moea64_pvo_remove(mmu, pvo); 2105 } 2106 UNLOCK_TABLE_WR(); 2107 PMAP_UNLOCK(pm); 2108} 2109 2110/* 2111 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2112 * will reflect changes in pte's back to the vm_page. 2113 */ 2114void 2115moea64_remove_all(mmu_t mmu, vm_page_t m) 2116{ 2117 struct pvo_entry *pvo, *next_pvo; 2118 pmap_t pmap; 2119 2120 LOCK_TABLE_WR(); 2121 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2122 pmap = pvo->pvo_pmap; 2123 PMAP_LOCK(pmap); 2124 moea64_pvo_remove(mmu, pvo); 2125 PMAP_UNLOCK(pmap); 2126 } 2127 UNLOCK_TABLE_WR(); 2128 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m)) 2129 vm_page_dirty(m); 2130 vm_page_aflag_clear(m, PGA_WRITEABLE); 2131 vm_page_aflag_clear(m, PGA_EXECUTABLE); 2132} 2133 2134/* 2135 * Allocate a physical page of memory directly from the phys_avail map. 2136 * Can only be called from moea64_bootstrap before avail start and end are 2137 * calculated. 2138 */ 2139vm_offset_t 2140moea64_bootstrap_alloc(vm_size_t size, u_int align) 2141{ 2142 vm_offset_t s, e; 2143 int i, j; 2144 2145 size = round_page(size); 2146 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2147 if (align != 0) 2148 s = (phys_avail[i] + align - 1) & ~(align - 1); 2149 else 2150 s = phys_avail[i]; 2151 e = s + size; 2152 2153 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2154 continue; 2155 2156 if (s + size > platform_real_maxaddr()) 2157 continue; 2158 2159 if (s == phys_avail[i]) { 2160 phys_avail[i] += size; 2161 } else if (e == phys_avail[i + 1]) { 2162 phys_avail[i + 1] -= size; 2163 } else { 2164 for (j = phys_avail_count * 2; j > i; j -= 2) { 2165 phys_avail[j] = phys_avail[j - 2]; 2166 phys_avail[j + 1] = phys_avail[j - 1]; 2167 } 2168 2169 phys_avail[i + 3] = phys_avail[i + 1]; 2170 phys_avail[i + 1] = s; 2171 phys_avail[i + 2] = e; 2172 phys_avail_count++; 2173 } 2174 2175 return (s); 2176 } 2177 panic("moea64_bootstrap_alloc: could not allocate memory"); 2178} 2179 2180static int 2181moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2182 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2183 uint64_t pte_lo, int flags, int8_t psind __unused) 2184{ 2185 struct pvo_entry *pvo; 2186 uintptr_t pt; 2187 uint64_t vsid; 2188 int first; 2189 u_int ptegidx; 2190 int i; 2191 int bootstrap; 2192 2193 /* 2194 * One nasty thing that can happen here is that the UMA calls to 2195 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2196 * which calls UMA... 2197 * 2198 * We break the loop by detecting recursion and allocating out of 2199 * the bootstrap pool. 2200 */ 2201 2202 first = 0; 2203 bootstrap = (flags & PVO_BOOTSTRAP); 2204 2205 if (!moea64_initialized) 2206 bootstrap = 1; 2207 2208 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2209 rw_assert(&moea64_table_lock, RA_WLOCKED); 2210 2211 /* 2212 * Compute the PTE Group index. 2213 */ 2214 va &= ~ADDR_POFF; 2215 vsid = va_to_vsid(pm, va); 2216 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2217 2218 /* 2219 * Remove any existing mapping for this page. Reuse the pvo entry if 2220 * there is a mapping. 2221 */ 2222 moea64_pvo_enter_calls++; 2223 2224 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2225 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2226 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2227 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2228 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2229 /* 2230 * The physical page and protection are not 2231 * changing. Instead, this may be a request 2232 * to change the mapping's wired attribute. 2233 */ 2234 pt = -1; 2235 if ((flags & PVO_WIRED) != 0 && 2236 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2237 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2238 pvo->pvo_vaddr |= PVO_WIRED; 2239 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2240 pm->pm_stats.wired_count++; 2241 } else if ((flags & PVO_WIRED) == 0 && 2242 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2243 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2244 pvo->pvo_vaddr &= ~PVO_WIRED; 2245 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 2246 pm->pm_stats.wired_count--; 2247 } 2248 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2249 KASSERT(pt == -1, 2250 ("moea64_pvo_enter: valid pt")); 2251 /* Re-insert if spilled */ 2252 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2253 &pvo->pvo_pte.lpte); 2254 if (i >= 0) 2255 PVO_PTEGIDX_SET(pvo, i); 2256 moea64_pte_overflow--; 2257 } else if (pt != -1) { 2258 /* 2259 * The PTE's wired attribute is not a 2260 * hardware feature, so there is no 2261 * need to invalidate any TLB entries. 2262 */ 2263 MOEA64_PTE_CHANGE(mmu, pt, 2264 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2265 } 2266 return (0); 2267 } 2268 moea64_pvo_remove(mmu, pvo); 2269 break; 2270 } 2271 } 2272 2273 /* 2274 * If we aren't overwriting a mapping, try to allocate. 2275 */ 2276 if (bootstrap) { 2277 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2278 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2279 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2280 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2281 } 2282 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2283 moea64_bpvo_pool_index++; 2284 bootstrap = 1; 2285 } else { 2286 pvo = uma_zalloc(zone, M_NOWAIT); 2287 } 2288 2289 if (pvo == NULL) 2290 return (ENOMEM); 2291 2292 moea64_pvo_entries++; 2293 pvo->pvo_vaddr = va; 2294 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2295 | (vsid << 16); 2296 pvo->pvo_pmap = pm; 2297 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2298 pvo->pvo_vaddr &= ~ADDR_POFF; 2299 2300 if (flags & PVO_WIRED) 2301 pvo->pvo_vaddr |= PVO_WIRED; 2302 if (pvo_head != NULL) 2303 pvo->pvo_vaddr |= PVO_MANAGED; 2304 if (bootstrap) 2305 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2306 if (flags & PVO_LARGE) 2307 pvo->pvo_vaddr |= PVO_LARGE; 2308 2309 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2310 (uint64_t)(pa) | pte_lo, flags); 2311 2312 /* 2313 * Add to pmap list 2314 */ 2315 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2316 2317 /* 2318 * Remember if the list was empty and therefore will be the first 2319 * item. 2320 */ 2321 if (pvo_head != NULL) { 2322 if (LIST_FIRST(pvo_head) == NULL) 2323 first = 1; 2324 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2325 } 2326 2327 if (pvo->pvo_vaddr & PVO_WIRED) { 2328 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2329 pm->pm_stats.wired_count++; 2330 } 2331 pm->pm_stats.resident_count++; 2332 2333 /* 2334 * We hope this succeeds but it isn't required. 2335 */ 2336 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2337 if (i >= 0) { 2338 PVO_PTEGIDX_SET(pvo, i); 2339 } else { 2340 panic("moea64_pvo_enter: overflow"); 2341 moea64_pte_overflow++; 2342 } 2343 2344 if (pm == kernel_pmap) 2345 isync(); 2346 2347#ifdef __powerpc64__ 2348 /* 2349 * Make sure all our bootstrap mappings are in the SLB as soon 2350 * as virtual memory is switched on. 2351 */ 2352 if (!pmap_bootstrapped) 2353 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2354#endif 2355 2356 return (first ? ENOENT : 0); 2357} 2358 2359static void 2360moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2361{ 2362 struct vm_page *pg; 2363 uintptr_t pt; 2364 2365 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2366 rw_assert(&moea64_table_lock, RA_WLOCKED); 2367 2368 /* 2369 * If there is an active pte entry, we need to deactivate it (and 2370 * save the ref & cfg bits). 2371 */ 2372 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2373 if (pt != -1) { 2374 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2375 PVO_PTEGIDX_CLR(pvo); 2376 } else { 2377 moea64_pte_overflow--; 2378 } 2379 2380 /* 2381 * Update our statistics. 2382 */ 2383 pvo->pvo_pmap->pm_stats.resident_count--; 2384 if (pvo->pvo_vaddr & PVO_WIRED) 2385 pvo->pvo_pmap->pm_stats.wired_count--; 2386 2387 /* 2388 * Remove this PVO from the pmap list. 2389 */ 2390 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2391 2392 /* 2393 * Remove this from the overflow list and return it to the pool 2394 * if we aren't going to reuse it. 2395 */ 2396 LIST_REMOVE(pvo, pvo_olink); 2397 2398 /* 2399 * Update vm about the REF/CHG bits if the page is managed. 2400 */ 2401 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2402 2403 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) { 2404 LIST_REMOVE(pvo, pvo_vlink); 2405 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 2406 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 2407 vm_page_dirty(pg); 2408 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 2409 vm_page_aflag_set(pg, PGA_REFERENCED); 2410 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2411 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2412 } 2413 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2414 vm_page_aflag_clear(pg, PGA_EXECUTABLE); 2415 } 2416 2417 moea64_pvo_entries--; 2418 moea64_pvo_remove_calls++; 2419 2420 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2421 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2422 moea64_upvo_zone, pvo); 2423} 2424 2425static struct pvo_entry * 2426moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2427{ 2428 struct pvo_entry key; 2429 2430 key.pvo_vaddr = va & ~ADDR_POFF; 2431 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2432} 2433 2434static boolean_t 2435moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2436{ 2437 struct pvo_entry *pvo; 2438 uintptr_t pt; 2439 2440 LOCK_TABLE_RD(); 2441 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2442 /* 2443 * See if we saved the bit off. If so, return success. 2444 */ 2445 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2446 UNLOCK_TABLE_RD(); 2447 return (TRUE); 2448 } 2449 } 2450 2451 /* 2452 * No luck, now go through the hard part of looking at the PTEs 2453 * themselves. Sync so that any pending REF/CHG bits are flushed to 2454 * the PTEs. 2455 */ 2456 powerpc_sync(); 2457 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2458 2459 /* 2460 * See if this pvo has a valid PTE. if so, fetch the 2461 * REF/CHG bits from the valid PTE. If the appropriate 2462 * ptebit is set, return success. 2463 */ 2464 PMAP_LOCK(pvo->pvo_pmap); 2465 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2466 if (pt != -1) { 2467 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2468 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2469 PMAP_UNLOCK(pvo->pvo_pmap); 2470 UNLOCK_TABLE_RD(); 2471 return (TRUE); 2472 } 2473 } 2474 PMAP_UNLOCK(pvo->pvo_pmap); 2475 } 2476 2477 UNLOCK_TABLE_RD(); 2478 return (FALSE); 2479} 2480 2481static u_int 2482moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2483{ 2484 u_int count; 2485 struct pvo_entry *pvo; 2486 uintptr_t pt; 2487 2488 /* 2489 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2490 * we can reset the right ones). note that since the pvo entries and 2491 * list heads are accessed via BAT0 and are never placed in the page 2492 * table, we don't have to worry about further accesses setting the 2493 * REF/CHG bits. 2494 */ 2495 powerpc_sync(); 2496 2497 /* 2498 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2499 * valid pte clear the ptebit from the valid pte. 2500 */ 2501 count = 0; 2502 LOCK_TABLE_RD(); 2503 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2504 PMAP_LOCK(pvo->pvo_pmap); 2505 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2506 if (pt != -1) { 2507 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2508 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2509 count++; 2510 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2511 pvo->pvo_vpn, ptebit); 2512 } 2513 } 2514 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2515 PMAP_UNLOCK(pvo->pvo_pmap); 2516 } 2517 2518 UNLOCK_TABLE_RD(); 2519 return (count); 2520} 2521 2522boolean_t 2523moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2524{ 2525 struct pvo_entry *pvo, key; 2526 vm_offset_t ppa; 2527 int error = 0; 2528 2529 PMAP_LOCK(kernel_pmap); 2530 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2531 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2532 ppa < pa + size; ppa += PAGE_SIZE, 2533 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2534 if (pvo == NULL || 2535 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2536 error = EFAULT; 2537 break; 2538 } 2539 } 2540 PMAP_UNLOCK(kernel_pmap); 2541 2542 return (error); 2543} 2544 2545/* 2546 * Map a set of physical memory pages into the kernel virtual 2547 * address space. Return a pointer to where it is mapped. This 2548 * routine is intended to be used for mapping device memory, 2549 * NOT real memory. 2550 */ 2551void * 2552moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2553{ 2554 vm_offset_t va, tmpva, ppa, offset; 2555 2556 ppa = trunc_page(pa); 2557 offset = pa & PAGE_MASK; 2558 size = roundup2(offset + size, PAGE_SIZE); 2559 2560 va = kva_alloc(size); 2561 2562 if (!va) 2563 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2564 2565 for (tmpva = va; size > 0;) { 2566 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2567 size -= PAGE_SIZE; 2568 tmpva += PAGE_SIZE; 2569 ppa += PAGE_SIZE; 2570 } 2571 2572 return ((void *)(va + offset)); 2573} 2574 2575void * 2576moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2577{ 2578 2579 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2580} 2581 2582void 2583moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2584{ 2585 vm_offset_t base, offset; 2586 2587 base = trunc_page(va); 2588 offset = va & PAGE_MASK; 2589 size = roundup2(offset + size, PAGE_SIZE); 2590 2591 kva_free(base, size); 2592} 2593 2594void 2595moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2596{ 2597 struct pvo_entry *pvo; 2598 vm_offset_t lim; 2599 vm_paddr_t pa; 2600 vm_size_t len; 2601 2602 PMAP_LOCK(pm); 2603 while (sz > 0) { 2604 lim = round_page(va); 2605 len = MIN(lim - va, sz); 2606 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2607 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) { 2608 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 2609 (va & ADDR_POFF); 2610 moea64_syncicache(mmu, pm, va, pa, len); 2611 } 2612 va += len; 2613 sz -= len; 2614 } 2615 PMAP_UNLOCK(pm); 2616} 2617 2618vm_offset_t 2619moea64_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2620 vm_size_t *sz) 2621{ 2622 if (md->md_vaddr == ~0UL) 2623 return (md->md_paddr + ofs); 2624 else 2625 return (md->md_vaddr + ofs); 2626} 2627 2628struct pmap_md * 2629moea64_scan_md(mmu_t mmu, struct pmap_md *prev) 2630{ 2631 static struct pmap_md md; 2632 struct pvo_entry *pvo; 2633 vm_offset_t va; 2634 2635 if (dumpsys_minidump) { 2636 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2637 if (prev == NULL) { 2638 /* 1st: kernel .data and .bss. */ 2639 md.md_index = 1; 2640 md.md_vaddr = trunc_page((uintptr_t)_etext); 2641 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2642 return (&md); 2643 } 2644 switch (prev->md_index) { 2645 case 1: 2646 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2647 md.md_index = 2; 2648 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr; 2649 md.md_size = round_page(msgbufp->msg_size); 2650 break; 2651 case 2: 2652 /* 3rd: kernel VM. */ 2653 va = prev->md_vaddr + prev->md_size; 2654 /* Find start of next chunk (from va). */ 2655 while (va < virtual_end) { 2656 /* Don't dump the buffer cache. */ 2657 if (va >= kmi.buffer_sva && 2658 va < kmi.buffer_eva) { 2659 va = kmi.buffer_eva; 2660 continue; 2661 } 2662 pvo = moea64_pvo_find_va(kernel_pmap, 2663 va & ~ADDR_POFF); 2664 if (pvo != NULL && 2665 (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) 2666 break; 2667 va += PAGE_SIZE; 2668 } 2669 if (va < virtual_end) { 2670 md.md_vaddr = va; 2671 va += PAGE_SIZE; 2672 /* Find last page in chunk. */ 2673 while (va < virtual_end) { 2674 /* Don't run into the buffer cache. */ 2675 if (va == kmi.buffer_sva) 2676 break; 2677 pvo = moea64_pvo_find_va(kernel_pmap, 2678 va & ~ADDR_POFF); 2679 if (pvo == NULL || 2680 !(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) 2681 break; 2682 va += PAGE_SIZE; 2683 } 2684 md.md_size = va - md.md_vaddr; 2685 break; 2686 } 2687 md.md_index = 3; 2688 /* FALLTHROUGH */ 2689 default: 2690 return (NULL); 2691 } 2692 } else { /* minidumps */ 2693 if (prev == NULL) { 2694 /* first physical chunk. */ 2695 md.md_paddr = pregions[0].mr_start; 2696 md.md_size = pregions[0].mr_size; 2697 md.md_vaddr = ~0UL; 2698 md.md_index = 1; 2699 } else if (md.md_index < pregions_sz) { 2700 md.md_paddr = pregions[md.md_index].mr_start; 2701 md.md_size = pregions[md.md_index].mr_size; 2702 md.md_vaddr = ~0UL; 2703 md.md_index++; 2704 } else { 2705 /* There's no next physical chunk. */ 2706 return (NULL); 2707 } 2708 } 2709 2710 return (&md); 2711} 2712