mlx4_en.h revision 297967
1193326Sed/* 2226633Sdim * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved. 3198092Srdivacky * 4203955Srdivacky * This software is available to you under a choice of one of two 5226633Sdim * licenses. You may choose to be licensed under the terms of the GNU 6193326Sed * General Public License (GPL) Version 2, available from the file 7226633Sdim * COPYING in the main directory of this source tree, or the 8226633Sdim * OpenIB.org BSD license below: 9193326Sed * 10226633Sdim * Redistribution and use in source and binary forms, with or 11226633Sdim * without modification, are permitted provided that the following 12226633Sdim * conditions are met: 13193326Sed * 14226633Sdim * - Redistributions of source code must retain the above 15193326Sed * copyright notice, this list of conditions and the following 16193326Sed * disclaimer. 17198092Srdivacky * 18226633Sdim * - Redistributions in binary form must reproduce the above 19226633Sdim * copyright notice, this list of conditions and the following 20226633Sdim * disclaimer in the documentation and/or other materials 21226633Sdim * provided with the distribution. 22226633Sdim * 23226633Sdim * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24226633Sdim * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25226633Sdim * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26226633Sdim * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27226633Sdim * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28226633Sdim * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29226633Sdim * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30226633Sdim * SOFTWARE. 31226633Sdim * 32226633Sdim */ 33226633Sdim 34226633Sdim#ifndef _MLX4_EN_H_ 35226633Sdim#define _MLX4_EN_H_ 36226633Sdim 37226633Sdim#include <linux/bitops.h> 38226633Sdim#include <linux/compiler.h> 39226633Sdim#include <linux/list.h> 40226633Sdim#include <linux/mutex.h> 41226633Sdim#include <linux/kobject.h> 42226633Sdim#include <linux/netdevice.h> 43226633Sdim#include <linux/if_vlan.h> 44226633Sdim#include <linux/if_ether.h> 45226633Sdim#ifdef CONFIG_MLX4_EN_DCB 46226633Sdim#include <linux/dcbnl.h> 47226633Sdim#endif 48226633Sdim 49226633Sdim#include <linux/mlx4/device.h> 50226633Sdim#include <linux/mlx4/qp.h> 51226633Sdim#include <linux/mlx4/cq.h> 52226633Sdim#include <linux/mlx4/srq.h> 53226633Sdim#include <linux/mlx4/doorbell.h> 54226633Sdim#include <linux/mlx4/cmd.h> 55226633Sdim 56198092Srdivacky#include <netinet/tcp_lro.h> 57226633Sdim 58226633Sdim#include "en_port.h" 59226633Sdim#include "mlx4_stats.h" 60226633Sdim 61226633Sdim#define DRV_NAME "mlx4_en" 62226633Sdim 63226633Sdim#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 64226633Sdim 65226633Sdim/* 66226633Sdim * Device constants 67226633Sdim */ 68226633Sdim 69226633Sdim 70226633Sdim#define MLX4_EN_PAGE_SHIFT 12 71226633Sdim#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 72226633Sdim#define MLX4_NET_IP_ALIGN 2 /* bytes */ 73226633Sdim#define DEF_RX_RINGS 16 74226633Sdim#define MAX_RX_RINGS 128 75226633Sdim#define MIN_RX_RINGS 4 76226633Sdim#define TXBB_SIZE 64 77226633Sdim#define HEADROOM (2048 / TXBB_SIZE + 1) 78226633Sdim#define STAMP_STRIDE 64 79226633Sdim#define STAMP_DWORDS (STAMP_STRIDE / 4) 80226633Sdim#define STAMP_SHIFT 31 81226633Sdim#define STAMP_VAL 0x7fffffff 82226633Sdim#define STATS_DELAY (HZ / 4) 83226633Sdim#define SERVICE_TASK_DELAY (HZ / 4) 84226633Sdim#define MAX_NUM_OF_FS_RULES 256 85226633Sdim 86226633Sdim#define MLX4_EN_FILTER_HASH_SHIFT 4 87226633Sdim#define MLX4_EN_FILTER_EXPIRY_QUOTA 60 88226633Sdim 89226633Sdim#ifdef CONFIG_NET_RX_BUSY_POLL 90226633Sdim#define LL_EXTENDED_STATS 91226633Sdim#endif 92226633Sdim 93226633Sdim/* vlan valid range */ 94226633Sdim#define VLAN_MIN_VALUE 1 95226633Sdim#define VLAN_MAX_VALUE 4094 96193326Sed 97226633Sdim/* 98226633Sdim * OS related constants and tunables 99226633Sdim */ 100226633Sdim 101226633Sdim#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 102226633Sdim 103226633Sdim#define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(PAGE_SIZE) 104226633Sdim#define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE) 105226633Sdim 106226633Sdimenum mlx4_en_alloc_type { 107226633Sdim MLX4_EN_ALLOC_NEW = 0, 108226633Sdim MLX4_EN_ALLOC_REPLACEMENT = 1, 109226633Sdim}; 110226633Sdim 111226633Sdim/* Maximum ring sizes */ 112226633Sdim#define MLX4_EN_DEF_TX_QUEUE_SIZE 4096 113226633Sdim 114226633Sdim/* Minimum packet number till arming the CQ */ 115226633Sdim#define MLX4_EN_MIN_RX_ARM 2048 116198092Srdivacky#define MLX4_EN_MIN_TX_ARM 2048 117226633Sdim 118226633Sdim/* Maximum ring sizes */ 119226633Sdim#define MLX4_EN_MAX_TX_SIZE 8192 120226633Sdim#define MLX4_EN_MAX_RX_SIZE 8192 121193326Sed 122226633Sdim/* Minimum ring sizes */ 123226633Sdim#define MLX4_EN_MIN_RX_SIZE (4096 / TXBB_SIZE) 124226633Sdim#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 125226633Sdim 126226633Sdim#define MLX4_EN_SMALL_PKT_SIZE 64 127226633Sdim 128226633Sdim#define MLX4_EN_MAX_TX_RING_P_UP 32 129193326Sed#define MLX4_EN_NUM_UP 1 130226633Sdim 131193326Sed#define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 132226633Sdim MLX4_EN_NUM_UP) 133226633Sdim 134198092Srdivacky#define MLX4_EN_DEF_TX_RING_SIZE 1024 135226633Sdim#define MLX4_EN_DEF_RX_RING_SIZE 1024 136193326Sed 137226633Sdim/* Target number of bytes to coalesce with interrupt moderation */ 138226633Sdim#define MLX4_EN_RX_COAL_TARGET 0x20000 139226633Sdim#define MLX4_EN_RX_COAL_TIME 0x10 140226633Sdim 141193326Sed#define MLX4_EN_TX_COAL_PKTS 64 142226633Sdim#define MLX4_EN_TX_COAL_TIME 64 143226633Sdim 144226633Sdim#define MLX4_EN_RX_RATE_LOW 400000 145226633Sdim#define MLX4_EN_RX_COAL_TIME_LOW 0 146226633Sdim#define MLX4_EN_RX_RATE_HIGH 450000 147226633Sdim#define MLX4_EN_RX_COAL_TIME_HIGH 128 148226633Sdim#define MLX4_EN_RX_SIZE_THRESH 1024 149226633Sdim#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 150193326Sed#define MLX4_EN_SAMPLE_INTERVAL 0 151226633Sdim#define MLX4_EN_AVG_PKT_SMALL 256 152226633Sdim 153198092Srdivacky#define MLX4_EN_AUTO_CONF 0xffff 154226633Sdim 155226633Sdim#define MLX4_EN_DEF_RX_PAUSE 1 156226633Sdim#define MLX4_EN_DEF_TX_PAUSE 1 157226633Sdim 158226633Sdim/* Interval between successive polls in the Tx routine when polling is used 159226633Sdim instead of interrupts (in per-core Tx rings) - should be power of 2 */ 160226633Sdim#define MLX4_EN_TX_POLL_MODER 16 161226633Sdim#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 162193326Sed 163226633Sdim#define MLX4_EN_64_ALIGN (64 - NET_SKB_PAD) 164226633Sdim#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 165226633Sdim#define HEADER_COPY_SIZE (128) 166198092Srdivacky#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETHER_HDR_LEN) 167226633Sdim 168226633Sdim#define MLX4_EN_MIN_MTU 46 169193326Sed#define ETH_BCAST 0xffffffffffffULL 170226633Sdim 171226633Sdim#define MLX4_EN_LOOPBACK_RETRIES 5 172226633Sdim#define MLX4_EN_LOOPBACK_TIMEOUT 100 173198092Srdivacky 174204643Srdivacky#ifdef MLX4_EN_PERF_STAT 175226633Sdim/* Number of samples to 'average' */ 176226633Sdim#define AVG_SIZE 128 177226633Sdim#define AVG_FACTOR 1024 178226633Sdim 179226633Sdim#define INC_PERF_COUNTER(cnt) (++(cnt)) 180226633Sdim#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 181226633Sdim#define AVG_PERF_COUNTER(cnt, sample) \ 182193326Sed ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 183193326Sed#define GET_PERF_COUNTER(cnt) (cnt) 184226633Sdim#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 185226633Sdim 186226633Sdim#else 187226633Sdim 188226633Sdim#define INC_PERF_COUNTER(cnt) do {} while (0) 189226633Sdim#define ADD_PERF_COUNTER(cnt, add) do {} while (0) 190226633Sdim#define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 191226633Sdim#define GET_PERF_COUNTER(cnt) (0) 192226633Sdim#define GET_AVG_PERF_COUNTER(cnt) (0) 193226633Sdim#endif /* MLX4_EN_PERF_STAT */ 194226633Sdim 195226633Sdim/* 196226633Sdim * Configurables 197226633Sdim */ 198226633Sdim 199226633Sdimenum cq_type { 200226633Sdim RX = 0, 201226633Sdim TX = 1, 202226633Sdim}; 203226633Sdim 204226633Sdim 205226633Sdim/* 206226633Sdim * Useful macros 207226633Sdim */ 208226633Sdim#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 209226633Sdim#define XNOR(x, y) (!(x) == !(y)) 210226633Sdim#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0) 211226633Sdim 212226633Sdimstruct mlx4_en_tx_info { 213226633Sdim bus_dmamap_t dma_map; 214226633Sdim struct mbuf *mb; 215226633Sdim u32 nr_txbb; 216226633Sdim u32 nr_bytes; 217226633Sdim}; 218226633Sdim 219193326Sed 220226633Sdim#define MLX4_EN_BIT_DESC_OWN 0x80000000 221198092Srdivacky#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 222193326Sed#define MLX4_EN_MEMTYPE_PAD 0x100 223226633Sdim#define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 224226633Sdim 225226633Sdim 226193326Sedstruct mlx4_en_tx_desc { 227226633Sdim struct mlx4_wqe_ctrl_seg ctrl; 228226633Sdim union { 229226633Sdim struct mlx4_wqe_data_seg data; /* at least one data segment */ 230193326Sed struct mlx4_wqe_lso_seg lso; 231226633Sdim struct mlx4_wqe_inline_seg inl; 232226633Sdim }; 233226633Sdim}; 234226633Sdim 235226633Sdim#define MLX4_EN_USE_SRQ 0x01000000 236226633Sdim 237226633Sdim#define MLX4_EN_RX_BUDGET 64 238226633Sdim 239226633Sdim#define MLX4_EN_TX_MAX_DESC_SIZE 512 /* bytes */ 240226633Sdim#define MLX4_EN_TX_MAX_MBUF_SIZE 65536 /* bytes */ 241226633Sdim#define MLX4_EN_TX_MAX_PAYLOAD_SIZE 65536 /* bytes */ 242226633Sdim#define MLX4_EN_TX_MAX_MBUF_FRAGS \ 243198092Srdivacky ((MLX4_EN_TX_MAX_DESC_SIZE - 128) / DS_SIZE_ALIGNMENT) /* units */ 244226633Sdim#define MLX4_EN_TX_WQE_MAX_WQEBBS \ 245226633Sdim (MLX4_EN_TX_MAX_DESC_SIZE / TXBB_SIZE) /* units */ 246226633Sdim 247201361Srdivacky#define MLX4_EN_CX3_LOW_ID 0x1000 248226633Sdim#define MLX4_EN_CX3_HIGH_ID 0x1005 249226633Sdim 250226633Sdimstruct mlx4_en_tx_ring { 251226633Sdim spinlock_t tx_lock; 252226633Sdim bus_dma_tag_t dma_tag; 253226633Sdim struct mlx4_hwq_resources wqres; 254226633Sdim u32 size ; /* number of TXBBs */ 255226633Sdim u32 size_mask; 256226633Sdim u16 stride; 257198092Srdivacky u16 cqn; /* index of port CQ associated with this ring */ 258226633Sdim u32 prod; 259226633Sdim u32 cons; 260218893Sdim u32 buf_size; 261226633Sdim u32 doorbell_qpn; 262226633Sdim u8 *buf; 263226633Sdim u16 poll_cnt; 264226633Sdim int blocked; 265226633Sdim struct mlx4_en_tx_info *tx_info; 266198092Srdivacky u8 queue_index; 267226633Sdim cpuset_t affinity_mask; 268226633Sdim struct buf_ring *br; 269226633Sdim u32 last_nr_txbb; 270198092Srdivacky struct mlx4_qp qp; 271226633Sdim struct mlx4_qp_context context; 272226633Sdim int qpn; 273226633Sdim enum mlx4_qp_state qp_state; 274198092Srdivacky struct mlx4_srq dummy; 275226633Sdim unsigned long bytes; 276226633Sdim unsigned long packets; 277226633Sdim unsigned long tx_csum; 278198092Srdivacky unsigned long queue_stopped; 279226633Sdim unsigned long oversized_packets; 280226633Sdim unsigned long wake_queue; 281226633Sdim struct mlx4_bf bf; 282201361Srdivacky bool bf_enabled; 283226633Sdim int hwtstamp_tx_type; 284226633Sdim spinlock_t comp_lock; 285226633Sdim int inline_thold; 286198092Srdivacky u64 watchdog_time; 287226633Sdim}; 288226633Sdim 289226633Sdimstruct mlx4_en_rx_desc { 290198092Srdivacky /* actual number of entries depends on rx ring stride */ 291226633Sdim struct mlx4_wqe_data_seg data[0]; 292226633Sdim}; 293226633Sdim 294198092Srdivackystruct mlx4_en_rx_mbuf { 295226633Sdim bus_dmamap_t dma_map; 296226633Sdim struct mbuf *mbuf; 297226633Sdim}; 298226633Sdim 299226633Sdimstruct mlx4_en_rx_spare { 300226633Sdim bus_dmamap_t dma_map; 301226633Sdim struct mbuf *mbuf; 302226633Sdim u64 paddr_be; 303226633Sdim}; 304226633Sdim 305226633Sdimstruct mlx4_en_rx_ring { 306226633Sdim struct mlx4_hwq_resources wqres; 307226633Sdim bus_dma_tag_t dma_tag; 308226633Sdim struct mlx4_en_rx_spare spare; 309226633Sdim u32 size ; /* number of Rx descs*/ 310226633Sdim u32 actual_size; 311226633Sdim u32 size_mask; 312226633Sdim u16 stride; 313226633Sdim u16 log_stride; 314226633Sdim u16 cqn; /* index of port CQ associated with this ring */ 315226633Sdim u32 prod; 316226633Sdim u32 cons; 317226633Sdim u32 buf_size; 318226633Sdim u8 fcs_del; 319226633Sdim u16 rx_alloc_order; 320226633Sdim u32 rx_alloc_size; 321226633Sdim u32 rx_buf_size; 322226633Sdim u32 rx_mb_size; 323226633Sdim int qpn; 324226633Sdim u8 *buf; 325226633Sdim struct mlx4_en_rx_mbuf *mbuf; 326226633Sdim unsigned long errors; 327193326Sed unsigned long bytes; 328226633Sdim unsigned long packets; 329226633Sdim#ifdef LL_EXTENDED_STATS 330193326Sed unsigned long yields; 331226633Sdim unsigned long misses; 332226633Sdim unsigned long cleaned; 333226633Sdim#endif 334226633Sdim unsigned long csum_ok; 335201361Srdivacky unsigned long csum_none; 336226633Sdim int hwtstamp_rx_filter; 337226633Sdim int numa_node; 338226633Sdim struct lro_ctrl lro; 339226633Sdim}; 340226633Sdim 341226633Sdimstatic inline int mlx4_en_can_lro(__be16 status) 342226633Sdim{ 343226633Sdim const __be16 status_all = cpu_to_be16( 344226633Sdim MLX4_CQE_STATUS_IPV4 | 345226633Sdim MLX4_CQE_STATUS_IPV4F | 346226633Sdim MLX4_CQE_STATUS_IPV6 | 347226633Sdim MLX4_CQE_STATUS_IPV4OPT | 348226633Sdim MLX4_CQE_STATUS_TCP | 349226633Sdim MLX4_CQE_STATUS_UDP | 350226633Sdim MLX4_CQE_STATUS_IPOK); 351226633Sdim const __be16 status_ipv4_ipok_tcp = cpu_to_be16( 352226633Sdim MLX4_CQE_STATUS_IPV4 | 353226633Sdim MLX4_CQE_STATUS_IPOK | 354226633Sdim MLX4_CQE_STATUS_TCP); 355226633Sdim const __be16 status_ipv6_ipok_tcp = cpu_to_be16( 356226633Sdim MLX4_CQE_STATUS_IPV6 | 357226633Sdim MLX4_CQE_STATUS_IPOK | 358226633Sdim MLX4_CQE_STATUS_TCP); 359226633Sdim 360226633Sdim status &= status_all; 361226633Sdim return (status == status_ipv4_ipok_tcp || 362226633Sdim status == status_ipv6_ipok_tcp); 363226633Sdim} 364226633Sdim 365226633Sdimstruct mlx4_en_cq { 366226633Sdim struct mlx4_cq mcq; 367226633Sdim struct mlx4_hwq_resources wqres; 368226633Sdim int ring; 369226633Sdim spinlock_t lock; 370226633Sdim struct net_device *dev; 371226633Sdim /* Per-core Tx cq processing support */ 372226633Sdim struct timer_list timer; 373226633Sdim int size; 374226633Sdim int buf_size; 375226633Sdim unsigned vector; 376226633Sdim enum cq_type is_tx; 377226633Sdim u16 moder_time; 378226633Sdim u16 moder_cnt; 379226633Sdim struct mlx4_cqe *buf; 380226633Sdim struct task cq_task; 381226633Sdim struct taskqueue *tq; 382226633Sdim#define MLX4_EN_OPCODE_ERROR 0x1e 383226633Sdim u32 tot_rx; 384226633Sdim u32 tot_tx; 385226633Sdim u32 curr_poll_rx_cpu_id; 386226633Sdim 387226633Sdim#ifdef CONFIG_NET_RX_BUSY_POLL 388226633Sdim unsigned int state; 389226633Sdim#define MLX4_EN_CQ_STATEIDLE 0 390226633Sdim#define MLX4_EN_CQ_STATENAPI 1 /* NAPI owns this CQ */ 391226633Sdim#define MLX4_EN_CQ_STATEPOLL 2 /* poll owns this CQ */ 392226633Sdim#define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATENAPI | MLX4_EN_CQ_STATEPOLL) 393226633Sdim#define MLX4_EN_CQ_STATENAPI_YIELD 4 /* NAPI yielded this CQ */ 394226633Sdim#define MLX4_EN_CQ_STATEPOLL_YIELD 8 /* poll yielded this CQ */ 395226633Sdim#define CQ_YIELD (MLX4_EN_CQ_STATENAPI_YIELD | MLX4_EN_CQ_STATEPOLL_YIELD) 396201361Srdivacky#define CQ_USER_PEND (MLX4_EN_CQ_STATEPOLL | MLX4_EN_CQ_STATEPOLL_YIELD) 397198092Srdivacky spinlock_t poll_lock; /* protects from LLS/napi conflicts */ 398226633Sdim#endif /* CONFIG_NET_RX_BUSY_POLL */ 399226633Sdim}; 400226633Sdim 401226633Sdimstruct mlx4_en_port_profile { 402226633Sdim u32 flags; 403226633Sdim u32 tx_ring_num; 404226633Sdim u32 rx_ring_num; 405226633Sdim u32 tx_ring_size; 406226633Sdim u32 rx_ring_size; 407226633Sdim u8 rx_pause; 408226633Sdim u8 rx_ppp; 409226633Sdim u8 tx_pause; 410226633Sdim u8 tx_ppp; 411198092Srdivacky int rss_rings; 412226633Sdim}; 413226633Sdim 414226633Sdimstruct mlx4_en_profile { 415226633Sdim int rss_xor; 416193326Sed int udp_rss; 417226633Sdim u8 rss_mask; 418226633Sdim u32 active_ports; 419226633Sdim u32 small_pkt_int; 420226633Sdim u8 no_reset; 421193326Sed u8 num_tx_rings_p_up; 422193326Sed struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 423226633Sdim}; 424199990Srdivacky 425226633Sdimstruct mlx4_en_dev { 426226633Sdim struct mlx4_dev *dev; 427199990Srdivacky struct pci_dev *pdev; 428226633Sdim struct mutex state_lock; 429226633Sdim struct net_device *pndev[MLX4_MAX_PORTS + 1]; 430226633Sdim u32 port_cnt; 431226633Sdim bool device_up; 432199990Srdivacky struct mlx4_en_profile profile; 433199990Srdivacky u32 LSO_support; 434198092Srdivacky struct workqueue_struct *workqueue; 435226633Sdim struct device *dma_device; 436226633Sdim void __iomem *uar_map; 437226633Sdim struct mlx4_uar priv_uar; 438226633Sdim struct mlx4_mr mr; 439193326Sed u32 priv_pdn; 440193326Sed spinlock_t uar_lock; 441226633Sdim u8 mac_removed[MLX4_MAX_PORTS + 1]; 442226633Sdim unsigned long last_overflow_check; 443226633Sdim unsigned long overflow_period; 444226633Sdim}; 445226633Sdim 446226633Sdim 447226633Sdimstruct mlx4_en_rss_map { 448226633Sdim int base_qpn; 449198092Srdivacky struct mlx4_qp qps[MAX_RX_RINGS]; 450226633Sdim enum mlx4_qp_state state[MAX_RX_RINGS]; 451226633Sdim struct mlx4_qp indir_qp; 452226633Sdim enum mlx4_qp_state indir_state; 453226633Sdim}; 454193326Sed 455226633Sdimstruct mlx4_en_port_state { 456226633Sdim int link_state; 457193326Sed int link_speed; 458193326Sed int transciver; 459226633Sdim int autoneg; 460226633Sdim}; 461226633Sdim 462226633Sdimenum mlx4_en_mclist_act { 463193326Sed MCLIST_NONE, 464226633Sdim MCLIST_REM, 465226633Sdim MCLIST_ADD, 466226633Sdim}; 467193326Sed 468193326Sedstruct mlx4_en_mc_list { 469193326Sed struct list_head list; 470226633Sdim enum mlx4_en_mclist_act action; 471226633Sdim u8 addr[ETH_ALEN]; 472226633Sdim u64 reg_id; 473226633Sdim}; 474226633Sdim 475226633Sdim#ifdef CONFIG_MLX4_EN_DCB 476226633Sdim/* Minimal TC BW - setting to 0 will block traffic */ 477226633Sdim#define MLX4_EN_BW_MIN 1 478198092Srdivacky#define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 479226633Sdim 480226633Sdim#define MLX4_EN_TC_ETS 7 481226633Sdim 482226633Sdim#endif 483226633Sdim 484226633Sdim 485198092Srdivackyenum { 486226633Sdim MLX4_EN_FLAG_PROMISC = (1 << 0), 487226633Sdim MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 488226633Sdim /* whether we need to enable hardware loopback by putting dmac 489226633Sdim * in Tx WQE 490226633Sdim */ 491226633Sdim MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 492226633Sdim /* whether we need to drop packets that hardware loopback-ed */ 493226633Sdim MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 494226633Sdim MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 495226633Sdim#ifdef CONFIG_MLX4_EN_DCB 496212904Sdim MLX4_EN_FLAG_DCB_ENABLED = (1 << 5) 497226633Sdim#endif 498212904Sdim}; 499212904Sdim 500226633Sdim#define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 501193326Sed#define MLX4_EN_MAC_HASH_IDX 5 502226633Sdim 503226633Sdimstruct en_port { 504226633Sdim struct kobject kobj; 505226633Sdim struct mlx4_dev *dev; 506226633Sdim u8 port_num; 507226633Sdim u8 vport_num; 508193326Sed}; 509198092Srdivacky 510226633Sdimstruct mlx4_en_priv { 511226633Sdim struct mlx4_en_dev *mdev; 512226633Sdim struct mlx4_en_port_profile *prof; 513226633Sdim struct net_device *dev; 514193326Sed unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 515226633Sdim struct mlx4_en_port_state port_state; 516226633Sdim spinlock_t stats_lock; 517226633Sdim /* To allow rules removal while port is going down */ 518226633Sdim struct list_head ethtool_list; 519226633Sdim 520226633Sdim unsigned long last_moder_packets[MAX_RX_RINGS]; 521226633Sdim unsigned long last_moder_tx_packets; 522226633Sdim unsigned long last_moder_bytes[MAX_RX_RINGS]; 523226633Sdim unsigned long last_moder_jiffies; 524226633Sdim int last_moder_time[MAX_RX_RINGS]; 525226633Sdim u16 rx_usecs; 526226633Sdim u16 rx_frames; 527226633Sdim u16 tx_usecs; 528226633Sdim u16 tx_frames; 529226633Sdim u32 pkt_rate_low; 530226633Sdim u32 rx_usecs_low; 531193326Sed u32 pkt_rate_high; 532226633Sdim u32 rx_usecs_high; 533226633Sdim u32 sample_interval; 534198092Srdivacky u32 adaptive_rx_coal; 535226633Sdim u32 msg_enable; 536226633Sdim u32 loopback_ok; 537226633Sdim u32 validate_loopback; 538226633Sdim 539193326Sed struct mlx4_hwq_resources res; 540193326Sed int link_state; 541226633Sdim int last_link_state; 542204643Srdivacky bool port_up; 543226633Sdim int port; 544226633Sdim int registered; 545193326Sed int allocated; 546198092Srdivacky int stride; 547226633Sdim unsigned char current_mac[ETH_ALEN + 2]; 548226633Sdim u64 mac; 549226633Sdim int mac_index; 550193326Sed unsigned max_mtu; 551226633Sdim int base_qpn; 552226633Sdim int cqe_factor; 553226633Sdim 554226633Sdim struct mlx4_en_rss_map rss_map; 555193326Sed u32 flags; 556226633Sdim u8 num_tx_rings_p_up; 557193326Sed u32 tx_ring_num; 558226633Sdim u32 rx_ring_num; 559226633Sdim u32 rx_mb_size; 560226633Sdim u16 rx_alloc_order; 561226633Sdim u32 rx_alloc_size; 562193326Sed u32 rx_buf_size; 563226633Sdim 564226633Sdim struct mlx4_en_tx_ring **tx_ring; 565226633Sdim struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 566226633Sdim struct mlx4_en_cq **tx_cq; 567226633Sdim struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 568226633Sdim struct mlx4_qp drop_qp; 569226633Sdim struct work_struct rx_mode_task; 570226633Sdim struct work_struct watchdog_task; 571226633Sdim struct work_struct linkstate_task; 572226633Sdim struct delayed_work stats_task; 573226633Sdim struct delayed_work service_task; 574226633Sdim struct mlx4_en_perf_stats pstats; 575226633Sdim struct mlx4_en_pkt_stats pkstats; 576226633Sdim struct mlx4_en_pkt_stats pkstats_last; 577226633Sdim struct mlx4_en_flow_stats flowstats[MLX4_NUM_PRIORITIES]; 578226633Sdim struct mlx4_en_port_stats port_stats; 579226633Sdim struct mlx4_en_vport_stats vport_stats; 580226633Sdim struct mlx4_en_vf_stats vf_stats; 581226633Sdim DECLARE_BITMAP(stats_bitmap, NUM_ALL_STATS); 582226633Sdim struct list_head mc_list; 583226633Sdim struct list_head curr_list; 584226633Sdim u64 broadcast_id; 585226633Sdim struct mlx4_en_stat_out_mbox hw_stats; 586226633Sdim int vids[128]; 587226633Sdim bool wol; 588226633Sdim struct device *ddev; 589226633Sdim struct dentry *dev_root; 590226633Sdim u32 counter_index; 591226633Sdim eventhandler_tag vlan_attach; 592226633Sdim eventhandler_tag vlan_detach; 593226633Sdim struct callout watchdog_timer; 594226633Sdim struct ifmedia media; 595226633Sdim volatile int blocked; 596226633Sdim struct sysctl_oid *sysctl; 597226633Sdim struct sysctl_ctx_list conf_ctx; 598226633Sdim struct sysctl_ctx_list stat_ctx; 599226633Sdim#define MLX4_EN_MAC_HASH_IDX 5 600226633Sdim struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 601226633Sdim 602226633Sdim#ifdef CONFIG_MLX4_EN_DCB 603226633Sdim struct ieee_ets ets; 604226633Sdim u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 605226633Sdim u8 dcbx_cap; 606226633Sdim#endif 607226633Sdim#ifdef CONFIG_RFS_ACCEL 608193326Sed spinlock_t filters_lock; 609226633Sdim int last_filter_id; 610226633Sdim struct list_head filters; 611226633Sdim struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 612226633Sdim#endif 613226633Sdim struct en_port *vf_ports[MLX4_MAX_NUM_VF]; 614226633Sdim unsigned long last_ifq_jiffies; 615226633Sdim u64 if_counters_rx_errors; 616226633Sdim u64 if_counters_rx_no_buffer; 617226633Sdim}; 618226633Sdim 619193326Sedenum mlx4_en_wol { 620193326Sed MLX4_EN_WOL_MAGIC = (1ULL << 61), 621226633Sdim MLX4_EN_WOL_ENABLED = (1ULL << 62), 622226633Sdim}; 623193326Sed 624193326Sedstruct mlx4_mac_entry { 625226633Sdim struct hlist_node hlist; 626226633Sdim unsigned char mac[ETH_ALEN + 2]; 627226633Sdim u64 reg_id; 628226633Sdim}; 629193326Sed 630193326Sed#ifdef CONFIG_NET_RX_BUSY_POLL 631226633Sdimstatic inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 632226633Sdim{ 633193326Sed spin_lock_init(&cq->poll_lock); 634193326Sed cq->state = MLX4_EN_CQ_STATEIDLE; 635226633Sdim} 636226633Sdim 637226633Sdim/* called from the device poll rutine to get ownership of a cq */ 638226633Sdimstatic inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 639226633Sdim{ 640226633Sdim int rc = true; 641226633Sdim spin_lock(&cq->poll_lock); 642226633Sdim if (cq->state & MLX4_CQ_LOCKED) { 643193326Sed WARN_ON(cq->state & MLX4_EN_CQ_STATENAPI); 644226633Sdim cq->state |= MLX4_EN_CQ_STATENAPI_YIELD; 645193326Sed rc = false; 646226633Sdim } else 647226633Sdim /* we don't care if someone yielded */ 648226633Sdim cq->state = MLX4_EN_CQ_STATENAPI; 649226633Sdim spin_unlock(&cq->poll_lock); 650226633Sdim return rc; 651226633Sdim} 652226633Sdim 653226633Sdim/* returns true is someone tried to get the cq while napi had it */ 654226633Sdimstatic inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 655226633Sdim{ 656226633Sdim int rc = false; 657226633Sdim spin_lock(&cq->poll_lock); 658226633Sdim WARN_ON(cq->state & (MLX4_EN_CQ_STATEPOLL | 659226633Sdim MLX4_EN_CQ_STATENAPI_YIELD)); 660226633Sdim 661226633Sdim if (cq->state & MLX4_EN_CQ_STATEPOLL_YIELD) 662226633Sdim rc = true; 663226633Sdim cq->state = MLX4_EN_CQ_STATEIDLE; 664226633Sdim spin_unlock(&cq->poll_lock); 665226633Sdim return rc; 666226633Sdim} 667198398Srdivacky 668193326Sed/* called from mlx4_en_low_latency_poll() */ 669226633Sdimstatic inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 670226633Sdim{ 671198092Srdivacky int rc = true; 672193326Sed spin_lock_bh(&cq->poll_lock); 673226633Sdim if ((cq->state & MLX4_CQ_LOCKED)) { 674226633Sdim struct net_device *dev = cq->dev; 675 struct mlx4_en_priv *priv = netdev_priv(dev); 676 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; 677 678 cq->state |= MLX4_EN_CQ_STATEPOLL_YIELD; 679 rc = false; 680#ifdef LL_EXTENDED_STATS 681 rx_ring->yields++; 682#endif 683 } else 684 /* preserve yield marks */ 685 cq->state |= MLX4_EN_CQ_STATEPOLL; 686 spin_unlock_bh(&cq->poll_lock); 687 return rc; 688} 689 690/* returns true if someone tried to get the cq while it was locked */ 691static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 692{ 693 int rc = false; 694 spin_lock_bh(&cq->poll_lock); 695 WARN_ON(cq->state & (MLX4_EN_CQ_STATENAPI)); 696 697 if (cq->state & MLX4_EN_CQ_STATEPOLL_YIELD) 698 rc = true; 699 cq->state = MLX4_EN_CQ_STATEIDLE; 700 spin_unlock_bh(&cq->poll_lock); 701 return rc; 702} 703 704/* true if a socket is polling, even if it did not get the lock */ 705static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq) 706{ 707 WARN_ON(!(cq->state & MLX4_CQ_LOCKED)); 708 return cq->state & CQ_USER_PEND; 709} 710#else 711static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 712{ 713} 714 715static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 716{ 717 return true; 718} 719 720static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 721{ 722 return false; 723} 724 725static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 726{ 727 return false; 728} 729 730static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 731{ 732 return false; 733} 734 735static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq) 736{ 737 return false; 738} 739#endif /* CONFIG_NET_RX_BUSY_POLL */ 740 741#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 742 743void mlx4_en_destroy_netdev(struct net_device *dev); 744int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 745 struct mlx4_en_port_profile *prof); 746 747int mlx4_en_start_port(struct net_device *dev); 748void mlx4_en_stop_port(struct net_device *dev); 749 750void mlx4_en_free_resources(struct mlx4_en_priv *priv); 751int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 752 753int mlx4_en_pre_config(struct mlx4_en_priv *priv); 754int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 755 int entries, int ring, enum cq_type mode, int node); 756void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 757int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 758 int cq_idx); 759void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 760int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 761int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 762 763void mlx4_en_tx_irq(struct mlx4_cq *mcq); 764u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb); 765 766int mlx4_en_transmit(struct ifnet *dev, struct mbuf *m); 767int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 768 struct mlx4_en_tx_ring **pring, 769 u32 size, u16 stride, int node, int queue_idx); 770void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 771 struct mlx4_en_tx_ring **pring); 772int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 773 struct mlx4_en_tx_ring *ring, 774 int cq, int user_prio); 775void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 776 struct mlx4_en_tx_ring *ring); 777void mlx4_en_qflush(struct ifnet *dev); 778 779int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 780 struct mlx4_en_rx_ring **pring, 781 u32 size, int node); 782void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 783 struct mlx4_en_rx_ring **pring, 784 u32 size, u16 stride); 785void mlx4_en_tx_que(void *context, int pending); 786void mlx4_en_rx_que(void *context, int pending); 787int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 788void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 789 struct mlx4_en_rx_ring *ring); 790int mlx4_en_process_rx_cq(struct net_device *dev, 791 struct mlx4_en_cq *cq, 792 int budget); 793void mlx4_en_poll_tx_cq(unsigned long data); 794void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 795 int is_tx, int rss, int qpn, int cqn, int user_prio, 796 struct mlx4_qp_context *context); 797void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 798int mlx4_en_map_buffer(struct mlx4_buf *buf); 799void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 800void mlx4_en_calc_rx_buf(struct net_device *dev); 801 802int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 803void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 804int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 805void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 806int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 807void mlx4_en_rx_irq(struct mlx4_cq *mcq); 808 809int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 810int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 811 812int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 813int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 814int mlx4_en_get_vport_stats(struct mlx4_en_dev *mdev, u8 port); 815void mlx4_en_create_debug_files(struct mlx4_en_priv *priv); 816void mlx4_en_delete_debug_files(struct mlx4_en_priv *priv); 817int mlx4_en_register_debugfs(void); 818void mlx4_en_unregister_debugfs(void); 819 820#ifdef CONFIG_MLX4_EN_DCB 821extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 822extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 823#endif 824 825int mlx4_en_setup_tc(struct net_device *dev, u8 up); 826 827#ifdef CONFIG_RFS_ACCEL 828void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv, 829 struct mlx4_en_rx_ring *rx_ring); 830#endif 831 832#define MLX4_EN_NUM_SELF_TEST 5 833void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 834void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 835 836/* 837 * Functions for time stamping 838 */ 839#define SKBTX_HW_TSTAMP (1 << 0) 840#define SKBTX_IN_PROGRESS (1 << 2) 841 842u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 843 844/* Functions for caching and restoring statistics */ 845int mlx4_en_get_sset_count(struct net_device *dev, int sset); 846void mlx4_en_restore_ethtool_stats(struct mlx4_en_priv *priv, 847 u64 *data); 848 849/* 850 * Globals 851 */ 852extern const struct ethtool_ops mlx4_en_ethtool_ops; 853 854/* 855 * Defines for link speed - needed by selftest 856 */ 857#define MLX4_EN_LINK_SPEED_1G 1000 858#define MLX4_EN_LINK_SPEED_10G 10000 859#define MLX4_EN_LINK_SPEED_40G 40000 860 861enum { 862 NETIF_MSG_DRV = 0x0001, 863 NETIF_MSG_PROBE = 0x0002, 864 NETIF_MSG_LINK = 0x0004, 865 NETIF_MSG_TIMER = 0x0008, 866 NETIF_MSG_IFDOWN = 0x0010, 867 NETIF_MSG_IFUP = 0x0020, 868 NETIF_MSG_RX_ERR = 0x0040, 869 NETIF_MSG_TX_ERR = 0x0080, 870 NETIF_MSG_TX_QUEUED = 0x0100, 871 NETIF_MSG_INTR = 0x0200, 872 NETIF_MSG_TX_DONE = 0x0400, 873 NETIF_MSG_RX_STATUS = 0x0800, 874 NETIF_MSG_PKTDATA = 0x1000, 875 NETIF_MSG_HW = 0x2000, 876 NETIF_MSG_WOL = 0x4000, 877}; 878 879 880/* 881 * printk / logging functions 882 */ 883 884#define en_print(level, priv, format, arg...) \ 885 { \ 886 if ((priv)->registered) \ 887 printk(level "%s: %s: " format, DRV_NAME, \ 888 (priv->dev)->if_xname, ## arg); \ 889 else \ 890 printk(level "%s: %s: Port %d: " format, \ 891 DRV_NAME, dev_name(&priv->mdev->pdev->dev), \ 892 (priv)->port, ## arg); \ 893 } 894 895 896#define en_dbg(mlevel, priv, format, arg...) \ 897do { \ 898 if (NETIF_MSG_##mlevel & priv->msg_enable) \ 899 en_print(KERN_DEBUG, priv, format, ##arg); \ 900} while (0) 901#define en_warn(priv, format, arg...) \ 902 en_print(KERN_WARNING, priv, format, ##arg) 903#define en_err(priv, format, arg...) \ 904 en_print(KERN_ERR, priv, format, ##arg) 905#define en_info(priv, format, arg...) \ 906 en_print(KERN_INFO, priv, format, ## arg) 907 908#define mlx4_err(mdev, format, arg...) \ 909 pr_err("%s %s: " format, DRV_NAME, \ 910 dev_name(&mdev->pdev->dev), ##arg) 911#define mlx4_info(mdev, format, arg...) \ 912 pr_info("%s %s: " format, DRV_NAME, \ 913 dev_name(&mdev->pdev->dev), ##arg) 914#define mlx4_warn(mdev, format, arg...) \ 915 pr_warning("%s %s: " format, DRV_NAME, \ 916 dev_name(&mdev->pdev->dev), ##arg) 917 918#endif 919