mlx4_en.h revision 291699
1/* 2 * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34#ifndef _MLX4_EN_H_ 35#define _MLX4_EN_H_ 36 37#include <linux/bitops.h> 38#include <linux/compiler.h> 39#include <linux/list.h> 40#include <linux/mutex.h> 41#include <linux/kobject.h> 42#include <linux/netdevice.h> 43#include <linux/if_vlan.h> 44#include <linux/if_ether.h> 45#ifdef CONFIG_MLX4_EN_DCB 46#include <linux/dcbnl.h> 47#endif 48 49#include <linux/mlx4/device.h> 50#include <linux/mlx4/qp.h> 51#include <linux/mlx4/cq.h> 52#include <linux/mlx4/srq.h> 53#include <linux/mlx4/doorbell.h> 54#include <linux/mlx4/cmd.h> 55 56#include <netinet/tcp_lro.h> 57 58#include "en_port.h" 59#include "mlx4_stats.h" 60 61#define DRV_NAME "mlx4_en" 62 63#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 64 65/* 66 * Device constants 67 */ 68 69 70#define MLX4_EN_PAGE_SHIFT 12 71#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 72#define DEF_RX_RINGS 16 73#define MAX_RX_RINGS 128 74#define MIN_RX_RINGS 4 75#define TXBB_SIZE 64 76#define HEADROOM (2048 / TXBB_SIZE + 1) 77#define STAMP_STRIDE 64 78#define STAMP_DWORDS (STAMP_STRIDE / 4) 79#define STAMP_SHIFT 31 80#define STAMP_VAL 0x7fffffff 81#define STATS_DELAY (HZ / 4) 82#define SERVICE_TASK_DELAY (HZ / 4) 83#define MAX_NUM_OF_FS_RULES 256 84 85#define MLX4_EN_FILTER_HASH_SHIFT 4 86#define MLX4_EN_FILTER_EXPIRY_QUOTA 60 87 88#ifdef CONFIG_NET_RX_BUSY_POLL 89#define LL_EXTENDED_STATS 90#endif 91 92/* vlan valid range */ 93#define VLAN_MIN_VALUE 1 94#define VLAN_MAX_VALUE 4094 95 96/* 97 * OS related constants and tunables 98 */ 99 100#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 101 102#define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(PAGE_SIZE) 103#define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE) 104 105enum mlx4_en_alloc_type { 106 MLX4_EN_ALLOC_NEW = 0, 107 MLX4_EN_ALLOC_REPLACEMENT = 1, 108}; 109 110/* Maximum ring sizes */ 111#define MLX4_EN_DEF_TX_QUEUE_SIZE 4096 112 113/* Minimum packet number till arming the CQ */ 114#define MLX4_EN_MIN_RX_ARM 2048 115#define MLX4_EN_MIN_TX_ARM 2048 116 117/* Maximum ring sizes */ 118#define MLX4_EN_MAX_TX_SIZE 8192 119#define MLX4_EN_MAX_RX_SIZE 8192 120 121/* Minimum ring sizes */ 122#define MLX4_EN_MIN_RX_SIZE (4096 / TXBB_SIZE) 123#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 124 125#define MLX4_EN_SMALL_PKT_SIZE 64 126 127#define MLX4_EN_MAX_TX_RING_P_UP 32 128#define MLX4_EN_NUM_UP 1 129 130#define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 131 MLX4_EN_NUM_UP) 132 133#define MLX4_EN_DEF_TX_RING_SIZE 1024 134#define MLX4_EN_DEF_RX_RING_SIZE 1024 135 136/* Target number of bytes to coalesce with interrupt moderation */ 137#define MLX4_EN_RX_COAL_TARGET 0x20000 138#define MLX4_EN_RX_COAL_TIME 0x10 139 140#define MLX4_EN_TX_COAL_PKTS 64 141#define MLX4_EN_TX_COAL_TIME 64 142 143#define MLX4_EN_RX_RATE_LOW 400000 144#define MLX4_EN_RX_COAL_TIME_LOW 0 145#define MLX4_EN_RX_RATE_HIGH 450000 146#define MLX4_EN_RX_COAL_TIME_HIGH 128 147#define MLX4_EN_RX_SIZE_THRESH 1024 148#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 149#define MLX4_EN_SAMPLE_INTERVAL 0 150#define MLX4_EN_AVG_PKT_SMALL 256 151 152#define MLX4_EN_AUTO_CONF 0xffff 153 154#define MLX4_EN_DEF_RX_PAUSE 1 155#define MLX4_EN_DEF_TX_PAUSE 1 156 157/* Interval between successive polls in the Tx routine when polling is used 158 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 159#define MLX4_EN_TX_POLL_MODER 16 160#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 161 162#define MLX4_EN_64_ALIGN (64 - NET_SKB_PAD) 163#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 164#define HEADER_COPY_SIZE (128) 165#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETHER_HDR_LEN) 166 167#define MLX4_EN_MIN_MTU 46 168#define ETH_BCAST 0xffffffffffffULL 169 170#define MLX4_EN_LOOPBACK_RETRIES 5 171#define MLX4_EN_LOOPBACK_TIMEOUT 100 172 173#ifdef MLX4_EN_PERF_STAT 174/* Number of samples to 'average' */ 175#define AVG_SIZE 128 176#define AVG_FACTOR 1024 177 178#define INC_PERF_COUNTER(cnt) (++(cnt)) 179#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 180#define AVG_PERF_COUNTER(cnt, sample) \ 181 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 182#define GET_PERF_COUNTER(cnt) (cnt) 183#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 184 185#else 186 187#define INC_PERF_COUNTER(cnt) do {} while (0) 188#define ADD_PERF_COUNTER(cnt, add) do {} while (0) 189#define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 190#define GET_PERF_COUNTER(cnt) (0) 191#define GET_AVG_PERF_COUNTER(cnt) (0) 192#endif /* MLX4_EN_PERF_STAT */ 193 194/* 195 * Configurables 196 */ 197 198enum cq_type { 199 RX = 0, 200 TX = 1, 201}; 202 203 204/* 205 * Useful macros 206 */ 207#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 208#define XNOR(x, y) (!(x) == !(y)) 209#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0) 210 211struct mlx4_en_tx_info { 212 bus_dmamap_t dma_map; 213 struct mbuf *mb; 214 u32 nr_txbb; 215 u32 nr_bytes; 216}; 217 218 219#define MLX4_EN_BIT_DESC_OWN 0x80000000 220#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 221#define MLX4_EN_MEMTYPE_PAD 0x100 222#define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 223 224 225struct mlx4_en_tx_desc { 226 struct mlx4_wqe_ctrl_seg ctrl; 227 union { 228 struct mlx4_wqe_data_seg data; /* at least one data segment */ 229 struct mlx4_wqe_lso_seg lso; 230 struct mlx4_wqe_inline_seg inl; 231 }; 232}; 233 234#define MLX4_EN_USE_SRQ 0x01000000 235 236#define MLX4_EN_RX_BUDGET 64 237 238#define MLX4_EN_TX_MAX_DESC_SIZE 512 /* bytes */ 239#define MLX4_EN_TX_MAX_MBUF_SIZE 65536 /* bytes */ 240#define MLX4_EN_TX_MAX_PAYLOAD_SIZE 65536 /* bytes */ 241#define MLX4_EN_TX_MAX_MBUF_FRAGS \ 242 ((MLX4_EN_TX_MAX_DESC_SIZE - 128) / DS_SIZE_ALIGNMENT) /* units */ 243#define MLX4_EN_TX_WQE_MAX_WQEBBS \ 244 (MLX4_EN_TX_MAX_DESC_SIZE / TXBB_SIZE) /* units */ 245 246#define MLX4_EN_CX3_LOW_ID 0x1000 247#define MLX4_EN_CX3_HIGH_ID 0x1005 248 249struct mlx4_en_tx_ring { 250 spinlock_t tx_lock; 251 bus_dma_tag_t dma_tag; 252 struct mlx4_hwq_resources wqres; 253 u32 size ; /* number of TXBBs */ 254 u32 size_mask; 255 u16 stride; 256 u16 cqn; /* index of port CQ associated with this ring */ 257 u32 prod; 258 u32 cons; 259 u32 buf_size; 260 u32 doorbell_qpn; 261 u8 *buf; 262 u16 poll_cnt; 263 int blocked; 264 struct mlx4_en_tx_info *tx_info; 265 u8 queue_index; 266 cpuset_t affinity_mask; 267 struct buf_ring *br; 268 u32 last_nr_txbb; 269 struct mlx4_qp qp; 270 struct mlx4_qp_context context; 271 int qpn; 272 enum mlx4_qp_state qp_state; 273 struct mlx4_srq dummy; 274 unsigned long bytes; 275 unsigned long packets; 276 unsigned long tx_csum; 277 unsigned long queue_stopped; 278 unsigned long oversized_packets; 279 unsigned long wake_queue; 280 struct mlx4_bf bf; 281 bool bf_enabled; 282 int hwtstamp_tx_type; 283 spinlock_t comp_lock; 284 int inline_thold; 285 u64 watchdog_time; 286}; 287 288struct mlx4_en_rx_desc { 289 /* actual number of entries depends on rx ring stride */ 290 struct mlx4_wqe_data_seg data[0]; 291}; 292 293struct mlx4_en_rx_mbuf { 294 bus_dmamap_t dma_map; 295 struct mbuf *mbuf; 296}; 297 298struct mlx4_en_rx_spare { 299 bus_dmamap_t dma_map; 300 struct mbuf *mbuf; 301 u64 paddr_be; 302}; 303 304struct mlx4_en_rx_ring { 305 struct mlx4_hwq_resources wqres; 306 bus_dma_tag_t dma_tag; 307 struct mlx4_en_rx_spare spare; 308 u32 size ; /* number of Rx descs*/ 309 u32 actual_size; 310 u32 size_mask; 311 u16 stride; 312 u16 log_stride; 313 u16 cqn; /* index of port CQ associated with this ring */ 314 u32 prod; 315 u32 cons; 316 u32 buf_size; 317 u8 fcs_del; 318 u16 rx_alloc_order; 319 u32 rx_alloc_size; 320 u32 rx_buf_size; 321 u32 rx_mb_size; 322 int qpn; 323 u8 *buf; 324 struct mlx4_en_rx_mbuf *mbuf; 325 unsigned long errors; 326 unsigned long bytes; 327 unsigned long packets; 328#ifdef LL_EXTENDED_STATS 329 unsigned long yields; 330 unsigned long misses; 331 unsigned long cleaned; 332#endif 333 unsigned long csum_ok; 334 unsigned long csum_none; 335 int hwtstamp_rx_filter; 336 int numa_node; 337 struct lro_ctrl lro; 338}; 339 340static inline int mlx4_en_can_lro(__be16 status) 341{ 342 const __be16 status_all = cpu_to_be16( 343 MLX4_CQE_STATUS_IPV4 | 344 MLX4_CQE_STATUS_IPV4F | 345 MLX4_CQE_STATUS_IPV6 | 346 MLX4_CQE_STATUS_IPV4OPT | 347 MLX4_CQE_STATUS_TCP | 348 MLX4_CQE_STATUS_UDP | 349 MLX4_CQE_STATUS_IPOK); 350 const __be16 status_ipv4_ipok_tcp = cpu_to_be16( 351 MLX4_CQE_STATUS_IPV4 | 352 MLX4_CQE_STATUS_IPOK | 353 MLX4_CQE_STATUS_TCP); 354 const __be16 status_ipv6_ipok_tcp = cpu_to_be16( 355 MLX4_CQE_STATUS_IPV6 | 356 MLX4_CQE_STATUS_IPOK | 357 MLX4_CQE_STATUS_TCP); 358 359 status &= status_all; 360 return (status == status_ipv4_ipok_tcp || 361 status == status_ipv6_ipok_tcp); 362} 363 364struct mlx4_en_cq { 365 struct mlx4_cq mcq; 366 struct mlx4_hwq_resources wqres; 367 int ring; 368 spinlock_t lock; 369 struct net_device *dev; 370 /* Per-core Tx cq processing support */ 371 struct timer_list timer; 372 int size; 373 int buf_size; 374 unsigned vector; 375 enum cq_type is_tx; 376 u16 moder_time; 377 u16 moder_cnt; 378 struct mlx4_cqe *buf; 379 struct task cq_task; 380 struct taskqueue *tq; 381#define MLX4_EN_OPCODE_ERROR 0x1e 382 u32 tot_rx; 383 u32 tot_tx; 384 u32 curr_poll_rx_cpu_id; 385 386#ifdef CONFIG_NET_RX_BUSY_POLL 387 unsigned int state; 388#define MLX4_EN_CQ_STATEIDLE 0 389#define MLX4_EN_CQ_STATENAPI 1 /* NAPI owns this CQ */ 390#define MLX4_EN_CQ_STATEPOLL 2 /* poll owns this CQ */ 391#define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATENAPI | MLX4_EN_CQ_STATEPOLL) 392#define MLX4_EN_CQ_STATENAPI_YIELD 4 /* NAPI yielded this CQ */ 393#define MLX4_EN_CQ_STATEPOLL_YIELD 8 /* poll yielded this CQ */ 394#define CQ_YIELD (MLX4_EN_CQ_STATENAPI_YIELD | MLX4_EN_CQ_STATEPOLL_YIELD) 395#define CQ_USER_PEND (MLX4_EN_CQ_STATEPOLL | MLX4_EN_CQ_STATEPOLL_YIELD) 396 spinlock_t poll_lock; /* protects from LLS/napi conflicts */ 397#endif /* CONFIG_NET_RX_BUSY_POLL */ 398}; 399 400struct mlx4_en_port_profile { 401 u32 flags; 402 u32 tx_ring_num; 403 u32 rx_ring_num; 404 u32 tx_ring_size; 405 u32 rx_ring_size; 406 u8 rx_pause; 407 u8 rx_ppp; 408 u8 tx_pause; 409 u8 tx_ppp; 410 int rss_rings; 411}; 412 413struct mlx4_en_profile { 414 int rss_xor; 415 int udp_rss; 416 u8 rss_mask; 417 u32 active_ports; 418 u32 small_pkt_int; 419 u8 no_reset; 420 u8 num_tx_rings_p_up; 421 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 422}; 423 424struct mlx4_en_dev { 425 struct mlx4_dev *dev; 426 struct pci_dev *pdev; 427 struct mutex state_lock; 428 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 429 u32 port_cnt; 430 bool device_up; 431 struct mlx4_en_profile profile; 432 u32 LSO_support; 433 struct workqueue_struct *workqueue; 434 struct device *dma_device; 435 void __iomem *uar_map; 436 struct mlx4_uar priv_uar; 437 struct mlx4_mr mr; 438 u32 priv_pdn; 439 spinlock_t uar_lock; 440 u8 mac_removed[MLX4_MAX_PORTS + 1]; 441 unsigned long last_overflow_check; 442 unsigned long overflow_period; 443}; 444 445 446struct mlx4_en_rss_map { 447 int base_qpn; 448 struct mlx4_qp qps[MAX_RX_RINGS]; 449 enum mlx4_qp_state state[MAX_RX_RINGS]; 450 struct mlx4_qp indir_qp; 451 enum mlx4_qp_state indir_state; 452}; 453 454struct mlx4_en_port_state { 455 int link_state; 456 int link_speed; 457 int transciver; 458 int autoneg; 459}; 460 461enum mlx4_en_mclist_act { 462 MCLIST_NONE, 463 MCLIST_REM, 464 MCLIST_ADD, 465}; 466 467struct mlx4_en_mc_list { 468 struct list_head list; 469 enum mlx4_en_mclist_act action; 470 u8 addr[ETH_ALEN]; 471 u64 reg_id; 472}; 473 474#ifdef CONFIG_MLX4_EN_DCB 475/* Minimal TC BW - setting to 0 will block traffic */ 476#define MLX4_EN_BW_MIN 1 477#define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 478 479#define MLX4_EN_TC_ETS 7 480 481#endif 482 483 484enum { 485 MLX4_EN_FLAG_PROMISC = (1 << 0), 486 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 487 /* whether we need to enable hardware loopback by putting dmac 488 * in Tx WQE 489 */ 490 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 491 /* whether we need to drop packets that hardware loopback-ed */ 492 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 493 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 494#ifdef CONFIG_MLX4_EN_DCB 495 MLX4_EN_FLAG_DCB_ENABLED = (1 << 5) 496#endif 497}; 498 499#define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 500#define MLX4_EN_MAC_HASH_IDX 5 501 502struct en_port { 503 struct kobject kobj; 504 struct mlx4_dev *dev; 505 u8 port_num; 506 u8 vport_num; 507}; 508 509struct mlx4_en_priv { 510 struct mlx4_en_dev *mdev; 511 struct mlx4_en_port_profile *prof; 512 struct net_device *dev; 513 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 514 struct mlx4_en_port_state port_state; 515 spinlock_t stats_lock; 516 /* To allow rules removal while port is going down */ 517 struct list_head ethtool_list; 518 519 unsigned long last_moder_packets[MAX_RX_RINGS]; 520 unsigned long last_moder_tx_packets; 521 unsigned long last_moder_bytes[MAX_RX_RINGS]; 522 unsigned long last_moder_jiffies; 523 int last_moder_time[MAX_RX_RINGS]; 524 u16 rx_usecs; 525 u16 rx_frames; 526 u16 tx_usecs; 527 u16 tx_frames; 528 u32 pkt_rate_low; 529 u32 rx_usecs_low; 530 u32 pkt_rate_high; 531 u32 rx_usecs_high; 532 u32 sample_interval; 533 u32 adaptive_rx_coal; 534 u32 msg_enable; 535 u32 loopback_ok; 536 u32 validate_loopback; 537 538 struct mlx4_hwq_resources res; 539 int link_state; 540 int last_link_state; 541 bool port_up; 542 int port; 543 int registered; 544 int allocated; 545 int stride; 546 unsigned char current_mac[ETH_ALEN + 2]; 547 u64 mac; 548 int mac_index; 549 unsigned max_mtu; 550 int base_qpn; 551 int cqe_factor; 552 553 struct mlx4_en_rss_map rss_map; 554 u32 flags; 555 u8 num_tx_rings_p_up; 556 u32 tx_ring_num; 557 u32 rx_ring_num; 558 u32 rx_mb_size; 559 u16 rx_alloc_order; 560 u32 rx_alloc_size; 561 u32 rx_buf_size; 562 563 struct mlx4_en_tx_ring **tx_ring; 564 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 565 struct mlx4_en_cq **tx_cq; 566 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 567 struct mlx4_qp drop_qp; 568 struct work_struct rx_mode_task; 569 struct work_struct watchdog_task; 570 struct work_struct linkstate_task; 571 struct delayed_work stats_task; 572 struct delayed_work service_task; 573 struct mlx4_en_perf_stats pstats; 574 struct mlx4_en_pkt_stats pkstats; 575 struct mlx4_en_pkt_stats pkstats_last; 576 struct mlx4_en_flow_stats flowstats[MLX4_NUM_PRIORITIES]; 577 struct mlx4_en_port_stats port_stats; 578 struct mlx4_en_vport_stats vport_stats; 579 struct mlx4_en_vf_stats vf_stats; 580 DECLARE_BITMAP(stats_bitmap, NUM_ALL_STATS); 581 struct list_head mc_list; 582 struct list_head curr_list; 583 u64 broadcast_id; 584 struct mlx4_en_stat_out_mbox hw_stats; 585 int vids[128]; 586 bool wol; 587 struct device *ddev; 588 struct dentry *dev_root; 589 u32 counter_index; 590 eventhandler_tag vlan_attach; 591 eventhandler_tag vlan_detach; 592 struct callout watchdog_timer; 593 struct ifmedia media; 594 volatile int blocked; 595 struct sysctl_oid *sysctl; 596 struct sysctl_ctx_list conf_ctx; 597 struct sysctl_ctx_list stat_ctx; 598#define MLX4_EN_MAC_HASH_IDX 5 599 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 600 601#ifdef CONFIG_MLX4_EN_DCB 602 struct ieee_ets ets; 603 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 604 u8 dcbx_cap; 605#endif 606#ifdef CONFIG_RFS_ACCEL 607 spinlock_t filters_lock; 608 int last_filter_id; 609 struct list_head filters; 610 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 611#endif 612 struct en_port *vf_ports[MLX4_MAX_NUM_VF]; 613 unsigned long last_ifq_jiffies; 614 u64 if_counters_rx_errors; 615 u64 if_counters_rx_no_buffer; 616}; 617 618enum mlx4_en_wol { 619 MLX4_EN_WOL_MAGIC = (1ULL << 61), 620 MLX4_EN_WOL_ENABLED = (1ULL << 62), 621}; 622 623struct mlx4_mac_entry { 624 struct hlist_node hlist; 625 unsigned char mac[ETH_ALEN + 2]; 626 u64 reg_id; 627}; 628 629#ifdef CONFIG_NET_RX_BUSY_POLL 630static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 631{ 632 spin_lock_init(&cq->poll_lock); 633 cq->state = MLX4_EN_CQ_STATEIDLE; 634} 635 636/* called from the device poll rutine to get ownership of a cq */ 637static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 638{ 639 int rc = true; 640 spin_lock(&cq->poll_lock); 641 if (cq->state & MLX4_CQ_LOCKED) { 642 WARN_ON(cq->state & MLX4_EN_CQ_STATENAPI); 643 cq->state |= MLX4_EN_CQ_STATENAPI_YIELD; 644 rc = false; 645 } else 646 /* we don't care if someone yielded */ 647 cq->state = MLX4_EN_CQ_STATENAPI; 648 spin_unlock(&cq->poll_lock); 649 return rc; 650} 651 652/* returns true is someone tried to get the cq while napi had it */ 653static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 654{ 655 int rc = false; 656 spin_lock(&cq->poll_lock); 657 WARN_ON(cq->state & (MLX4_EN_CQ_STATEPOLL | 658 MLX4_EN_CQ_STATENAPI_YIELD)); 659 660 if (cq->state & MLX4_EN_CQ_STATEPOLL_YIELD) 661 rc = true; 662 cq->state = MLX4_EN_CQ_STATEIDLE; 663 spin_unlock(&cq->poll_lock); 664 return rc; 665} 666 667/* called from mlx4_en_low_latency_poll() */ 668static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 669{ 670 int rc = true; 671 spin_lock_bh(&cq->poll_lock); 672 if ((cq->state & MLX4_CQ_LOCKED)) { 673 struct net_device *dev = cq->dev; 674 struct mlx4_en_priv *priv = netdev_priv(dev); 675 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; 676 677 cq->state |= MLX4_EN_CQ_STATEPOLL_YIELD; 678 rc = false; 679#ifdef LL_EXTENDED_STATS 680 rx_ring->yields++; 681#endif 682 } else 683 /* preserve yield marks */ 684 cq->state |= MLX4_EN_CQ_STATEPOLL; 685 spin_unlock_bh(&cq->poll_lock); 686 return rc; 687} 688 689/* returns true if someone tried to get the cq while it was locked */ 690static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 691{ 692 int rc = false; 693 spin_lock_bh(&cq->poll_lock); 694 WARN_ON(cq->state & (MLX4_EN_CQ_STATENAPI)); 695 696 if (cq->state & MLX4_EN_CQ_STATEPOLL_YIELD) 697 rc = true; 698 cq->state = MLX4_EN_CQ_STATEIDLE; 699 spin_unlock_bh(&cq->poll_lock); 700 return rc; 701} 702 703/* true if a socket is polling, even if it did not get the lock */ 704static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq) 705{ 706 WARN_ON(!(cq->state & MLX4_CQ_LOCKED)); 707 return cq->state & CQ_USER_PEND; 708} 709#else 710static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 711{ 712} 713 714static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 715{ 716 return true; 717} 718 719static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 720{ 721 return false; 722} 723 724static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 725{ 726 return false; 727} 728 729static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 730{ 731 return false; 732} 733 734static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq) 735{ 736 return false; 737} 738#endif /* CONFIG_NET_RX_BUSY_POLL */ 739 740#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 741 742void mlx4_en_destroy_netdev(struct net_device *dev); 743int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 744 struct mlx4_en_port_profile *prof); 745 746int mlx4_en_start_port(struct net_device *dev); 747void mlx4_en_stop_port(struct net_device *dev); 748 749void mlx4_en_free_resources(struct mlx4_en_priv *priv); 750int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 751 752int mlx4_en_pre_config(struct mlx4_en_priv *priv); 753int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 754 int entries, int ring, enum cq_type mode, int node); 755void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 756int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 757 int cq_idx); 758void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 759int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 760int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 761 762void mlx4_en_tx_irq(struct mlx4_cq *mcq); 763u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb); 764 765int mlx4_en_transmit(struct ifnet *dev, struct mbuf *m); 766int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 767 struct mlx4_en_tx_ring **pring, 768 u32 size, u16 stride, int node, int queue_idx); 769void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 770 struct mlx4_en_tx_ring **pring); 771int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 772 struct mlx4_en_tx_ring *ring, 773 int cq, int user_prio); 774void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 775 struct mlx4_en_tx_ring *ring); 776void mlx4_en_qflush(struct ifnet *dev); 777 778int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 779 struct mlx4_en_rx_ring **pring, 780 u32 size, int node); 781void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 782 struct mlx4_en_rx_ring **pring, 783 u32 size, u16 stride); 784void mlx4_en_tx_que(void *context, int pending); 785void mlx4_en_rx_que(void *context, int pending); 786int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 787void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 788 struct mlx4_en_rx_ring *ring); 789int mlx4_en_process_rx_cq(struct net_device *dev, 790 struct mlx4_en_cq *cq, 791 int budget); 792void mlx4_en_poll_tx_cq(unsigned long data); 793void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 794 int is_tx, int rss, int qpn, int cqn, int user_prio, 795 struct mlx4_qp_context *context); 796void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 797int mlx4_en_map_buffer(struct mlx4_buf *buf); 798void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 799void mlx4_en_calc_rx_buf(struct net_device *dev); 800 801int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 802void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 803int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 804void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 805int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 806void mlx4_en_rx_irq(struct mlx4_cq *mcq); 807 808int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 809int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 810 811int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 812int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 813int mlx4_en_get_vport_stats(struct mlx4_en_dev *mdev, u8 port); 814void mlx4_en_create_debug_files(struct mlx4_en_priv *priv); 815void mlx4_en_delete_debug_files(struct mlx4_en_priv *priv); 816int mlx4_en_register_debugfs(void); 817void mlx4_en_unregister_debugfs(void); 818 819#ifdef CONFIG_MLX4_EN_DCB 820extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 821extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 822#endif 823 824int mlx4_en_setup_tc(struct net_device *dev, u8 up); 825 826#ifdef CONFIG_RFS_ACCEL 827void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv, 828 struct mlx4_en_rx_ring *rx_ring); 829#endif 830 831#define MLX4_EN_NUM_SELF_TEST 5 832void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 833void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 834 835/* 836 * Functions for time stamping 837 */ 838#define SKBTX_HW_TSTAMP (1 << 0) 839#define SKBTX_IN_PROGRESS (1 << 2) 840 841u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 842 843/* Functions for caching and restoring statistics */ 844int mlx4_en_get_sset_count(struct net_device *dev, int sset); 845void mlx4_en_restore_ethtool_stats(struct mlx4_en_priv *priv, 846 u64 *data); 847 848/* 849 * Globals 850 */ 851extern const struct ethtool_ops mlx4_en_ethtool_ops; 852 853/* 854 * Defines for link speed - needed by selftest 855 */ 856#define MLX4_EN_LINK_SPEED_1G 1000 857#define MLX4_EN_LINK_SPEED_10G 10000 858#define MLX4_EN_LINK_SPEED_40G 40000 859 860enum { 861 NETIF_MSG_DRV = 0x0001, 862 NETIF_MSG_PROBE = 0x0002, 863 NETIF_MSG_LINK = 0x0004, 864 NETIF_MSG_TIMER = 0x0008, 865 NETIF_MSG_IFDOWN = 0x0010, 866 NETIF_MSG_IFUP = 0x0020, 867 NETIF_MSG_RX_ERR = 0x0040, 868 NETIF_MSG_TX_ERR = 0x0080, 869 NETIF_MSG_TX_QUEUED = 0x0100, 870 NETIF_MSG_INTR = 0x0200, 871 NETIF_MSG_TX_DONE = 0x0400, 872 NETIF_MSG_RX_STATUS = 0x0800, 873 NETIF_MSG_PKTDATA = 0x1000, 874 NETIF_MSG_HW = 0x2000, 875 NETIF_MSG_WOL = 0x4000, 876}; 877 878 879/* 880 * printk / logging functions 881 */ 882 883#define en_print(level, priv, format, arg...) \ 884 { \ 885 if ((priv)->registered) \ 886 printk(level "%s: %s: " format, DRV_NAME, \ 887 (priv->dev)->if_xname, ## arg); \ 888 else \ 889 printk(level "%s: %s: Port %d: " format, \ 890 DRV_NAME, dev_name(&priv->mdev->pdev->dev), \ 891 (priv)->port, ## arg); \ 892 } 893 894 895#define en_dbg(mlevel, priv, format, arg...) \ 896do { \ 897 if (NETIF_MSG_##mlevel & priv->msg_enable) \ 898 en_print(KERN_DEBUG, priv, format, ##arg); \ 899} while (0) 900#define en_warn(priv, format, arg...) \ 901 en_print(KERN_WARNING, priv, format, ##arg) 902#define en_err(priv, format, arg...) \ 903 en_print(KERN_ERR, priv, format, ##arg) 904#define en_info(priv, format, arg...) \ 905 en_print(KERN_INFO, priv, format, ## arg) 906 907#define mlx4_err(mdev, format, arg...) \ 908 pr_err("%s %s: " format, DRV_NAME, \ 909 dev_name(&mdev->pdev->dev), ##arg) 910#define mlx4_info(mdev, format, arg...) \ 911 pr_info("%s %s: " format, DRV_NAME, \ 912 dev_name(&mdev->pdev->dev), ##arg) 913#define mlx4_warn(mdev, format, arg...) \ 914 pr_warning("%s %s: " format, DRV_NAME, \ 915 dev_name(&mdev->pdev->dev), ##arg) 916 917#endif 918