mlx4_en.h revision 272060
1/* 2 * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34#ifndef _MLX4_EN_H_ 35#define _MLX4_EN_H_ 36 37#include <linux/bitops.h> 38#include <linux/compiler.h> 39#include <linux/list.h> 40#include <linux/mutex.h> 41#include <linux/kobject.h> 42#include <linux/netdevice.h> 43#include <linux/if_vlan.h> 44#include <linux/if_ether.h> 45#ifdef CONFIG_MLX4_EN_DCB 46#include <linux/dcbnl.h> 47#endif 48 49#include <linux/mlx4/device.h> 50#include <linux/mlx4/qp.h> 51#include <linux/mlx4/cq.h> 52#include <linux/mlx4/srq.h> 53#include <linux/mlx4/doorbell.h> 54#include <linux/mlx4/cmd.h> 55 56#include <netinet/tcp_lro.h> 57 58#include "en_port.h" 59#include "mlx4_stats.h" 60 61#define DRV_NAME "mlx4_en" 62#define DRV_VERSION "2.1" 63#define DRV_RELDATE __DATE__ 64 65#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 66 67/* 68 * Device constants 69 */ 70 71 72#define MLX4_EN_PAGE_SHIFT 12 73#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 74#define DEF_RX_RINGS 16 75#define MAX_RX_RINGS 128 76#define MIN_RX_RINGS 4 77#define TXBB_SIZE 64 78#define HEADROOM (2048 / TXBB_SIZE + 1) 79#define STAMP_STRIDE 64 80#define STAMP_DWORDS (STAMP_STRIDE / 4) 81#define STAMP_SHIFT 31 82#define STAMP_VAL 0x7fffffff 83#define STATS_DELAY (HZ / 4) 84#define SERVICE_TASK_DELAY (HZ / 4) 85#define MAX_NUM_OF_FS_RULES 256 86 87#define MLX4_EN_FILTER_HASH_SHIFT 4 88#define MLX4_EN_FILTER_EXPIRY_QUOTA 60 89 90#ifdef CONFIG_NET_RX_BUSY_POLL 91#define LL_EXTENDED_STATS 92#endif 93 94/* vlan valid range */ 95#define VLAN_MIN_VALUE 1 96#define VLAN_MAX_VALUE 4094 97 98/* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 99#define MAX_DESC_SIZE 512 100#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 101 102/* 103 * OS related constants and tunables 104 */ 105 106#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 107 108#define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(PAGE_SIZE) 109#define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE) 110 111enum mlx4_en_alloc_type { 112 MLX4_EN_ALLOC_NEW = 0, 113 MLX4_EN_ALLOC_REPLACEMENT = 1, 114}; 115 116/* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 117 * and 4K allocations) */ 118#if MJUMPAGESIZE == 4096 119enum { 120 FRAG_SZ0 = MCLBYTES, 121 FRAG_SZ1 = MJUMPAGESIZE, 122 FRAG_SZ2 = MJUMPAGESIZE, 123}; 124#define MLX4_EN_MAX_RX_FRAGS 3 125#elif MJUMPAGESIZE == 8192 126enum { 127 FRAG_SZ0 = MCLBYTES, 128 FRAG_SZ1 = MJUMPAGESIZE, 129}; 130#define MLX4_EN_MAX_RX_FRAGS 2 131#elif MJUMPAGESIZE == 8192 132#else 133#error "Unknown PAGE_SIZE" 134#endif 135 136/* Maximum ring sizes */ 137#define MLX4_EN_DEF_TX_QUEUE_SIZE 4096 138 139/* Minimum packet number till arming the CQ */ 140#define MLX4_EN_MIN_RX_ARM 2048 141#define MLX4_EN_MIN_TX_ARM 2048 142 143/* Maximum ring sizes */ 144#define MLX4_EN_MAX_TX_SIZE 8192 145#define MLX4_EN_MAX_RX_SIZE 8192 146 147/* Minimum ring sizes */ 148#define MLX4_EN_MIN_RX_SIZE (4096 / TXBB_SIZE) 149#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 150 151#define MLX4_EN_SMALL_PKT_SIZE 64 152 153#define MLX4_EN_MAX_TX_RING_P_UP 32 154#define MLX4_EN_NUM_UP 1 155 156#define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 157 (MLX4_EN_NUM_UP + 1)) 158 159#define MLX4_EN_DEF_TX_RING_SIZE 1024 160#define MLX4_EN_DEF_RX_RING_SIZE 1024 161 162/* Target number of bytes to coalesce with interrupt moderation */ 163#define MLX4_EN_RX_COAL_TARGET 0x20000 164#define MLX4_EN_RX_COAL_TIME 0x10 165 166#define MLX4_EN_TX_COAL_PKTS 64 167#define MLX4_EN_TX_COAL_TIME 64 168 169#define MLX4_EN_RX_RATE_LOW 400000 170#define MLX4_EN_RX_COAL_TIME_LOW 0 171#define MLX4_EN_RX_RATE_HIGH 450000 172#define MLX4_EN_RX_COAL_TIME_HIGH 128 173#define MLX4_EN_RX_SIZE_THRESH 1024 174#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 175#define MLX4_EN_SAMPLE_INTERVAL 0 176#define MLX4_EN_AVG_PKT_SMALL 256 177 178#define MLX4_EN_AUTO_CONF 0xffff 179 180#define MLX4_EN_DEF_RX_PAUSE 1 181#define MLX4_EN_DEF_TX_PAUSE 1 182 183/* Interval between successive polls in the Tx routine when polling is used 184 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 185#define MLX4_EN_TX_POLL_MODER 16 186#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 187 188#define MLX4_EN_64_ALIGN (64 - NET_SKB_PAD) 189#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 190#define HEADER_COPY_SIZE (128) 191#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETHER_HDR_LEN) 192 193#define MLX4_EN_MIN_MTU 46 194#define ETH_BCAST 0xffffffffffffULL 195 196#define MLX4_EN_LOOPBACK_RETRIES 5 197#define MLX4_EN_LOOPBACK_TIMEOUT 100 198 199#ifdef MLX4_EN_PERF_STAT 200/* Number of samples to 'average' */ 201#define AVG_SIZE 128 202#define AVG_FACTOR 1024 203 204#define INC_PERF_COUNTER(cnt) (++(cnt)) 205#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 206#define AVG_PERF_COUNTER(cnt, sample) \ 207 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 208#define GET_PERF_COUNTER(cnt) (cnt) 209#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 210 211#else 212 213#define INC_PERF_COUNTER(cnt) do {} while (0) 214#define ADD_PERF_COUNTER(cnt, add) do {} while (0) 215#define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 216#define GET_PERF_COUNTER(cnt) (0) 217#define GET_AVG_PERF_COUNTER(cnt) (0) 218#endif /* MLX4_EN_PERF_STAT */ 219 220/* 221 * Configurables 222 */ 223 224enum cq_type { 225 RX = 0, 226 TX = 1, 227}; 228 229 230/* 231 * Useful macros 232 */ 233#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 234#define XNOR(x, y) (!(x) == !(y)) 235#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0) 236 237struct mlx4_en_tx_info { 238 struct mbuf *mb; 239 u32 nr_txbb; 240 u32 nr_bytes; 241 u8 linear; 242 u8 nr_segs; 243 u8 data_offset; 244 u8 inl; 245#if 0 246 u8 ts_requested; 247#endif 248}; 249 250 251#define MLX4_EN_BIT_DESC_OWN 0x80000000 252#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 253#define MLX4_EN_MEMTYPE_PAD 0x100 254#define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 255 256 257struct mlx4_en_tx_desc { 258 struct mlx4_wqe_ctrl_seg ctrl; 259 union { 260 struct mlx4_wqe_data_seg data; /* at least one data segment */ 261 struct mlx4_wqe_lso_seg lso; 262 struct mlx4_wqe_inline_seg inl; 263 }; 264}; 265 266#define MLX4_EN_USE_SRQ 0x01000000 267 268#define MLX4_EN_TX_BUDGET 64*4 //Compensate for no NAPI in freeBSD - might need some fine tunning in the future. 269#define MLX4_EN_RX_BUDGET 64 270 271#define MLX4_EN_CX3_LOW_ID 0x1000 272#define MLX4_EN_CX3_HIGH_ID 0x1005 273 274struct mlx4_en_tx_ring { 275 spinlock_t tx_lock; 276 struct mlx4_hwq_resources wqres; 277 u32 size ; /* number of TXBBs */ 278 u32 size_mask; 279 u16 stride; 280 u16 cqn; /* index of port CQ associated with this ring */ 281 u32 prod; 282 u32 cons; 283 u32 buf_size; 284 u32 doorbell_qpn; 285 void *buf; 286 u16 poll_cnt; 287 int blocked; 288 struct mlx4_en_tx_info *tx_info; 289 u8 *bounce_buf; 290 u8 queue_index; 291 cpuset_t affinity_mask; 292 struct buf_ring *br; 293 u32 last_nr_txbb; 294 struct mlx4_qp qp; 295 struct mlx4_qp_context context; 296 int qpn; 297 enum mlx4_qp_state qp_state; 298 struct mlx4_srq dummy; 299 unsigned long bytes; 300 unsigned long packets; 301 unsigned long tx_csum; 302 unsigned long queue_stopped; 303 unsigned long wake_queue; 304 struct mlx4_bf bf; 305 bool bf_enabled; 306 struct netdev_queue *tx_queue; 307 int hwtstamp_tx_type; 308 spinlock_t comp_lock; 309 int full_size; 310 int inline_thold; 311 u64 watchdog_time; 312}; 313 314struct mlx4_en_rx_desc { 315 /* actual number of entries depends on rx ring stride */ 316 struct mlx4_wqe_data_seg data[0]; 317}; 318 319struct mlx4_en_rx_buf { 320 dma_addr_t dma; 321 struct page *page; 322 unsigned int page_offset; 323}; 324 325struct mlx4_en_rx_ring { 326 struct mlx4_hwq_resources wqres; 327 u32 size ; /* number of Rx descs*/ 328 u32 actual_size; 329 u32 size_mask; 330 u16 stride; 331 u16 log_stride; 332 u16 cqn; /* index of port CQ associated with this ring */ 333 u32 prod; 334 u32 cons; 335 u32 buf_size; 336 u8 fcs_del; 337 u16 rx_alloc_order; 338 u32 rx_alloc_size; 339 u32 rx_buf_size; 340 u32 rx_mb_size; 341 int qpn; 342 void *buf; 343 void *rx_info; 344 unsigned long errors; 345 unsigned long bytes; 346 unsigned long packets; 347#ifdef LL_EXTENDED_STATS 348 unsigned long yields; 349 unsigned long misses; 350 unsigned long cleaned; 351#endif 352 unsigned long csum_ok; 353 unsigned long csum_none; 354 int hwtstamp_rx_filter; 355 int numa_node; 356 struct lro_ctrl lro; 357}; 358 359static inline int mlx4_en_can_lro(__be16 status) 360{ 361 static __be16 status_all; 362 static __be16 status_ipv4_ipok_tcp; 363 static __be16 status_ipv6_ipok_tcp; 364 365 status_all = cpu_to_be16( 366 MLX4_CQE_STATUS_IPV4 | 367 MLX4_CQE_STATUS_IPV4F | 368 MLX4_CQE_STATUS_IPV6 | 369 MLX4_CQE_STATUS_IPV4OPT | 370 MLX4_CQE_STATUS_TCP | 371 MLX4_CQE_STATUS_UDP | 372 MLX4_CQE_STATUS_IPOK); 373 status_ipv4_ipok_tcp = cpu_to_be16( 374 MLX4_CQE_STATUS_IPV4 | 375 MLX4_CQE_STATUS_IPOK | 376 MLX4_CQE_STATUS_TCP); 377 status_ipv6_ipok_tcp = cpu_to_be16( 378 MLX4_CQE_STATUS_IPV6 | 379 MLX4_CQE_STATUS_IPOK | 380 MLX4_CQE_STATUS_TCP); 381 382 status &= status_all; 383 return (status == status_ipv4_ipok_tcp || 384 status == status_ipv6_ipok_tcp); 385} 386 387 388struct mlx4_en_cq { 389 struct mlx4_cq mcq; 390 struct mlx4_hwq_resources wqres; 391 int ring; 392 spinlock_t lock; 393 struct net_device *dev; 394 /* Per-core Tx cq processing support */ 395 struct timer_list timer; 396 int size; 397 int buf_size; 398 unsigned vector; 399 enum cq_type is_tx; 400 u16 moder_time; 401 u16 moder_cnt; 402 struct mlx4_cqe *buf; 403 struct task cq_task; 404 struct taskqueue *tq; 405#define MLX4_EN_OPCODE_ERROR 0x1e 406 u32 tot_rx; 407 u32 tot_tx; 408 409#ifdef CONFIG_NET_RX_BUSY_POLL 410 unsigned int state; 411#define MLX4_EN_CQ_STATEIDLE 0 412#define MLX4_EN_CQ_STATENAPI 1 /* NAPI owns this CQ */ 413#define MLX4_EN_CQ_STATEPOLL 2 /* poll owns this CQ */ 414#define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATENAPI | MLX4_EN_CQ_STATEPOLL) 415#define MLX4_EN_CQ_STATENAPI_YIELD 4 /* NAPI yielded this CQ */ 416#define MLX4_EN_CQ_STATEPOLL_YIELD 8 /* poll yielded this CQ */ 417#define CQ_YIELD (MLX4_EN_CQ_STATENAPI_YIELD | MLX4_EN_CQ_STATEPOLL_YIELD) 418#define CQ_USER_PEND (MLX4_EN_CQ_STATEPOLL | MLX4_EN_CQ_STATEPOLL_YIELD) 419 spinlock_t poll_lock; /* protects from LLS/napi conflicts */ 420#endif /* CONFIG_NET_RX_BUSY_POLL */ 421}; 422 423struct mlx4_en_port_profile { 424 u32 flags; 425 u32 tx_ring_num; 426 u32 rx_ring_num; 427 u32 tx_ring_size; 428 u32 rx_ring_size; 429 u8 rx_pause; 430 u8 rx_ppp; 431 u8 tx_pause; 432 u8 tx_ppp; 433 int rss_rings; 434}; 435 436struct mlx4_en_profile { 437 int rss_xor; 438 int udp_rss; 439 u8 rss_mask; 440 u32 active_ports; 441 u32 small_pkt_int; 442 u8 no_reset; 443 u8 num_tx_rings_p_up; 444 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 445}; 446 447struct mlx4_en_dev { 448 struct mlx4_dev *dev; 449 struct pci_dev *pdev; 450 struct mutex state_lock; 451 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 452 u32 port_cnt; 453 bool device_up; 454 struct mlx4_en_profile profile; 455 u32 LSO_support; 456 struct workqueue_struct *workqueue; 457 struct device *dma_device; 458 void __iomem *uar_map; 459 struct mlx4_uar priv_uar; 460 struct mlx4_mr mr; 461 u32 priv_pdn; 462 spinlock_t uar_lock; 463 u8 mac_removed[MLX4_MAX_PORTS + 1]; 464 unsigned long last_overflow_check; 465 unsigned long overflow_period; 466}; 467 468 469struct mlx4_en_rss_map { 470 int base_qpn; 471 struct mlx4_qp qps[MAX_RX_RINGS]; 472 enum mlx4_qp_state state[MAX_RX_RINGS]; 473 struct mlx4_qp indir_qp; 474 enum mlx4_qp_state indir_state; 475}; 476 477struct mlx4_en_port_state { 478 int link_state; 479 int link_speed; 480 int transciver; 481 int autoneg; 482}; 483 484enum mlx4_en_mclist_act { 485 MCLIST_NONE, 486 MCLIST_REM, 487 MCLIST_ADD, 488}; 489 490struct mlx4_en_mc_list { 491 struct list_head list; 492 enum mlx4_en_mclist_act action; 493 u8 addr[ETH_ALEN]; 494 u64 reg_id; 495}; 496 497#ifdef CONFIG_MLX4_EN_DCB 498/* Minimal TC BW - setting to 0 will block traffic */ 499#define MLX4_EN_BW_MIN 1 500#define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 501 502#define MLX4_EN_TC_ETS 7 503 504#endif 505 506 507enum { 508 MLX4_EN_FLAG_PROMISC = (1 << 0), 509 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 510 /* whether we need to enable hardware loopback by putting dmac 511 * in Tx WQE 512 */ 513 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 514 /* whether we need to drop packets that hardware loopback-ed */ 515 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 516 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 517#ifdef CONFIG_MLX4_EN_DCB 518 MLX4_EN_FLAG_DCB_ENABLED = (1 << 5) 519#endif 520}; 521 522#define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 523#define MLX4_EN_MAC_HASH_IDX 5 524 525struct en_port { 526 struct kobject kobj; 527 struct mlx4_dev *dev; 528 u8 port_num; 529 u8 vport_num; 530}; 531 532struct mlx4_en_frag_info { 533 u16 frag_size; 534 u16 frag_prefix_size; 535}; 536 537 538struct mlx4_en_priv { 539 struct mlx4_en_dev *mdev; 540 struct mlx4_en_port_profile *prof; 541 struct net_device *dev; 542 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 543 struct mlx4_en_port_state port_state; 544 spinlock_t stats_lock; 545 /* To allow rules removal while port is going down */ 546 struct list_head ethtool_list; 547 548 unsigned long last_moder_packets[MAX_RX_RINGS]; 549 unsigned long last_moder_tx_packets; 550 unsigned long last_moder_bytes[MAX_RX_RINGS]; 551 unsigned long last_moder_jiffies; 552 int last_moder_time[MAX_RX_RINGS]; 553 u16 rx_usecs; 554 u16 rx_frames; 555 u16 tx_usecs; 556 u16 tx_frames; 557 u32 pkt_rate_low; 558 u16 rx_usecs_low; 559 u32 pkt_rate_high; 560 u16 rx_usecs_high; 561 u16 sample_interval; 562 u16 adaptive_rx_coal; 563 u32 msg_enable; 564 u32 loopback_ok; 565 u32 validate_loopback; 566 567 struct mlx4_hwq_resources res; 568 int link_state; 569 int last_link_state; 570 bool port_up; 571 int port; 572 int registered; 573 int allocated; 574 int stride; 575 unsigned char current_mac[ETH_ALEN + 2]; 576 u64 mac; 577 int mac_index; 578 unsigned max_mtu; 579 int base_qpn; 580 int cqe_factor; 581 582 struct mlx4_en_rss_map rss_map; 583 __be32 ctrl_flags; 584 u32 flags; 585 u8 num_tx_rings_p_up; 586 u32 tx_ring_num; 587 u32 rx_ring_num; 588 u32 rx_mb_size; 589 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 590 u16 rx_alloc_order; 591 u32 rx_alloc_size; 592 u32 rx_buf_size; 593 u16 num_frags; 594 u16 log_rx_info; 595 596 struct mlx4_en_tx_ring **tx_ring; 597 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 598 struct mlx4_en_cq **tx_cq; 599 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 600 struct mlx4_qp drop_qp; 601 struct work_struct rx_mode_task; 602 struct work_struct watchdog_task; 603 struct work_struct linkstate_task; 604 struct delayed_work stats_task; 605 struct delayed_work service_task; 606 struct mlx4_en_perf_stats pstats; 607 struct mlx4_en_pkt_stats pkstats; 608 struct mlx4_en_pkt_stats pkstats_last; 609 struct mlx4_en_flow_stats flowstats[MLX4_NUM_PRIORITIES]; 610 struct mlx4_en_port_stats port_stats; 611 struct mlx4_en_vport_stats vport_stats; 612 struct mlx4_en_vf_stats vf_stats; 613 DECLARE_BITMAP(stats_bitmap, NUM_ALL_STATS); 614 struct list_head mc_list; 615 struct list_head curr_list; 616 u64 broadcast_id; 617 struct mlx4_en_stat_out_mbox hw_stats; 618 int vids[128]; 619 bool wol; 620 struct device *ddev; 621 struct dentry *dev_root; 622 u32 counter_index; 623 eventhandler_tag vlan_attach; 624 eventhandler_tag vlan_detach; 625 struct callout watchdog_timer; 626 struct ifmedia media; 627 volatile int blocked; 628 struct sysctl_oid *sysctl; 629 struct sysctl_ctx_list conf_ctx; 630 struct sysctl_ctx_list stat_ctx; 631#define MLX4_EN_MAC_HASH_IDX 5 632 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 633 634#ifdef CONFIG_MLX4_EN_DCB 635 struct ieee_ets ets; 636 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 637 u8 dcbx_cap; 638#endif 639#ifdef CONFIG_RFS_ACCEL 640 spinlock_t filters_lock; 641 int last_filter_id; 642 struct list_head filters; 643 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 644#endif 645 struct en_port *vf_ports[MLX4_MAX_NUM_VF]; 646 unsigned long last_ifq_jiffies; 647 u64 if_counters_rx_errors; 648 u64 if_counters_rx_no_buffer; 649 650}; 651 652enum mlx4_en_wol { 653 MLX4_EN_WOL_MAGIC = (1ULL << 61), 654 MLX4_EN_WOL_ENABLED = (1ULL << 62), 655}; 656 657struct mlx4_mac_entry { 658 struct hlist_node hlist; 659 unsigned char mac[ETH_ALEN + 2]; 660 u64 reg_id; 661}; 662 663#ifdef CONFIG_NET_RX_BUSY_POLL 664static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 665{ 666 spin_lock_init(&cq->poll_lock); 667 cq->state = MLX4_EN_CQ_STATEIDLE; 668} 669 670/* called from the device poll rutine to get ownership of a cq */ 671static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 672{ 673 int rc = true; 674 spin_lock(&cq->poll_lock); 675 if (cq->state & MLX4_CQ_LOCKED) { 676 WARN_ON(cq->state & MLX4_EN_CQ_STATENAPI); 677 cq->state |= MLX4_EN_CQ_STATENAPI_YIELD; 678 rc = false; 679 } else 680 /* we don't care if someone yielded */ 681 cq->state = MLX4_EN_CQ_STATENAPI; 682 spin_unlock(&cq->poll_lock); 683 return rc; 684} 685 686/* returns true is someone tried to get the cq while napi had it */ 687static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 688{ 689 int rc = false; 690 spin_lock(&cq->poll_lock); 691 WARN_ON(cq->state & (MLX4_EN_CQ_STATEPOLL | 692 MLX4_EN_CQ_STATENAPI_YIELD)); 693 694 if (cq->state & MLX4_EN_CQ_STATEPOLL_YIELD) 695 rc = true; 696 cq->state = MLX4_EN_CQ_STATEIDLE; 697 spin_unlock(&cq->poll_lock); 698 return rc; 699} 700 701/* called from mlx4_en_low_latency_poll() */ 702static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 703{ 704 int rc = true; 705 spin_lock_bh(&cq->poll_lock); 706 if ((cq->state & MLX4_CQ_LOCKED)) { 707 struct net_device *dev = cq->dev; 708 struct mlx4_en_priv *priv = netdev_priv(dev); 709 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; 710 711 cq->state |= MLX4_EN_CQ_STATEPOLL_YIELD; 712 rc = false; 713#ifdef LL_EXTENDED_STATS 714 rx_ring->yields++; 715#endif 716 } else 717 /* preserve yield marks */ 718 cq->state |= MLX4_EN_CQ_STATEPOLL; 719 spin_unlock_bh(&cq->poll_lock); 720 return rc; 721} 722 723/* returns true if someone tried to get the cq while it was locked */ 724static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 725{ 726 int rc = false; 727 spin_lock_bh(&cq->poll_lock); 728 WARN_ON(cq->state & (MLX4_EN_CQ_STATENAPI)); 729 730 if (cq->state & MLX4_EN_CQ_STATEPOLL_YIELD) 731 rc = true; 732 cq->state = MLX4_EN_CQ_STATEIDLE; 733 spin_unlock_bh(&cq->poll_lock); 734 return rc; 735} 736 737/* true if a socket is polling, even if it did not get the lock */ 738static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq) 739{ 740 WARN_ON(!(cq->state & MLX4_CQ_LOCKED)); 741 return cq->state & CQ_USER_PEND; 742} 743#else 744static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 745{ 746} 747 748static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 749{ 750 return true; 751} 752 753static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 754{ 755 return false; 756} 757 758static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 759{ 760 return false; 761} 762 763static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 764{ 765 return false; 766} 767 768static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq) 769{ 770 return false; 771} 772#endif /* CONFIG_NET_RX_BUSY_POLL */ 773 774#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 775 776void mlx4_en_destroy_netdev(struct net_device *dev); 777int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 778 struct mlx4_en_port_profile *prof); 779 780int mlx4_en_start_port(struct net_device *dev); 781void mlx4_en_stop_port(struct net_device *dev); 782 783void mlx4_en_free_resources(struct mlx4_en_priv *priv); 784int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 785 786int mlx4_en_pre_config(struct mlx4_en_priv *priv); 787int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 788 int entries, int ring, enum cq_type mode, int node); 789void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 790int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 791 int cq_idx); 792void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 793int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 794int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 795 796void mlx4_en_tx_irq(struct mlx4_cq *mcq); 797u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb); 798 799int mlx4_en_transmit(struct ifnet *dev, struct mbuf *m); 800int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 801 struct mlx4_en_tx_ring **pring, 802 u32 size, u16 stride, int node, int queue_idx); 803void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 804 struct mlx4_en_tx_ring **pring); 805int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 806 struct mlx4_en_tx_ring *ring, 807 int cq, int user_prio); 808void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 809 struct mlx4_en_tx_ring *ring); 810void mlx4_en_qflush(struct ifnet *dev); 811 812int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 813 struct mlx4_en_rx_ring **pring, 814 u32 size, int node); 815void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 816 struct mlx4_en_rx_ring **pring, 817 u32 size, u16 stride); 818void mlx4_en_tx_que(void *context, int pending); 819void mlx4_en_rx_que(void *context, int pending); 820int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 821void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 822 struct mlx4_en_rx_ring *ring); 823int mlx4_en_process_rx_cq(struct net_device *dev, 824 struct mlx4_en_cq *cq, 825 int budget); 826void mlx4_en_poll_tx_cq(unsigned long data); 827void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 828 int is_tx, int rss, int qpn, int cqn, int user_prio, 829 struct mlx4_qp_context *context); 830void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 831int mlx4_en_map_buffer(struct mlx4_buf *buf); 832void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 833void mlx4_en_calc_rx_buf(struct net_device *dev); 834 835int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 836void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 837int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 838void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 839int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 840void mlx4_en_rx_irq(struct mlx4_cq *mcq); 841 842int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 843int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 844 845int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 846int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 847int mlx4_en_get_vport_stats(struct mlx4_en_dev *mdev, u8 port); 848void mlx4_en_create_debug_files(struct mlx4_en_priv *priv); 849void mlx4_en_delete_debug_files(struct mlx4_en_priv *priv); 850int mlx4_en_register_debugfs(void); 851void mlx4_en_unregister_debugfs(void); 852 853#ifdef CONFIG_MLX4_EN_DCB 854extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 855extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 856#endif 857 858int mlx4_en_setup_tc(struct net_device *dev, u8 up); 859 860#ifdef CONFIG_RFS_ACCEL 861void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv, 862 struct mlx4_en_rx_ring *rx_ring); 863#endif 864 865#define MLX4_EN_NUM_SELF_TEST 5 866void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 867void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 868 869/* 870 * Functions for time stamping 871 */ 872#define SKBTX_HW_TSTAMP (1 << 0) 873#define SKBTX_IN_PROGRESS (1 << 2) 874 875u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 876 877/* Functions for caching and restoring statistics */ 878int mlx4_en_get_sset_count(struct net_device *dev, int sset); 879void mlx4_en_restore_ethtool_stats(struct mlx4_en_priv *priv, 880 u64 *data); 881 882/* 883 * Globals 884 */ 885extern const struct ethtool_ops mlx4_en_ethtool_ops; 886 887/* 888 * Defines for link speed - needed by selftest 889 */ 890#define MLX4_EN_LINK_SPEED_1G 1000 891#define MLX4_EN_LINK_SPEED_10G 10000 892#define MLX4_EN_LINK_SPEED_40G 40000 893 894enum { 895 NETIF_MSG_DRV = 0x0001, 896 NETIF_MSG_PROBE = 0x0002, 897 NETIF_MSG_LINK = 0x0004, 898 NETIF_MSG_TIMER = 0x0008, 899 NETIF_MSG_IFDOWN = 0x0010, 900 NETIF_MSG_IFUP = 0x0020, 901 NETIF_MSG_RX_ERR = 0x0040, 902 NETIF_MSG_TX_ERR = 0x0080, 903 NETIF_MSG_TX_QUEUED = 0x0100, 904 NETIF_MSG_INTR = 0x0200, 905 NETIF_MSG_TX_DONE = 0x0400, 906 NETIF_MSG_RX_STATUS = 0x0800, 907 NETIF_MSG_PKTDATA = 0x1000, 908 NETIF_MSG_HW = 0x2000, 909 NETIF_MSG_WOL = 0x4000, 910}; 911 912 913/* 914 * printk / logging functions 915 */ 916 917#define en_print(level, priv, format, arg...) \ 918 { \ 919 if ((priv)->registered) \ 920 printk(level "%s: %s: " format, DRV_NAME, \ 921 (priv->dev)->if_xname, ## arg); \ 922 else \ 923 printk(level "%s: %s: Port %d: " format, \ 924 DRV_NAME, dev_name(&priv->mdev->pdev->dev), \ 925 (priv)->port, ## arg); \ 926 } 927 928 929#define en_dbg(mlevel, priv, format, arg...) \ 930do { \ 931 if (NETIF_MSG_##mlevel & priv->msg_enable) \ 932 en_print(KERN_DEBUG, priv, format, ##arg); \ 933} while (0) 934#define en_warn(priv, format, arg...) \ 935 en_print(KERN_WARNING, priv, format, ##arg) 936#define en_err(priv, format, arg...) \ 937 en_print(KERN_ERR, priv, format, ##arg) 938#define en_info(priv, format, arg...) \ 939 en_print(KERN_INFO, priv, format, ## arg) 940 941#define mlx4_err(mdev, format, arg...) \ 942 pr_err("%s %s: " format, DRV_NAME, \ 943 dev_name(&mdev->pdev->dev), ##arg) 944#define mlx4_info(mdev, format, arg...) \ 945 pr_info("%s %s: " format, DRV_NAME, \ 946 dev_name(&mdev->pdev->dev), ##arg) 947#define mlx4_warn(mdev, format, arg...) \ 948 pr_warning("%s %s: " format, DRV_NAME, \ 949 dev_name(&mdev->pdev->dev), ##arg) 950 951#endif 952