sff8472.h revision 298995
1258692Sgnn/*- 2258692Sgnn * Copyright (c) 2013 George V. Neville-Neil 3258692Sgnn * All rights reserved. 4258692Sgnn * 5258692Sgnn * Redistribution and use in source and binary forms, with or without 6258692Sgnn * modification, are permitted provided that the following conditions 7258692Sgnn * are met: 8258692Sgnn * 1. Redistributions of source code must retain the above copyright 9258692Sgnn * notice, this list of conditions and the following disclaimer. 10258692Sgnn * 2. Redistributions in binary form must reproduce the above copyright 11258692Sgnn * notice, this list of conditions and the following disclaimer in the 12258692Sgnn * documentation and/or other materials provided with the distribution. 13258692Sgnn * 14258692Sgnn * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15258692Sgnn * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16258692Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17258692Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18258692Sgnn * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19258692Sgnn * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20258692Sgnn * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21258692Sgnn * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22258692Sgnn * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23258692Sgnn * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24258692Sgnn * SUCH DAMAGE. 25258692Sgnn * 26258692Sgnn * $FreeBSD: head/sys/net/sff8472.h 298995 2016-05-03 18:05:43Z pfg $ 27258692Sgnn */ 28258692Sgnn 29258692Sgnn/* 30258692Sgnn * The following set of constants are from Document SFF-8472 31258692Sgnn * "Diagnostic Monitoring Interface for Optical Transceivers" revision 32258692Sgnn * 11.3 published by the SFF Committee on June 11, 2013 33258692Sgnn * 34258692Sgnn * The SFF standard defines two ranges of addresses, each 255 bytes 35258692Sgnn * long for the storage of data and diagnostics on cables, such as 36258692Sgnn * SFP+ optics and TwinAx cables. The ranges are defined in the 37258692Sgnn * following way: 38258692Sgnn * 39258692Sgnn * Base Address 0xa0 (Identification Data) 40258692Sgnn * 0-95 Serial ID Defined by SFP MSA 41258692Sgnn * 96-127 Vendor Specific Data 42258692Sgnn * 128-255 Reserved 43258692Sgnn * 44258692Sgnn * Base Address 0xa2 (Diagnostic Data) 45258692Sgnn * 0-55 Alarm and Warning Thresholds 46258692Sgnn * 56-95 Cal Constants 47258692Sgnn * 96-119 Real Time Diagnostic Interface 48258692Sgnn * 120-127 Vendor Specific 49258692Sgnn * 128-247 User Writable EEPROM 50258692Sgnn * 248-255 Vendor Specific 51258692Sgnn * 52258692Sgnn * Note that not all addresses are supported. Where support is 53258692Sgnn * optional this is noted and instructions for checking for the 54258692Sgnn * support are supplied. 55258692Sgnn * 56258692Sgnn * All these values are read across an I2C (i squared C) bus. Any 57258692Sgnn * device wishing to read these addresses must first have support for 58258692Sgnn * i2c calls. The Chelsio T4/T5 driver (dev/cxgbe) is one such 59258692Sgnn * driver. 60258692Sgnn */ 61258692Sgnn 62258692Sgnn 63258692Sgnn/* Table 3.1 Two-wire interface ID: Data Fields */ 64258692Sgnn 65260207Sgnnenum { 66260207Sgnn SFF_8472_BASE = 0xa0, /* Base address for all our queries. */ 67260207Sgnn SFF_8472_ID = 0, /* Transceiver Type (Table 3.2) */ 68260207Sgnn SFF_8472_EXT_ID = 1, /* Extended transceiver type (Table 3.3) */ 69260207Sgnn SFF_8472_CONNECTOR = 2, /* Connector type (Table 3.4) */ 70260207Sgnn SFF_8472_TRANS_START = 3, /* Elec or Optical Compatibility 71258692Sgnn * (Table 3.5) */ 72260207Sgnn SFF_8472_TRANS_END = 10, 73260207Sgnn SFF_8472_ENCODING = 11, /* Encoding Code for high speed 74260207Sgnn * serial encoding algorithm (see 75260207Sgnn * Table 3.6) */ 76260207Sgnn SFF_8472_BITRATE = 12, /* Nominal signaling rate, units 77260207Sgnn * of 100MBd. (see details for 78260207Sgnn * rates > 25.0Gb/s) */ 79260207Sgnn SFF_8472_RATEID = 13, /* Type of rate select 80260207Sgnn * functionality (see Table 81260207Sgnn * 3.6a) */ 82260207Sgnn SFF_8472_LEN_SMF_KM = 14, /* Link length supported for single 83258692Sgnn * mode fiber, units of km */ 84260207Sgnn SFF_8472_LEN_SMF = 15, /* Link length supported for single 85258692Sgnn * mode fiber, units of 100 m */ 86260207Sgnn SFF_8472_LEN_50UM = 16, /* Link length supported for 50 um 87258692Sgnn * OM2 fiber, units of 10 m */ 88260207Sgnn SFF_8472_LEN_625UM = 17, /* Link length supported for 62.5 89258692Sgnn * um OM1 fiber, units of 10 m */ 90260207Sgnn SFF_8472_LEN_OM4 = 18, /* Link length supported for 50um 91258692Sgnn * OM4 fiber, units of 10m. 92258692Sgnn * Alternatively copper or direct 93258692Sgnn * attach cable, units of m */ 94260207Sgnn SFF_8472_LEN_OM3 = 19, /* Link length supported for 50 um OM3 fiber, units of 10 m */ 95260207Sgnn SFF_8472_VENDOR_START = 20, /* Vendor name [Address A0h, Bytes 96258692Sgnn * 20-35] */ 97260207Sgnn SFF_8472_VENDOR_END = 35, 98260207Sgnn SFF_8472_TRANS = 36, /* Transceiver Code for electronic 99258692Sgnn * or optical compatibility (see 100258692Sgnn * Table 3.5) */ 101260207Sgnn SFF_8472_VENDOR_OUI_START = 37, /* Vendor OUI SFP vendor IEEE 102258692Sgnn * company ID */ 103260207Sgnn SFF_8472_VENDOR_OUI_END = 39, 104260207Sgnn SFF_8472_PN_START = 40, /* Vendor PN */ 105260207Sgnn SFF_8472_PN_END = 55, 106260207Sgnn SFF_8472_REV_START = 56, /* Vendor Revision */ 107260207Sgnn SFF_8472_REV_END = 59, 108260207Sgnn SFF_8472_WAVELEN_START = 60, /* Wavelength Laser wavelength 109258692Sgnn * (Passive/Active Cable 110258692Sgnn * Specification Compliance) */ 111260207Sgnn SFF_8472_WAVELEN_END = 61, 112260207Sgnn SFF_8472_CC_BASE = 63, /* CC_BASE Check code for Base ID 113258692Sgnn * Fields (addresses 0 to 62) */ 114258692Sgnn 115258692Sgnn/* 116258692Sgnn * Extension Fields (optional) check the options before reading other 117258692Sgnn * addresses. 118258692Sgnn */ 119260207Sgnn SFF_8472_OPTIONS_MSB = 64, /* Options Indicates which optional 120258692Sgnn * transceiver signals are 121258692Sgnn * implemented */ 122260207Sgnn SFF_8472_OPTIONS_LSB = 65, /* (see Table 3.7) */ 123260207Sgnn SFF_8472_BR_MAX = 66, /* BR max Upper bit rate margin, 124258692Sgnn * units of % (see details for 125258692Sgnn * rates > 25.0Gb/s) */ 126260207Sgnn SFF_8472_BR_MIN = 67, /* Lower bit rate margin, units of 127258692Sgnn * % (see details for rates > 128258692Sgnn * 25.0Gb/s) */ 129260207Sgnn SFF_8472_SN_START = 68, /* Vendor SN [Address A0h, Bytes 68-83] */ 130260207Sgnn SFF_8472_SN_END = 83, 131260207Sgnn SFF_8472_DATE_START = 84, /* Date code Vendor���s manufacturing 132258692Sgnn * date code (see Table 3.8) */ 133260207Sgnn SFF_8472_DATE_END = 91, 134260207Sgnn SFF_8472_DIAG_TYPE = 92, /* Diagnostic Monitoring Type 135258692Sgnn * Indicates which type of 136258692Sgnn * diagnostic monitoring is 137258692Sgnn * implemented (if any) in the 138258692Sgnn * transceiver (see Table 3.9) 139258692Sgnn */ 140258692Sgnn 141260207Sgnn SFF_8472_ENHANCED = 93, /* Enhanced Options Indicates which 142258692Sgnn * optional enhanced features are 143258692Sgnn * implemented (if any) in the 144258692Sgnn * transceiver (see Table 3.10) */ 145260207Sgnn SFF_8472_COMPLIANCE = 94, /* SFF-8472 Compliance Indicates 146258692Sgnn * which revision of SFF-8472 the 147258692Sgnn * transceiver complies with. (see 148258692Sgnn * Table 3.12)*/ 149260207Sgnn SFF_8472_CC_EXT = 95, /* Check code for the Extended ID 150258692Sgnn * Fields (addresses 64 to 94) 151258692Sgnn */ 152258692Sgnn 153260207Sgnn SFF_8472_VENDOR_RSRVD_START = 96, 154260207Sgnn SFF_8472_VENDOR_RSRVD_END = 127, 155258692Sgnn 156260207Sgnn SFF_8472_RESERVED_START = 128, 157260207Sgnn SFF_8472_RESERVED_END = 255 158260207Sgnn}; 159258692Sgnn 160260207Sgnn#define SFF_8472_DIAG_IMPL (1 << 6) /* Required to be 1 */ 161260207Sgnn#define SFF_8472_DIAG_INTERNAL (1 << 5) /* Internal measurements. */ 162260207Sgnn#define SFF_8472_DIAG_EXTERNAL (1 << 4) /* External measurements. */ 163260207Sgnn#define SFF_8472_DIAG_POWER (1 << 3) /* Power measurement type */ 164260207Sgnn#define SFF_8472_DIAG_ADDR_CHG (1 << 2) /* Address change required. 165260207Sgnn * See SFF-8472 doc. */ 166260207Sgnn 167258692Sgnn /* 168258692Sgnn * Diagnostics are available at the two wire address 0xa2. All 169258692Sgnn * diagnostics are OPTIONAL so you should check 0xa0 registers 92 to 170258692Sgnn * see which, if any are supported. 171258692Sgnn */ 172258692Sgnn 173260207Sgnnenum {SFF_8472_DIAG = 0xa2}; /* Base address for diagnostics. */ 174258692Sgnn 175258692Sgnn /* 176258692Sgnn * Table 3.15 Alarm and Warning Thresholds All values are 2 bytes 177258692Sgnn * and MUST be read in a single read operation starting at the MSB 178258692Sgnn */ 179258692Sgnn 180260207Sgnnenum { 181260207Sgnn SFF_8472_TEMP_HIGH_ALM = 0, /* Temp High Alarm */ 182260207Sgnn SFF_8472_TEMP_LOW_ALM = 2, /* Temp Low Alarm */ 183260207Sgnn SFF_8472_TEMP_HIGH_WARN = 4, /* Temp High Warning */ 184260207Sgnn SFF_8472_TEMP_LOW_WARN = 6, /* Temp Low Warning */ 185260207Sgnn SFF_8472_VOLTAGE_HIGH_ALM = 8, /* Voltage High Alarm */ 186260207Sgnn SFF_8472_VOLTAGE_LOW_ALM = 10, /* Voltage Low Alarm */ 187260207Sgnn SFF_8472_VOLTAGE_HIGH_WARN = 12, /* Voltage High Warning */ 188260207Sgnn SFF_8472_VOLTAGE_LOW_WARN = 14, /* Voltage Low Warning */ 189260207Sgnn SFF_8472_BIAS_HIGH_ALM = 16, /* Bias High Alarm */ 190260207Sgnn SFF_8472_BIAS_LOW_ALM = 18, /* Bias Low Alarm */ 191260207Sgnn SFF_8472_BIAS_HIGH_WARN = 20, /* Bias High Warning */ 192260207Sgnn SFF_8472_BIAS_LOW_WARN = 22, /* Bias Low Warning */ 193260207Sgnn SFF_8472_TX_POWER_HIGH_ALM = 24, /* TX Power High Alarm */ 194260207Sgnn SFF_8472_TX_POWER_LOW_ALM = 26, /* TX Power Low Alarm */ 195260207Sgnn SFF_8472_TX_POWER_HIGH_WARN = 28, /* TX Power High Warning */ 196260207Sgnn SFF_8472_TX_POWER_LOW_WARN = 30, /* TX Power Low Warning */ 197260207Sgnn SFF_8472_RX_POWER_HIGH_ALM = 32, /* RX Power High Alarm */ 198260207Sgnn SFF_8472_RX_POWER_LOW_ALM = 34, /* RX Power Low Alarm */ 199260207Sgnn SFF_8472_RX_POWER_HIGH_WARN = 36, /* RX Power High Warning */ 200260207Sgnn SFF_8472_RX_POWER_LOW_WARN = 38, /* RX Power Low Warning */ 201258692Sgnn 202260207Sgnn SFF_8472_RX_POWER4 = 56, /* Rx_PWR(4) Single precision 203258692Sgnn * floating point calibration data 204258692Sgnn * - Rx optical power. Bit 7 of 205258692Sgnn * byte 56 is MSB. Bit 0 of byte 206258692Sgnn * 59 is LSB. Rx_PWR(4) should be 207258692Sgnn * set to zero for ���internally 208258692Sgnn * calibrated��� devices. */ 209260207Sgnn SFF_8472_RX_POWER3 = 60, /* Rx_PWR(3) Single precision 210258692Sgnn * floating point calibration data 211258692Sgnn * - Rx optical power. Bit 7 of 212258692Sgnn * byte 60 is MSB. Bit 0 of byte 63 213258692Sgnn * is LSB. Rx_PWR(3) should be set 214258692Sgnn * to zero for ���internally 215258692Sgnn * calibrated��� devices.*/ 216260207Sgnn SFF_8472_RX_POWER2 = 64, /* Rx_PWR(2) Single precision 217258692Sgnn * floating point calibration data, 218258692Sgnn * Rx optical power. Bit 7 of byte 219258692Sgnn * 64 is MSB, bit 0 of byte 67 is 220258692Sgnn * LSB. Rx_PWR(2) should be set to 221258692Sgnn * zero for ���internally calibrated��� 222258692Sgnn * devices. */ 223260207Sgnn SFF_8472_RX_POWER1 = 68, /* Rx_PWR(1) Single precision 224258692Sgnn * floating point calibration data, 225258692Sgnn * Rx optical power. Bit 7 of byte 226258692Sgnn * 68 is MSB, bit 0 of byte 71 is 227258692Sgnn * LSB. Rx_PWR(1) should be set to 228258692Sgnn * 1 for ���internally calibrated��� 229258692Sgnn * devices. */ 230260207Sgnn SFF_8472_RX_POWER0 = 72, /* Rx_PWR(0) Single precision 231258692Sgnn * floating point calibration data, 232258692Sgnn * Rx optical power. Bit 7 of byte 233258692Sgnn * 72 is MSB, bit 0 of byte 75 is 234258692Sgnn * LSB. Rx_PWR(0) should be set to 235258692Sgnn * zero for ���internally calibrated��� 236258692Sgnn * devices. */ 237260207Sgnn SFF_8472_TX_I_SLOPE = 76, /* Tx_I(Slope) Fixed decimal 238258692Sgnn * (unsigned) calibration data, 239258692Sgnn * laser bias current. Bit 7 of 240258692Sgnn * byte 76 is MSB, bit 0 of byte 77 241258692Sgnn * is LSB. Tx_I(Slope) should be 242258692Sgnn * set to 1 for ���internally 243258692Sgnn * calibrated��� devices. */ 244260207Sgnn SFF_8472_TX_I_OFFSET = 78, /* Tx_I(Offset) Fixed decimal 245258692Sgnn * (signed two���s complement) 246258692Sgnn * calibration data, laser bias 247258692Sgnn * current. Bit 7 of byte 78 is 248258692Sgnn * MSB, bit 0 of byte 79 is 249258692Sgnn * LSB. Tx_I(Offset) should be set 250258692Sgnn * to zero for ���internally 251258692Sgnn * calibrated��� devices. */ 252260207Sgnn SFF_8472_TX_POWER_SLOPE = 80, /* Tx_PWR(Slope) Fixed decimal 253258692Sgnn * (unsigned) calibration data, 254258692Sgnn * transmitter coupled output 255258692Sgnn * power. Bit 7 of byte 80 is MSB, 256258692Sgnn * bit 0 of byte 81 is LSB. 257258692Sgnn * Tx_PWR(Slope) should be set to 1 258258692Sgnn * for ���internally calibrated��� 259258692Sgnn * devices. */ 260260207Sgnn SFF_8472_TX_POWER_OFFSET = 82, /* Tx_PWR(Offset) Fixed decimal 261260207Sgnn * (signed two���s complement) 262260207Sgnn * calibration data, transmitter 263260207Sgnn * coupled output power. Bit 7 of 264260207Sgnn * byte 82 is MSB, bit 0 of byte 83 265260207Sgnn * is LSB. Tx_PWR(Offset) should be 266260207Sgnn * set to zero for ���internally 267260207Sgnn * calibrated��� devices. */ 268260207Sgnn SFF_8472_T_SLOPE = 84, /* T (Slope) Fixed decimal 269258692Sgnn * (unsigned) calibration data, 270258692Sgnn * internal module temperature. Bit 271258692Sgnn * 7 of byte 84 is MSB, bit 0 of 272258692Sgnn * byte 85 is LSB. T(Slope) should 273258692Sgnn * be set to 1 for ���internally 274258692Sgnn * calibrated��� devices. */ 275260207Sgnn SFF_8472_T_OFFSET = 86, /* T (Offset) Fixed decimal (signed 276258692Sgnn * two���s complement) calibration 277258692Sgnn * data, internal module 278258692Sgnn * temperature. Bit 7 of byte 86 is 279258692Sgnn * MSB, bit 0 of byte 87 is LSB. 280258692Sgnn * T(Offset) should be set to zero 281258692Sgnn * for ���internally calibrated��� 282258692Sgnn * devices. */ 283260207Sgnn SFF_8472_V_SLOPE = 88, /* V (Slope) Fixed decimal 284258692Sgnn * (unsigned) calibration data, 285258692Sgnn * internal module supply 286258692Sgnn * voltage. Bit 7 of byte 88 is 287258692Sgnn * MSB, bit 0 of byte 89 is 288258692Sgnn * LSB. V(Slope) should be set to 1 289258692Sgnn * for ���internally calibrated��� 290258692Sgnn * devices. */ 291260207Sgnn SFF_8472_V_OFFSET = 90, /* V (Offset) Fixed decimal (signed 292258692Sgnn * two���s complement) calibration 293258692Sgnn * data, internal module supply 294258692Sgnn * voltage. Bit 7 of byte 90 is 295258692Sgnn * MSB. Bit 0 of byte 91 is 296258692Sgnn * LSB. V(Offset) should be set to 297258692Sgnn * zero for ���internally calibrated��� 298258692Sgnn * devices. */ 299260207Sgnn SFF_8472_CHECKSUM = 95, /* Checksum Byte 95 contains the 300258692Sgnn * low order 8 bits of the sum of 301258692Sgnn * bytes 0 ��� 94. */ 302260207Sgnn /* Internal measurements. */ 303258692Sgnn 304260207Sgnn SFF_8472_TEMP = 96, /* Internally measured module temperature. */ 305260207Sgnn SFF_8472_VCC = 98, /* Internally measured supply 306258692Sgnn * voltage in transceiver. 307258692Sgnn */ 308260207Sgnn SFF_8472_TX_BIAS = 100, /* Internally measured TX Bias Current. */ 309260207Sgnn SFF_8472_TX_POWER = 102, /* Measured TX output power. */ 310260207Sgnn SFF_8472_RX_POWER = 104, /* Measured RX input power. */ 311258692Sgnn 312260207Sgnn SFF_8472_STATUS = 110 /* See below */ 313260207Sgnn}; 314258692Sgnn /* Status Bits Described */ 315258692Sgnn 316258692Sgnn/* 317258692Sgnn * TX Disable State Digital state of the TX Disable Input Pin. Updated 318258692Sgnn * within 100ms of change on pin. 319258692Sgnn */ 320258692Sgnn#define SFF_8472_STATUS_TX_DISABLE (1 << 7) 321258692Sgnn 322258692Sgnn/* 323258692Sgnn * Select Read/write bit that allows software disable of 324258692Sgnn * laser. Writing ���1��� disables laser. See Table 3.11 for 325258692Sgnn * enable/disable timing requirements. This bit is ���OR���d with the hard 326258692Sgnn * TX_DISABLE pin value. Note, per SFP MSA TX_DISABLE pin is default 327258692Sgnn * enabled unless pulled low by hardware. If Soft TX Disable is not 328258692Sgnn * implemented, the transceiver ignores the value of this bit. Default 329258692Sgnn * power up value is zero/low. 330258692Sgnn */ 331258692Sgnn#define SFF_8472_STATUS_SOFT_TX_DISABLE (1 << 6) 332258692Sgnn 333258692Sgnn/* 334258692Sgnn * RS(1) State Digital state of SFP input pin AS(1) per SFF-8079 or 335258692Sgnn * RS(1) per SFF-8431. Updated within 100ms of change on pin. See A2h 336258692Sgnn * Byte 118, Bit 3 for Soft RS(1) Select control information. 337258692Sgnn */ 338258692Sgnn#define SFF_8472_RS_STATE (1 << 5) 339258692Sgnn 340258692Sgnn/* 341258692Sgnn * Rate_Select State [aka. ���RS(0)���] Digital state of the SFP 342258692Sgnn * Rate_Select Input Pin. Updated within 100ms of change on pin. Note: 343258692Sgnn * This pin is also known as AS(0) in SFF-8079 and RS(0) in SFF-8431. 344258692Sgnn */ 345258692Sgnn#define SFF_8472_STATUS_SELECT_STATE (1 << 4) 346258692Sgnn 347258692Sgnn/* 348258692Sgnn * Read/write bit that allows software rate select control. Writing 349258692Sgnn * ���1��� selects full bandwidth operation. This bit is ���OR���d with the 350258692Sgnn * hard Rate_Select, AS(0) or RS(0) pin value. See Table 3.11 for 351258692Sgnn * timing requirements. Default at power up is logic zero/low. If Soft 352258692Sgnn * Rate Select is not implemented, the transceiver ignores the value 353258692Sgnn * of this bit. Note: Specific transceiver behaviors of this bit are 354258692Sgnn * identified in Table 3.6a and referenced documents. See Table 3.18a, 355258692Sgnn * byte 118, bit 3 for Soft RS(1) Select. 356258692Sgnn */ 357258692Sgnn#define SFF_8472_STATUS_SOFT_RATE_SELECT (1 << 3) 358258692Sgnn 359258692Sgnn/* 360258692Sgnn * TX Fault State Digital state of the TX Fault Output Pin. Updated 361258692Sgnn * within 100ms of change on pin. 362258692Sgnn */ 363258692Sgnn#define SFF_8472_STATUS_TX_FAULT_STATE (1 << 2) 364258692Sgnn 365258692Sgnn/* 366258692Sgnn * Digital state of the RX_LOS Output Pin. Updated within 100ms of 367258692Sgnn * change on pin. 368258692Sgnn */ 369258692Sgnn#define SFF_8472_STATUS_RX_LOS (1 << 1) 370258692Sgnn 371258692Sgnn/* 372258692Sgnn * Indicates transceiver has achieved power up and data is ready. Bit 373258692Sgnn * remains high until data is ready to be read at which time the 374258692Sgnn * device sets the bit low. 375258692Sgnn */ 376258692Sgnn#define SFF_8472_STATUS_DATA_READY (1 << 0) 377258692Sgnn 378270287Smelifaro/* 379270287Smelifaro * Table 3.2 Identifier values. 380283009Smelifaro * Identifier constants has taken from SFF-8024 rev 2.9 table 4.1 381270287Smelifaro * (as referenced by table 3.2 footer) 382270287Smelifaro * */ 383260207Sgnnenum { 384270287Smelifaro SFF_8024_ID_UNKNOWN = 0x0, /* Unknown or unspecified */ 385270287Smelifaro SFF_8024_ID_GBIC = 0x1, /* GBIC */ 386270287Smelifaro SFF_8024_ID_SFF = 0x2, /* Module soldered to motherboard (ex: SFF)*/ 387270287Smelifaro SFF_8024_ID_SFP = 0x3, /* SFP or SFP ���Plus��� */ 388270287Smelifaro SFF_8024_ID_XBI = 0x4, /* 300 pin XBI */ 389270287Smelifaro SFF_8024_ID_XENPAK = 0x5, /* Xenpak */ 390270287Smelifaro SFF_8024_ID_XFP = 0x6, /* XFP */ 391270287Smelifaro SFF_8024_ID_XFF = 0x7, /* XFF */ 392270287Smelifaro SFF_8024_ID_XFPE = 0x8, /* XFP-E */ 393270287Smelifaro SFF_8024_ID_XPAK = 0x9, /* XPAk */ 394270287Smelifaro SFF_8024_ID_X2 = 0xA, /* X2 */ 395270287Smelifaro SFF_8024_ID_DWDM_SFP = 0xB, /* DWDM-SFP */ 396270287Smelifaro SFF_8024_ID_QSFP = 0xC, /* QSFP */ 397270287Smelifaro SFF_8024_ID_QSFPPLUS = 0xD, /* QSFP+ */ 398270287Smelifaro SFF_8024_ID_CXP = 0xE, /* CXP */ 399270287Smelifaro SFF_8024_ID_HD4X = 0xF, /* Shielded Mini Multilane HD 4X */ 400270287Smelifaro SFF_8024_ID_HD8X = 0x10, /* Shielded Mini Multilane HD 8X */ 401270287Smelifaro SFF_8024_ID_QSFP28 = 0x11, /* QSFP28 */ 402270287Smelifaro SFF_8024_ID_CXP2 = 0x12, /* CXP2 (aka CXP28) */ 403283009Smelifaro SFF_8024_ID_CDFP = 0x13, /* CDFP (Style 1/Style 2) */ 404283009Smelifaro SFF_8024_ID_SMM4 = 0x14, /* Shielded Mini Multilate HD 4X Fanout */ 405283009Smelifaro SFF_8024_ID_SMM8 = 0x15, /* Shielded Mini Multilate HD 8X Fanout */ 406283009Smelifaro SFF_8024_ID_CDFP3 = 0x16, /* CDFP (Style3) */ 407283009Smelifaro SFF_8024_ID_LAST = SFF_8024_ID_CDFP3 408260207Sgnn }; 409258692Sgnn 410270287Smelifarostatic const char *sff_8024_id[SFF_8024_ID_LAST + 1] = {"Unknown", 411258692Sgnn "GBIC", 412258692Sgnn "SFF", 413283009Smelifaro "SFP/SFP+/SFP28", 414258692Sgnn "XBI", 415258692Sgnn "Xenpak", 416258692Sgnn "XFP", 417258692Sgnn "XFF", 418258692Sgnn "XFP-E", 419283009Smelifaro "XPAK", 420258692Sgnn "X2", 421283009Smelifaro "DWDM-SFP/SFP+", 422270287Smelifaro "QSFP", 423270287Smelifaro "QSFP+", 424270287Smelifaro "CXP", 425270287Smelifaro "HD4X", 426270287Smelifaro "HD8X", 427270287Smelifaro "QSFP28", 428283009Smelifaro "CXP2", 429283009Smelifaro "CDFP", 430283009Smelifaro "SMM4", 431283009Smelifaro "SMM8", 432283009Smelifaro "CDFP3"}; 433258692Sgnn 434298995Spfg/* Keep compatibility with old definitions */ 435270287Smelifaro#define SFF_8472_ID_UNKNOWN SFF_8024_ID_UNKNOWN 436270287Smelifaro#define SFF_8472_ID_GBIC SFF_8024_ID_GBIC 437270287Smelifaro#define SFF_8472_ID_SFF SFF_8024_ID_SFF 438270287Smelifaro#define SFF_8472_ID_SFP SFF_8024_ID_SFP 439270287Smelifaro#define SFF_8472_ID_XBI SFF_8024_ID_XBI 440270287Smelifaro#define SFF_8472_ID_XENPAK SFF_8024_ID_XENPAK 441270287Smelifaro#define SFF_8472_ID_XFP SFF_8024_ID_XFP 442270287Smelifaro#define SFF_8472_ID_XFF SFF_8024_ID_XFF 443270287Smelifaro#define SFF_8472_ID_XFPE SFF_8024_ID_XFPE 444270287Smelifaro#define SFF_8472_ID_XPAK SFF_8024_ID_XPAK 445270287Smelifaro#define SFF_8472_ID_X2 SFF_8024_ID_X2 446270287Smelifaro#define SFF_8472_ID_DWDM_SFP SFF_8024_ID_DWDM_SFP 447270287Smelifaro#define SFF_8472_ID_QSFP SFF_8024_ID_QSFP 448270287Smelifaro#define SFF_8472_ID_LAST SFF_8024_ID_LAST 449270287Smelifaro 450270287Smelifaro#define sff_8472_id sff_8024_id 451270287Smelifaro 452270287Smelifaro/* 453270287Smelifaro * Table 3.9 Diagnostic Monitoring Type (byte 92) 454270287Smelifaro * bits described. 455270287Smelifaro */ 456270287Smelifaro 457270287Smelifaro/* 458270287Smelifaro * Digital diagnostic monitoring implemented. 459270287Smelifaro * Set to 1 for transceivers implementing DDM. 460270287Smelifaro */ 461270287Smelifaro#define SFF_8472_DDM_DONE (1 << 6) 462270287Smelifaro 463270287Smelifaro/* 464270287Smelifaro * Measurements are internally calibrated. 465270287Smelifaro */ 466270287Smelifaro#define SFF_8472_DDM_INTERNAL (1 << 5) 467270287Smelifaro 468270287Smelifaro/* 469270287Smelifaro * Measurements are externally calibrated. 470270287Smelifaro */ 471270287Smelifaro#define SFF_8472_DDM_EXTERNAL (1 << 4) 472270287Smelifaro 473270287Smelifaro/* 474270287Smelifaro * Received power measurement type 475270287Smelifaro * 0 = OMA, 1 = average power 476270287Smelifaro */ 477270287Smelifaro#define SFF_8472_DDM_PMTYPE (1 << 3) 478270287Smelifaro 479258692Sgnn/* Table 3.13 and 3.14 Temperature Conversion Values */ 480258692Sgnn#define SFF_8472_TEMP_SIGN (1 << 15) 481258692Sgnn#define SFF_8472_TEMP_SHIFT 8 482258692Sgnn#define SFF_8472_TEMP_MSK 0xEF00 483258692Sgnn#define SFF_8472_TEMP_FRAC 0x00FF 484258692Sgnn 485258692Sgnn/* Internal Callibration Conversion factors */ 486258692Sgnn 487258692Sgnn/* 488258692Sgnn * Represented as a 16 bit unsigned integer with the voltage defined 489258692Sgnn * as the full 16 bit value (0 ��� 65535) with LSB equal to 100 uVolt, 490258692Sgnn * yielding a total range of 0 to +6.55 Volts. 491258692Sgnn */ 492258692Sgnn#define SFF_8472_VCC_FACTOR 10000.0 493258692Sgnn 494258692Sgnn/* 495258692Sgnn * Represented as a 16 bit unsigned integer with the current defined 496258692Sgnn * as the full 16 bit value (0 ��� 65535) with LSB equal to 2 uA, 497258692Sgnn * yielding a total range of 0 to 131 mA. 498258692Sgnn */ 499258692Sgnn 500258692Sgnn#define SFF_8472_BIAS_FACTOR 2000.0 501258692Sgnn 502258692Sgnn/* 503258692Sgnn * Represented as a 16 bit unsigned integer with the power defined as 504258692Sgnn * the full 16 bit value (0 ��� 65535) with LSB equal to 0.1 uW, 505258692Sgnn * yielding a total range of 0 to 6.5535 mW (~ -40 to +8.2 dBm). 506258692Sgnn */ 507258692Sgnn 508258692Sgnn#define SFF_8472_POWER_FACTOR 10000.0 509