rmi_mips_exts.h revision 201917
1208747Sraj/*- 2261352Snwhitehorn * Copyright (c) 2003-2009 RMI Corporation 3208747Sraj * All rights reserved. 4208747Sraj * 5208747Sraj * Redistribution and use in source and binary forms, with or without 6208747Sraj * modification, are permitted provided that the following conditions 7208747Sraj * are met: 8208747Sraj * 1. Redistributions of source code must retain the above copyright 9208747Sraj * notice, this list of conditions and the following disclaimer. 10208747Sraj * 2. Redistributions in binary form must reproduce the above copyright 11208747Sraj * notice, this list of conditions and the following disclaimer in the 12208747Sraj * documentation and/or other materials provided with the distribution. 13208747Sraj * 3. Neither the name of RMI Corporation, nor the names of its contributors, 14208747Sraj * may be used to endorse or promote products derived from this software 15208747Sraj * without specific prior written permission. 16208747Sraj * 17261352Snwhitehorn * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18208747Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19208747Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20208747Sraj * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21208747Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22208747Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23208747Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24208747Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25208747Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26208747Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27208747Sraj * SUCH DAMAGE. 28208747Sraj * 29208747Sraj * RMI_BSD */ 30208747Sraj#ifndef __MIPS_EXTS_H__ 31208747Sraj#define __MIPS_EXTS_H__ 32208747Sraj 33261352Snwhitehorn#define enable_KX(flags) __asm__ __volatile__ ( \ 34261352Snwhitehorn ".set push\n" \ 35208747Sraj ".set noat\n" \ 36208747Sraj ".set noreorder\n" \ 37261352Snwhitehorn "mfc0 %0, $12\n\t" \ 38208747Sraj "ori $1, %0, 0x81\n\t" \ 39208747Sraj "xori $1, 1\n\t" \ 40208747Sraj "mtc0 $1, $12\n" \ 41261352Snwhitehorn ".set pop\n" \ 42261352Snwhitehorn : "=r"(flags) ) 43261352Snwhitehorn 44261352Snwhitehorn#define disable_KX(flags) __asm__ __volatile__ ( \ 45261352Snwhitehorn ".set push\n" \ 46208747Sraj "mtc0 %0, $12\n" \ 47261352Snwhitehorn ".set pop\n" \ 48261352Snwhitehorn : : "r"(flags) ) 49261352Snwhitehorn 50208747Sraj#define CPU_BLOCKID_IFU 0 51261352Snwhitehorn#define CPU_BLOCKID_ICU 1 52261352Snwhitehorn#define CPU_BLOCKID_IEU 2 53208747Sraj#define CPU_BLOCKID_LSU 3 54261352Snwhitehorn#define CPU_BLOCKID_MMU 4 55208747Sraj#define CPU_BLOCKID_PRF 5 56208747Sraj 57208747Sraj#define LSU_CERRLOG_REGID 9 58261352Snwhitehorn 59261352Snwhitehornstatic __inline__ unsigned int read_32bit_phnx_ctrl_reg(int block, int reg) 60208747Sraj{ 61208747Sraj unsigned int __res; 62208747Sraj 63261352Snwhitehorn __asm__ __volatile__( 64208747Sraj ".set\tpush\n\t" 65261352Snwhitehorn ".set\tnoreorder\n\t" 66261352Snwhitehorn "move $9, %1\n" 67208747Sraj /* "mfcr\t$8, $9\n\t" */ 68208747Sraj ".word 0x71280018\n" 69261352Snwhitehorn "move %0, $8\n" 70261352Snwhitehorn ".set\tpop" 71208747Sraj : "=r" (__res) : "r"((block<<8)|reg) 72261352Snwhitehorn : "$8", "$9" 73261352Snwhitehorn ); 74261352Snwhitehorn return __res; 75261352Snwhitehorn} 76261352Snwhitehorn 77208747Srajstatic __inline__ void write_32bit_phnx_ctrl_reg(int block, int reg, unsigned int value) 78208747Sraj{ 79261352Snwhitehorn __asm__ __volatile__( 80208747Sraj ".set\tpush\n\t" 81261352Snwhitehorn ".set\tnoreorder\n\t" 82261352Snwhitehorn "move $8, %0\n" 83261352Snwhitehorn "move $9, %1\n" 84261352Snwhitehorn /* "mtcr\t$8, $9\n\t" */ 85261352Snwhitehorn ".word 0x71280019\n" 86261352Snwhitehorn ".set\tpop" 87261352Snwhitehorn : 88261352Snwhitehorn : "r" (value), "r"((block<<8)|reg) 89261352Snwhitehorn : "$8", "$9" 90261352Snwhitehorn ); 91208747Sraj} 92208747Sraj 93208747Srajstatic __inline__ unsigned long long read_64bit_phnx_ctrl_reg(int block, int reg) 94208747Sraj{ 95208747Sraj unsigned int high, low; 96208747Sraj 97261352Snwhitehorn __asm__ __volatile__( 98261352Snwhitehorn ".set\tmips64\n\t" 99261352Snwhitehorn "move $9, %2\n" 100208747Sraj /* "mfcr $8, $9\n" */ 101261352Snwhitehorn ".word 0x71280018\n" 102261352Snwhitehorn "dsrl32 %0, $8, 0\n\t" 103261352Snwhitehorn "dsll32 $8, $8, 0\n\t" 104261352Snwhitehorn "dsrl32 %1, $8, 0\n\t" 105261352Snwhitehorn ".set mips0" 106208747Sraj : "=r" (high), "=r"(low) 107261352Snwhitehorn : "r"((block<<8)|reg) 108208747Sraj : "$8", "$9" 109208747Sraj ); 110208747Sraj 111208747Sraj return ( (((unsigned long long)high)<<32) | low); 112208747Sraj} 113208747Sraj 114208747Srajstatic __inline__ void write_64bit_phnx_ctrl_reg(int block, int reg,unsigned long long value) 115261352Snwhitehorn{ 116208747Sraj __uint32_t low, high; 117208747Sraj high = value >> 32; 118208747Sraj low = value & 0xffffffff; 119208747Sraj 120208747Sraj __asm__ __volatile__( 121208747Sraj ".set push\n" 122208747Sraj ".set noreorder\n" 123261352Snwhitehorn ".set mips4\n\t" 124269594Sian /* Set up "rs" */ 125269594Sian "move $9, %0\n" 126269594Sian 127269597Sian /* Store 64 bit value in "rt" */ 128208747Sraj "dsll32 $10, %1, 0 \n\t" 129208747Sraj "dsll32 $8, %2, 0 \n\t" 130208747Sraj "dsrl32 $8, $8, 0 \n\t" 131208747Sraj "or $10, $8, $8 \n\t" 132261352Snwhitehorn 133261410Sian ".word 0x71280019\n" /* mtcr $8, $9 */ 134261410Sian 135261410Sian ".set pop\n" 136273282Sian 137273282Sian : /* No outputs */ 138273282Sian : "r"((block<<8)|reg), "r" (high), "r" (low) 139273282Sian : "$8", "$9", "$10" 140273282Sian ); 141273282Sian} 142273282Sian 143261352Snwhitehorn 144261352Snwhitehorn#endif 145208747Sraj