174462Salfred/********************************************************************* 274462Salfred * 3272850Shrs * Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights 4272850Shrs * reserved. 58870Srgrimes * 6272850Shrs * Redistribution and use in source and binary forms, with or without 7272850Shrs * modification, are permitted provided that the following conditions 8272850Shrs * are met: 98870Srgrimes * 10272850Shrs * 1. Redistributions of source code must retain the above copyright 11272850Shrs * notice, this list of conditions and the following disclaimer. 12272850Shrs * 2. Redistributions in binary form must reproduce the above copyright 13272850Shrs * notice, this list of conditions and the following disclaimer in 14272850Shrs * the documentation and/or other materials provided with the 15272850Shrs * distribution. 16272850Shrs * 17272850Shrs * THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND 18272850Shrs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 198870Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20272850Shrs * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE 21272850Shrs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22272850Shrs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23272850Shrs * SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS 24272850Shrs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25272850Shrs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26272850Shrs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27272850Shrs * THE POSSIBILITY OF SUCH DAMAGE. 28272850Shrs * 29272850Shrs * *****************************RMI_2**********************************/ 30272850Shrs#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31272850Shrs__FBSDID("$FreeBSD: releng/11.0/sys/mips/rmi/board.c 216390 2010-12-12 06:00:26Z jchandra $"); 321902Swollman#include <sys/param.h> 331902Swollman#include <sys/systm.h> 341902Swollman#include <sys/bus.h> 35136582Sobrien#include <sys/kernel.h> 3674462Salfred#include <sys/lock.h> 371902Swollman#include <sys/mutex.h> 3892986Sobrien 3992986Sobrien#include <machine/cpufunc.h> 401902Swollman#include <mips/rmi/msgring.h> 411902Swollman#include <mips/rmi/rmi_boot_info.h> 4274462Salfred#include <mips/rmi/board.h> 431902Swollman#include <mips/rmi/pic.h> 441902Swollman 451902Swollman#define XLR_I2C_RTC_ADDR 0xd0 461902Swollman#define XLR_I2C_EEPROM_ADDR 0xa0 471902Swollman#define XLR_I2C_TEMPSENSOR_ADDR 0x98 481902Swollman#define XLR_I2C_ATX8_TEMPSENSOR_ADDR 0x9a 4974462Salfred 501902Swollmanstruct stn_cc *xlr_core_cc_configs[] = { &cc_table_cpu_0, &cc_table_cpu_1, 511902Swollman &cc_table_cpu_2, &cc_table_cpu_3, &cc_table_cpu_4, &cc_table_cpu_5, 5274462Salfred &cc_table_cpu_6, &cc_table_cpu_7}; 5374462Salfred 5474462Salfredstruct stn_cc *xls_core_cc_configs[] = { &xls_cc_table_cpu_0, &xls_cc_table_cpu_1, 551902Swollman &xls_cc_table_cpu_2, &xls_cc_table_cpu_3 }; 561902Swollman 5774462Salfredstruct xlr_board_info xlr_board_info; 581902Swollman 591902Swollmanstatic int 601902Swollmanxlr_pcmcia_present(void) 6121062Speter{ 621902Swollman xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); 631902Swollman uint32_t resetconf; 6421062Speter 6521062Speter resetconf = xlr_read_reg(mmio, 21); 66129201Scognet return ((resetconf & 0x4000) != 0); 67114322Speter} 6821062Speter 691902Swollmanstatic void 701902Swollmanxlr_chip_specific_overrides(struct xlr_board_info* board) 711902Swollman{ 7274462Salfred struct xlr_gmac_block_t *blk0, *blk1, *blk2; 731902Swollman uint32_t chipid; 741902Swollman uint32_t revision; 751902Swollman 761902Swollman blk0 = &board->gmac_block[0]; 771902Swollman blk1 = &board->gmac_block[1]; 781902Swollman blk2 = &board->gmac_block[2]; 791902Swollman 801902Swollman chipid = xlr_processor_id(); 811902Swollman revision = xlr_revision(); 821902Swollman 831902Swollman if (revision == 0x04) { /* B2 */ 841902Swollman switch (chipid) { 851902Swollman case 0x07: /* XLR 508 */ 861902Swollman case 0x08: /* XLR 516 */ 871902Swollman case 0x09: /* XLR 532 */ 881902Swollman /* NA[12] not available */ 891902Swollman memset(blk1, 0, sizeof(*blk1)); 901902Swollman memset(blk2, 0, sizeof(*blk2)); 911902Swollman break; 921902Swollman case 0x06: /* XLR 308 */ 931902Swollman /* NA0 has 3 ports */ 941902Swollman blk0->gmac_port[3].valid = 0; 951902Swollman blk0->num_ports--; 961902Swollman /* NA[12] not available */ 971902Swollman memset(blk1, 0, sizeof(*blk1)); 981902Swollman memset(blk2, 0, sizeof(*blk2)); 991902Swollman break; 1001902Swollman default: 1011902Swollman break; 1021902Swollman } 1031902Swollman } else if (revision == 0x91) { /* C4 */ 1041902Swollman switch (chipid) { 10574462Salfred case 0x0B: /* XLR 508 */ 10674462Salfred case 0x0A: /* XLR 516 */ 1071902Swollman case 0x08: /* XLR 532 */ 10874462Salfred /* NA[12] not available */ 1091902Swollman memset(blk1, 0, sizeof(*blk1)); 1101902Swollman memset(blk2, 0, sizeof(*blk2)); 1111902Swollman break; 1121902Swollman case 0x0F: /* XLR 308 */ 1131902Swollman /* NA0 has 3 ports */ 1141902Swollman blk0->gmac_port[3].valid = 0; 1151902Swollman blk0->num_ports--; 1161902Swollman /* NA[12] not available */ 1178870Srgrimes memset(blk1, 0, sizeof(*blk1)); 11874462Salfred memset(blk2, 0, sizeof(*blk2)); 1191902Swollman break; 1201902Swollman default: 1211902Swollman break; 1221902Swollman } 1231902Swollman } else { /* other pre-production silicon */ 1241902Swollman switch (chipid) { 1251902Swollman /* XLR 5xx */ 1261902Swollman case 0x0B: 1271902Swollman case 0x0A: 1281902Swollman case 0x07: 1291902Swollman case 0x08: 1301902Swollman case 0x09: 1311902Swollman /* NA[12] not available */ 1321902Swollman memset(blk1, 0, sizeof(*blk1)); 1331902Swollman memset(blk2, 0, sizeof(*blk2)); 1341902Swollman break; 13574462Salfred /* XLR 3xx */ 1361902Swollman case 0x0F: 1371902Swollman case 0x06: 1381902Swollman /* NA0 has 3 ports */ 1391902Swollman blk0->gmac_port[3].valid = 0; 14074462Salfred blk0->num_ports--; 1411902Swollman /* NA[12] not available */ 1421902Swollman memset(blk1, 0, sizeof(*blk1)); 14374462Salfred memset(blk2, 0, sizeof(*blk2)); 1441902Swollman break; 1451902Swollman default: 1461902Swollman break; 1471902Swollman } 1481902Swollman } 1491902Swollman} 1501902Swollman 1511902Swollmanstatic void 1521902Swollmanxlr_board_specific_overrides(struct xlr_board_info* board) 1531902Swollman{ 1541902Swollman struct xlr_gmac_block_t *blk1, *blk2; 1551902Swollman 1561902Swollman blk1 = &board->gmac_block[1]; 1571902Swollman blk2 = &board->gmac_block[2]; 1581902Swollman 1591902Swollman switch (xlr_boot1_info.board_major_version) { 1601902Swollman case RMI_XLR_BOARD_ARIZONA_I: 1611902Swollman /* ATX-I has SPI-4, not XGMAC */ 1621902Swollman blk1->type = XLR_SPI4; 1631902Swollman blk1->enabled = 0; /* nlge does not 1641902Swollman support SPI-4 */ 16574462Salfred blk2->type = XLR_SPI4; 1661902Swollman blk2->enabled = 0; 1671902Swollman break; 1681902Swollman 16974462Salfred case RMI_XLR_BOARD_ARIZONA_II: 1701902Swollman /* XGMII_A --> VSC7281, XGMII_B --> VSC7281 */ 1711902Swollman blk1->enabled = 1; 1721902Swollman blk1->num_ports = 1; 1731902Swollman blk1->gmac_port[0].valid = 1; 1741902Swollman 1751902Swollman blk2->enabled = 1; 1761902Swollman blk2->num_ports = 1; 1771902Swollman blk2->gmac_port[0].valid = 1; 1781902Swollman default: 1791902Swollman break; 1801902Swollman } 1811902Swollman} 1821902Swollman 1831902Swollmanstatic int 1841902Swollmanquad0_xaui(void) 1851902Swollman{ 1861902Swollman xlr_reg_t *gpio_mmio = 1871902Swollman (unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET); 1881902Swollman uint32_t bit24; 1891902Swollman 1901902Swollman bit24 = (xlr_read_reg(gpio_mmio, 0x15) >> 24) & 0x1; 1911902Swollman return (bit24); 1921902Swollman} 1931902Swollman 1941902Swollmanstatic int 1951902Swollmanquad1_xaui(void) 1961902Swollman{ 1971902Swollman xlr_reg_t *gpio_mmio = 1981902Swollman (unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET); 1991902Swollman uint32_t bit25; 2001902Swollman 2011902Swollman bit25 = (xlr_read_reg(gpio_mmio, 0x15) >> 25) & 0x1; 2021902Swollman return (bit25); 2031902Swollman} 2041902Swollman 2051902Swollmanstatic void 2061902Swollmanxls_chip_specific_overrides(struct xlr_board_info* board) 20774462Salfred{ 2081902Swollman struct xlr_gmac_block_t *blk0, *blk1; 2091902Swollman uint32_t chipid; 21021062Speter 21174462Salfred blk0 = &board->gmac_block[0]; 21221062Speter blk1 = &board->gmac_block[1]; 21321062Speter chipid = xlr_processor_id(); 21474462Salfred 2151902Swollman switch (chipid) { 2161902Swollman case 0x8E: /* XLS208 */ 21774462Salfred case 0x8F: /* XLS204 */ 2181902Swollman /* NA1 is not available */ 2191902Swollman memset(blk1, 0, sizeof(*blk1)); 2201902Swollman break; 2211902Swollman case 0xCE: /* XLS108 */ 2221902Swollman case 0xCF: /* XLS104 */ 2231902Swollman /* NA0 has 3 ports */ 2241902Swollman blk0->gmac_port[3].valid = 0; 22574462Salfred blk0->num_ports--; 2261902Swollman /* NA1 is not available */ 22774462Salfred memset(blk1, 0, sizeof(*blk1)); 22821062Speter break; 22921062Speter default: 23074462Salfred break; 2311902Swollman } 23274462Salfred} 23321062Speter 23421062Speterstatic void 23574462Salfredxls_board_specific_overrides(struct xlr_board_info* board) 2361902Swollman{ 23721062Speter struct xlr_gmac_block_t *blk0, *blk1; 2381902Swollman int i; 2391902Swollman struct xlr_i2c_dev_t* iic_blk; 2401902Swollman 2411902Swollman blk0 = &board->gmac_block[0]; 2421902Swollman blk1 = &board->gmac_block[1]; 2431902Swollman 2441902Swollman switch (xlr_boot1_info.board_major_version) { 2451902Swollman case RMI_XLR_BOARD_ARIZONA_VI: 2461902Swollman blk0->mode = XLR_PORT0_RGMII; 2471902Swollman blk0->gmac_port[0].type = XLR_RGMII; 2481902Swollman blk0->gmac_port[0].phy_addr = 0; 2491902Swollman blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_4_OFFSET; 2501902Swollman /* Because of the Octal PHY, SGMII Quad1 is MII is also bound 2511902Swollman * to the PHY attached to SGMII0_MDC/MDIO/MDINT. */ 2521902Swollman for (i = 0; i < 4; i++) { 2531902Swollman blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET; 2541902Swollman blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET; 2551902Swollman } 2561902Swollman blk1->gmac_port[1].mii_addr = XLR_IO_GMAC_0_OFFSET; 2571902Swollman blk1->gmac_port[2].mii_addr = XLR_IO_GMAC_0_OFFSET; 2581902Swollman blk1->gmac_port[3].mii_addr = XLR_IO_GMAC_0_OFFSET; 25974462Salfred 26074462Salfred blk1->gmac_port[1].serdes_addr = XLR_IO_GMAC_0_OFFSET; 2611902Swollman blk1->gmac_port[2].serdes_addr = XLR_IO_GMAC_0_OFFSET; 2621902Swollman blk1->gmac_port[3].serdes_addr = XLR_IO_GMAC_0_OFFSET; 2631902Swollman 2641902Swollman /* RGMII MDIO interrupt is thru NA1 and SGMII MDIO 26574462Salfred * interrupts for ports in blk1 are from NA0 */ 2661902Swollman blk0->gmac_port[0].mdint_id = 1; 26774462Salfred 26821062Speter blk1->gmac_port[0].mdint_id = 0; 26921062Speter blk1->gmac_port[1].mdint_id = 0; 27074462Salfred blk1->gmac_port[2].mdint_id = 0; 2711902Swollman blk1->gmac_port[3].mdint_id = 0; 27274462Salfred 27321062Speter /* If we have a 4xx lite chip, don't enable the 27421062Speter * GMACs which are disabled in hardware */ 27574462Salfred if (xlr_is_xls4xx_lite()) { 2761902Swollman xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); 27721062Speter uint32_t tmp; 2781902Swollman 27974462Salfred /* Port 6 & 7 are not enabled on the condor 4xx, figure 28074462Salfred * this out from the GPIO fuse bank */ 2811902Swollman tmp = xlr_read_reg(mmio, 35); 2821902Swollman if ((tmp & (3 << 28)) != 0) { 2831902Swollman blk1->enabled = 0x3; 2841902Swollman blk1->gmac_port[2].valid = 0; 2851902Swollman blk1->gmac_port[3].valid = 0; 2861902Swollman blk1->num_ports = 2; 2871902Swollman } 2881902Swollman } 2891902Swollman break; 2901902Swollman 2911902Swollman case RMI_XLR_BOARD_ARIZONA_VIII: 2921902Swollman iic_blk = &xlr_board_info.xlr_i2c_device[I2C_THERMAL]; 2931902Swollman if (iic_blk->enabled) { 2941902Swollman iic_blk->addr = XLR_I2C_ATX8_TEMPSENSOR_ADDR; 2951902Swollman } 2961902Swollman if (blk1->enabled) { 2971902Swollman /* There is just one Octal PHY on the board and it is 2981902Swollman * connected to the MII interface for NA Quad 0. */ 2991902Swollman for (i = 0; i < 4; i++) { 3001902Swollman blk1->gmac_port[i].mii_addr = 3011902Swollman XLR_IO_GMAC_0_OFFSET; 3021902Swollman blk1->gmac_port[i].mdint_id = 0; 3031902Swollman } 3041902Swollman } 3051902Swollman break; 3061902Swollman 30774462Salfred case RMI_XLR_BOARD_ARIZONA_XI: 3081902Swollman case RMI_XLR_BOARD_ARIZONA_XII: 3091902Swollman if (quad0_xaui()) { /* GMAC ports 0-3 are set to XAUI */ 310 /* only GMAC0 is active i.e, the 0-th port on this quad. 311 * Disable all the other 7 possible ports. */ 312 for (i = 1; i < MAX_NA_PORTS; i++) { 313 memset(&blk0->gmac_port[i], 0, 314 sizeof(blk0->gmac_port[i])); 315 } 316 /* Setup for XAUI on N/w Acc0: gmac0 */ 317 blk0->type = XLR_XGMAC; 318 blk0->mode = XLR_XAUI; 319 blk0->num_ports = 1; 320 blk0->gmac_port[0].type = XLR_XAUI; 321 blk1->gmac_port[0].phy_addr = 16; 322 blk0->gmac_port[0].tx_bucket_id = blk0->station_txbase; 323 /* Other addresses etc need not be modified as XAUI_0 324 * shares its addresses with SGMII GMAC_0, which was 325 * set in the caller. */ 326 } 327 else { 328 blk0->num_ports = 1; /* only 1 RGMII port */ 329 blk0->mode = XLR_PORT0_RGMII; 330 blk0->gmac_port[0].type = XLR_RGMII; 331 blk0->gmac_port[0].phy_addr = 0; 332 blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_0_OFFSET; 333 } 334 335 if (quad1_xaui()) { /* GMAC ports 4-7 are used for XAUI */ 336 /* only GMAC4 is active i.e, the 0-th port on this quad. 337 * Disable all the other 7 possible ports. */ 338 for (i = 1; i < MAX_NA_PORTS; i++) { 339 memset(&blk1->gmac_port[i], 0, 340 sizeof(blk1->gmac_port[i])); 341 } 342 /* Setup for XAUI on N/w Acc1: gmac4 */ 343 blk1->type = XLR_XGMAC; 344 blk1->mode = XLR_XAUI; 345 blk1->num_ports = 1; 346 /* XAUI and SGMII ports share FMN buckets on N/w Acc 1; 347 so, station_txbase, station_rfr need not be 348 patched up. */ 349 blk1->gmac_port[0].type = XLR_XAUI; 350 blk1->gmac_port[0].phy_addr = 16; 351 blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase; 352 /* Other addresses etc need not be modified as XAUI_1 353 * shares its addresses with SGMII GMAC_4, which was 354 * set in the caller. */ 355 } 356 break; 357 358 default: 359 break; 360 } 361} 362 363/* 364 * All our knowledge of chip and board that cannot be detected by probing 365 * at run-time goes here 366 */ 367int 368xlr_board_info_setup() 369{ 370 struct xlr_gmac_block_t *blk0, *blk1, *blk2; 371 struct xlr_i2c_dev_t* iic_blk; 372 int i; 373 374 /* This setup code is long'ish because the same base driver 375 * (if_nlge.c) is used for different: 376 * - CPUs (XLR/XLS) 377 * - boards (for each CPU, multiple board configs are possible 378 * and available). 379 * 380 * At the time of writing, there are atleast 12 boards, 4 with XLR 381 * and 8 with XLS. This means that the base driver needs to work with 382 * 12 different configurations, with varying levels of differences. 383 * To accomodate the different configs, the xlr_board_info struct 384 * has various attributes for paramters that could be different. 385 * These attributes are setup here and can be used directly in the 386 * base driver. 387 * It was seen that the setup code is not entirely trivial and 388 * it is possible to organize it in different ways. In the following, 389 * we choose an approach that sacrifices code-compactness/speed for 390 * readability. This is because configuration code executes once 391 * per reboot and hence has a minimal performance impact. 392 * On the other hand, driver debugging/enhancements require 393 * that different engineers can quickly comprehend the setup 394 * sequence. Hence, readability is seen as the key requirement for 395 * this code. It is for the reader to decide how much of this 396 * requirement is met with the current code organization !! 397 * 398 * The initialization is organized thus: 399 * 400 * if (CPU is XLS) { 401 * // initialize per XLS architecture 402 * // default inits (per chip spec) 403 * // chip-specific overrides 404 * // board-specific overrides 405 * } else if (CPU is XLR) { 406 * // initialize per XLR architecture 407 * // default inits (per chip spec) 408 * // chip-specific overrides 409 * // board-specific overrides 410 * } 411 * 412 * For each CPU family, all the default initializations 413 * are done for a fully-loaded device of that family. 414 * This configuration is then adjusted for the actual 415 * chip id. This is followed up with board specific 416 * overrides. 417 */ 418 419 /* start with a clean slate */ 420 memset(&xlr_board_info, 0, sizeof(xlr_board_info)); 421 xlr_board_info.ata = xlr_pcmcia_present(); 422 423 blk0 = &xlr_board_info.gmac_block[0]; 424 blk1 = &xlr_board_info.gmac_block[1]; 425 blk2 = &xlr_board_info.gmac_block[2]; 426 427 iic_blk = xlr_board_info.xlr_i2c_device; 428 iic_blk[I2C_RTC].enabled = 1; 429 iic_blk[I2C_RTC].addr = XLR_I2C_RTC_ADDR; 430 iic_blk[I2C_THERMAL].enabled = 1; 431 iic_blk[I2C_THERMAL].addr = XLR_I2C_TEMPSENSOR_ADDR; 432 iic_blk[I2C_EEPROM].enabled = 1; 433 iic_blk[I2C_EEPROM].addr = XLR_I2C_EEPROM_ADDR; 434 435 if (xlr_is_xls()) { 436 xlr_board_info.is_xls = 1; 437 xlr_board_info.nr_cpus = 8; 438 xlr_board_info.usb = 1; 439 /* Board version 8 has NAND flash */ 440 xlr_board_info.cfi = 441 (xlr_boot1_info.board_major_version != RMI_XLR_BOARD_ARIZONA_VIII); 442 xlr_board_info.pci_irq = 0; 443 xlr_board_info.credit_configs = xls_core_cc_configs; 444 xlr_board_info.bucket_sizes = &xls_bucket_sizes; 445 xlr_board_info.gmacports = MAX_NA_PORTS; 446 447 /* ---------------- Network Acc 0 ---------------- */ 448 449 blk0->type = XLR_GMAC; 450 blk0->enabled = 0xf; 451 blk0->credit_config = &xls_cc_table_gmac0; 452 blk0->station_id = MSGRNG_STNID_GMAC; 453 blk0->station_txbase = MSGRNG_STNID_GMACTX0; 454 blk0->station_rfr = MSGRNG_STNID_GMACRFR_0; 455 blk0->mode = XLR_SGMII; 456 blk0->baseaddr = XLR_IO_GMAC_0_OFFSET; 457 blk0->baseirq = PIC_GMAC_0_IRQ; 458 blk0->baseinst = 0; 459 460 /* By default, assume SGMII is setup. But this can change based 461 on board-specific or setting-specific info. */ 462 for (i = 0; i < 4; i++) { 463 blk0->gmac_port[i].valid = 1; 464 blk0->gmac_port[i].instance = i + blk0->baseinst; 465 blk0->gmac_port[i].type = XLR_SGMII; 466 blk0->gmac_port[i].phy_addr = i + 16; 467 blk0->gmac_port[i].tx_bucket_id = 468 blk0->station_txbase + i; 469 blk0->gmac_port[i].mdint_id = 0; 470 blk0->num_ports++; 471 blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000; 472 blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET; 473 blk0->gmac_port[i].pcs_addr = XLR_IO_GMAC_0_OFFSET; 474 blk0->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET; 475 } 476 477 /* ---------------- Network Acc 1 ---------------- */ 478 blk1->type = XLR_GMAC; 479 blk1->enabled = 0xf; 480 blk1->credit_config = &xls_cc_table_gmac1; 481 blk1->station_id = MSGRNG_STNID_GMAC1; 482 blk1->station_txbase = MSGRNG_STNID_GMAC1_TX0; 483 blk1->station_rfr = MSGRNG_STNID_GMAC1_FR_0; 484 blk1->mode = XLR_SGMII; 485 blk1->baseaddr = XLR_IO_GMAC_4_OFFSET; 486 blk1->baseirq = PIC_XGS_0_IRQ; 487 blk1->baseinst = 4; 488 489 for (i = 0; i < 4; i++) { 490 blk1->gmac_port[i].valid = 1; 491 blk1->gmac_port[i].instance = i + blk1->baseinst; 492 blk1->gmac_port[i].type = XLR_SGMII; 493 blk1->gmac_port[i].phy_addr = i + 20; 494 blk1->gmac_port[i].tx_bucket_id = 495 blk1->station_txbase + i; 496 blk1->gmac_port[i].mdint_id = 1; 497 blk1->num_ports++; 498 blk1->gmac_port[i].base_addr = XLR_IO_GMAC_4_OFFSET + i * 0x1000; 499 blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_4_OFFSET; 500 blk1->gmac_port[i].pcs_addr = XLR_IO_GMAC_4_OFFSET; 501 blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET; 502 } 503 504 /* ---------------- Network Acc 2 ---------------- */ 505 xlr_board_info.gmac_block[2].enabled = 0; /* disabled on XLS */ 506 507 xls_chip_specific_overrides(&xlr_board_info); 508 xls_board_specific_overrides(&xlr_board_info); 509 510 } else { /* XLR */ 511 xlr_board_info.is_xls = 0; 512 xlr_board_info.nr_cpus = 32; 513 xlr_board_info.usb = 0; 514 xlr_board_info.cfi = 1; 515 xlr_board_info.pci_irq = 0; 516 xlr_board_info.credit_configs = xlr_core_cc_configs; 517 xlr_board_info.bucket_sizes = &bucket_sizes; 518 xlr_board_info.gmacports = 4; 519 520 /* ---------------- GMAC0 ---------------- */ 521 blk0->type = XLR_GMAC; 522 blk0->enabled = 0xf; 523 blk0->credit_config = &cc_table_gmac; 524 blk0->station_id = MSGRNG_STNID_GMAC; 525 blk0->station_txbase = MSGRNG_STNID_GMACTX0; 526 blk0->station_rfr = MSGRNG_STNID_GMACRFR_0; 527 blk0->mode = XLR_RGMII; 528 blk0->baseaddr = XLR_IO_GMAC_0_OFFSET; 529 blk0->baseirq = PIC_GMAC_0_IRQ; 530 blk0->baseinst = 0; 531 532 /* first, do the common/easy stuff for all the ports */ 533 for (i = 0; i < 4; i++) { 534 blk0->gmac_port[i].valid = 1; 535 blk0->gmac_port[i].instance = i + blk0->baseinst; 536 blk0->gmac_port[i].type = XLR_RGMII; 537 blk0->gmac_port[i].phy_addr = i; 538 blk0->gmac_port[i].tx_bucket_id = 539 blk0->station_txbase + i; 540 blk0->gmac_port[i].mdint_id = 0; 541 blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000; 542 blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET; 543 /* RGMII ports, no PCS/SERDES */ 544 blk0->num_ports++; 545 } 546 547 /* ---------------- XGMAC0 ---------------- */ 548 blk1->type = XLR_XGMAC; 549 blk1->mode = XLR_XGMII; 550 blk1->enabled = 0; 551 blk1->credit_config = &cc_table_xgs_0; 552 blk1->station_txbase = MSGRNG_STNID_XGS0_TX; 553 blk1->station_rfr = MSGRNG_STNID_XMAC0RFR; 554 blk1->station_id = MSGRNG_STNID_XGS0FR; 555 blk1->baseaddr = XLR_IO_XGMAC_0_OFFSET; 556 blk1->baseirq = PIC_XGS_0_IRQ; 557 blk1->baseinst = 4; 558 559 blk1->gmac_port[0].type = XLR_XGMII; 560 blk1->gmac_port[0].instance = 0; 561 blk1->gmac_port[0].phy_addr = 0; 562 blk1->gmac_port[0].base_addr = XLR_IO_XGMAC_0_OFFSET; 563 blk1->gmac_port[0].mii_addr = XLR_IO_XGMAC_0_OFFSET; 564 blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase; 565 blk1->gmac_port[0].mdint_id = 1; 566 567 /* ---------------- XGMAC1 ---------------- */ 568 blk2->type = XLR_XGMAC; 569 blk2->mode = XLR_XGMII; 570 blk2->enabled = 0; 571 blk2->credit_config = &cc_table_xgs_1; 572 blk2->station_txbase = MSGRNG_STNID_XGS1_TX; 573 blk2->station_rfr = MSGRNG_STNID_XMAC1RFR; 574 blk2->station_id = MSGRNG_STNID_XGS1FR; 575 blk2->baseaddr = XLR_IO_XGMAC_1_OFFSET; 576 blk2->baseirq = PIC_XGS_1_IRQ; 577 blk2->baseinst = 5; 578 579 blk2->gmac_port[0].type = XLR_XGMII; 580 blk2->gmac_port[0].instance = 0; 581 blk2->gmac_port[0].phy_addr = 0; 582 blk2->gmac_port[0].base_addr = XLR_IO_XGMAC_1_OFFSET; 583 blk2->gmac_port[0].mii_addr = XLR_IO_XGMAC_1_OFFSET; 584 blk2->gmac_port[0].tx_bucket_id = blk2->station_txbase; 585 blk2->gmac_port[0].mdint_id = 2; 586 587 /* Done with default setup. Now handle chip and board-specific 588 variations. */ 589 xlr_chip_specific_overrides(&xlr_board_info); 590 xlr_board_specific_overrides(&xlr_board_info); 591 } 592 return 0; 593} 594