sys.h revision 224110
1224110Sjchandra/*- 2224110Sjchandra * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3224110Sjchandra * reserved. 4224110Sjchandra * 5224110Sjchandra * Redistribution and use in source and binary forms, with or without 6224110Sjchandra * modification, are permitted provided that the following conditions are 7224110Sjchandra * met: 8224110Sjchandra * 9224110Sjchandra * 1. Redistributions of source code must retain the above copyright 10224110Sjchandra * notice, this list of conditions and the following disclaimer. 11224110Sjchandra * 2. Redistributions in binary form must reproduce the above copyright 12224110Sjchandra * notice, this list of conditions and the following disclaimer in 13224110Sjchandra * the documentation and/or other materials provided with the 14224110Sjchandra * distribution. 15224110Sjchandra * 16224110Sjchandra * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17224110Sjchandra * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18224110Sjchandra * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19224110Sjchandra * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20224110Sjchandra * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21224110Sjchandra * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22224110Sjchandra * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23224110Sjchandra * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24224110Sjchandra * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25224110Sjchandra * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26224110Sjchandra * THE POSSIBILITY OF SUCH DAMAGE. 27224110Sjchandra * 28224110Sjchandra * $FreeBSD: head/sys/mips/nlm/hal/sys.h 224110 2011-07-16 19:35:44Z jchandra $ 29224110Sjchandra * NETLOGIC_BSD */ 30224110Sjchandra 31224110Sjchandra#ifndef __NLM_SYS_H__ 32224110Sjchandra#define __NLM_SYS_H__ 33224110Sjchandra 34224110Sjchandra/** 35224110Sjchandra* @file_name sys.h 36224110Sjchandra* @author Netlogic Microsystems 37224110Sjchandra* @brief HAL for System configuration registers 38224110Sjchandra*/ 39224110Sjchandra#define XLP_SYS_CHIP_RESET_REG 0x40 40224110Sjchandra#define XLP_SYS_POWER_ON_RESET_REG 0x41 41224110Sjchandra#define XLP_SYS_EFUSE_DEVICE_CFG_STATUS0_REG 0x42 42224110Sjchandra#define XLP_SYS_EFUSE_DEVICE_CFG_STATUS1_REG 0x43 43224110Sjchandra#define XLP_SYS_EFUSE_DEVICE_CFG_STATUS2_REG 0x44 44224110Sjchandra#define XLP_SYS_EFUSE_DEVICE_CFG3_REG 0x45 45224110Sjchandra#define XLP_SYS_EFUSE_DEVICE_CFG4_REG 0x46 46224110Sjchandra#define XLP_SYS_EFUSE_DEVICE_CFG5_REG 0x47 47224110Sjchandra#define XLP_SYS_EFUSE_DEVICE_CFG6_REG 0x48 48224110Sjchandra#define XLP_SYS_EFUSE_DEVICE_CFG7_REG 0x49 49224110Sjchandra#define XLP_SYS_PLL_CTRL_REG 0x4a 50224110Sjchandra#define XLP_SYS_CPU_RESET_REG 0x4b 51224110Sjchandra#define XLP_SYS_CPU_NONCOHERENT_MODE_REG 0x4d 52224110Sjchandra#define XLP_SYS_CORE_DFS_DIS_CTRL_REG 0x4e 53224110Sjchandra#define XLP_SYS_CORE_DFS_RST_CTRL_REG 0x4f 54224110Sjchandra#define XLP_SYS_CORE_DFS_BYP_CTRL_REG 0x50 55224110Sjchandra#define XLP_SYS_CORE_DFS_PHA_CTRL_REG 0x51 56224110Sjchandra#define XLP_SYS_CORE_DFS_DIV_INC_CTRL_REG 0x52 57224110Sjchandra#define XLP_SYS_CORE_DFS_DIV_DEC_CTRL_REG 0x53 58224110Sjchandra#define XLP_SYS_CORE_DFS_DIV_VALUE_REG 0x54 59224110Sjchandra#define XLP_SYS_RESET_REG 0x55 60224110Sjchandra#define XLP_SYS_DFS_DIS_CTRL_REG 0x56 61224110Sjchandra#define XLP_SYS_DFS_RST_CTRL_REG 0x57 62224110Sjchandra#define XLP_SYS_DFS_BYP_CTRL_REG 0x58 63224110Sjchandra#define XLP_SYS_DFS_DIV_INC_CTRL_REG 0x59 64224110Sjchandra#define XLP_SYS_DFS_DIV_DEC_CTRL_REG 0x5a 65224110Sjchandra#define XLP_SYS_DFS_DIV_VALUE0_REG 0x5b 66224110Sjchandra#define XLP_SYS_DFS_DIV_VALUE1_REG 0x5c 67224110Sjchandra#define XLP_SYS_SENSE_AMP_DLY_REG 0x5d 68224110Sjchandra#define XLP_SYS_SOC_SENSE_AMP_DLY_REG 0x5e 69224110Sjchandra#define XLP_SYS_CTRL0_REG 0x5f 70224110Sjchandra#define XLP_SYS_CTRL1_REG 0x60 71224110Sjchandra#define XLP_SYS_TIMEOUT_BS1_REG 0x61 72224110Sjchandra#define XLP_SYS_BYTE_SWAP_REG 0x62 73224110Sjchandra#define XLP_SYS_VRM_VID_REG 0x63 74224110Sjchandra#define XLP_SYS_PWR_RAM_CMD_REG 0x64 75224110Sjchandra#define XLP_SYS_PWR_RAM_ADDR_REG 0x65 76224110Sjchandra#define XLP_SYS_PWR_RAM_DATA0_REG 0x66 77224110Sjchandra#define XLP_SYS_PWR_RAM_DATA1_REG 0x67 78224110Sjchandra#define XLP_SYS_PWR_RAM_DATA2_REG 0x68 79224110Sjchandra#define XLP_SYS_PWR_UCODE_REG 0x69 80224110Sjchandra#define XLP_SYS_CPU0_PWR_STATUS_REG 0x6a 81224110Sjchandra#define XLP_SYS_CPU1_PWR_STATUS_REG 0x6b 82224110Sjchandra#define XLP_SYS_CPU2_PWR_STATUS_REG 0x6c 83224110Sjchandra#define XLP_SYS_CPU3_PWR_STATUS_REG 0x6d 84224110Sjchandra#define XLP_SYS_CPU4_PWR_STATUS_REG 0x6e 85224110Sjchandra#define XLP_SYS_CPU5_PWR_STATUS_REG 0x6f 86224110Sjchandra#define XLP_SYS_CPU6_PWR_STATUS_REG 0x70 87224110Sjchandra#define XLP_SYS_CPU7_PWR_STATUS_REG 0x71 88224110Sjchandra#define XLP_SYS_STATUS_REG 0x72 89224110Sjchandra#define XLP_SYS_INT_POL_REG 0x73 90224110Sjchandra#define XLP_SYS_INT_TYPE_REG 0x74 91224110Sjchandra#define XLP_SYS_INT_STATUS_REG 0x75 92224110Sjchandra#define XLP_SYS_INT_MASK0_REG 0x76 93224110Sjchandra#define XLP_SYS_INT_MASK1_REG 0x77 94224110Sjchandra#define XLP_SYS_UCO_S_ECC_REG 0x78 95224110Sjchandra#define XLP_SYS_UCO_M_ECC_REG 0x79 96224110Sjchandra#define XLP_SYS_UCO_ADDR_REG 0x7a 97224110Sjchandra#define XLP_SYS_UCO_INSTR_REG 0x7b 98224110Sjchandra#define XLP_SYS_MEM_BIST0_REG 0x7c 99224110Sjchandra#define XLP_SYS_MEM_BIST1_REG 0x7d 100224110Sjchandra#define XLP_SYS_MEM_BIST2_REG 0x7e 101224110Sjchandra#define XLP_SYS_MEM_BIST3_REG 0x7f 102224110Sjchandra#define XLP_SYS_MEM_BIST4_REG 0x80 103224110Sjchandra#define XLP_SYS_MEM_BIST5_REG 0x81 104224110Sjchandra#define XLP_SYS_MEM_BIST6_REG 0x82 105224110Sjchandra#define XLP_SYS_MEM_BIST7_REG 0x83 106224110Sjchandra#define XLP_SYS_MEM_BIST8_REG 0x84 107224110Sjchandra#define XLP_SYS_MEM_BIST9_REG 0x85 108224110Sjchandra#define XLP_SYS_MEM_BIST10_REG 0x86 109224110Sjchandra#define XLP_SYS_MEM_BIST11_REG 0x87 110224110Sjchandra#define XLP_SYS_MEM_BIST12_REG 0x88 111224110Sjchandra#define XLP_SYS_SCRTCH0_REG 0x89 112224110Sjchandra#define XLP_SYS_SCRTCH1_REG 0x8a 113224110Sjchandra#define XLP_SYS_SCRTCH2_REG 0x8b 114224110Sjchandra#define XLP_SYS_SCRTCH3_REG 0x8c 115224110Sjchandra 116224110Sjchandra#if !defined(LOCORE) && !defined(__ASSEMBLY__) 117224110Sjchandra 118224110Sjchandra#define nlm_rdreg_sys(b, r) nlm_read_reg_kseg(b,r) 119224110Sjchandra#define nlm_wreg_sys(b, r, v) nlm_write_reg_kseg(b,r,v) 120224110Sjchandra#define nlm_pcibase_sys(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) 121224110Sjchandra#define nlm_regbase_sys(node) nlm_pcibase_sys(node) 122224110Sjchandra 123224110Sjchandra#endif 124224110Sjchandra 125224110Sjchandra#endif 126