1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD 29 * $FreeBSD: releng/11.0/sys/mips/nlm/hal/iomap.h 233545 2012-03-27 14:05:12Z jchandra $ 30 */ 31 32#ifndef __NLM_HAL_IOMAP_H__ 33#define __NLM_HAL_IOMAP_H__ 34 35#define XLP_DEFAULT_IO_BASE 0x18000000 36#define NMI_BASE 0xbfc00000 37#define XLP_IO_CLK 133333333 38 39#define XLP_L2L3_CACHELINE_SIZE 64 40#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */ 41#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE) 42#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE) 43#define XLP_IO_SIZE (64 << 20) /* ECFG space size */ 44#define XLP_IO_PCI_HDRSZ 0x100 45#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) 46#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \ 47 ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12)) 48 49#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) 50/* coherent inter chip */ 51#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1) 52#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2) 53#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3) 54#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4) 55 56#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i) 57#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0) 58#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1) 59#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2) 60#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3) 61 62#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i) 63#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0) 64#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1) 65#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2) 66#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3) 67#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4) 68#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5) 69 70#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0) 71#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1) 72#define XLP_IO_SATA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 2) 73 74#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0) 75 76#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 0) 77#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1) 78#define XLP_IO_RSA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2) 79#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3) 80#define XLP_IO_SRIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 4) 81#define XLP_IO_REGEX_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 5) 82 83#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i) 84#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0) 85#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1) 86#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i) 87#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2) 88#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3) 89#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4) 90/* system management */ 91#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5) 92#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6) 93 94#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0) 95#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1) 96#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2) 97/* SD flash */ 98#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3) 99#define XLP_IO_MMC_OFFSET(node, slot) \ 100 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ) 101 102/* PCI config header register id's */ 103#define XLP_PCI_CFGREG0 0x00 104#define XLP_PCI_CFGREG1 0x01 105#define XLP_PCI_CFGREG2 0x02 106#define XLP_PCI_CFGREG3 0x03 107#define XLP_PCI_CFGREG4 0x04 108#define XLP_PCI_CFGREG5 0x05 109#define XLP_PCI_DEVINFO_REG0 0x30 110#define XLP_PCI_DEVINFO_REG1 0x31 111#define XLP_PCI_DEVINFO_REG2 0x32 112#define XLP_PCI_DEVINFO_REG3 0x33 113#define XLP_PCI_DEVINFO_REG4 0x34 114#define XLP_PCI_DEVINFO_REG5 0x35 115#define XLP_PCI_DEVINFO_REG6 0x36 116#define XLP_PCI_DEVINFO_REG7 0x37 117#define XLP_PCI_DEVSCRATCH_REG0 0x38 118#define XLP_PCI_DEVSCRATCH_REG1 0x39 119#define XLP_PCI_DEVSCRATCH_REG2 0x3a 120#define XLP_PCI_DEVSCRATCH_REG3 0x3b 121#define XLP_PCI_MSGSTN_REG 0x3c 122#define XLP_PCI_IRTINFO_REG 0x3d 123#define XLP_PCI_UCODEINFO_REG 0x3e 124#define XLP_PCI_SBB_WT_REG 0x3f 125 126/* PCI IDs for SoC device */ 127#define PCI_VENDOR_NETLOGIC 0x184e 128 129#define PCI_DEVICE_ID_NLM_ROOT 0x1001 130#define PCI_DEVICE_ID_NLM_ICI 0x1002 131#define PCI_DEVICE_ID_NLM_PIC 0x1003 132#define PCI_DEVICE_ID_NLM_PCIE 0x1004 133#define PCI_DEVICE_ID_NLM_EHCI 0x1007 134#define PCI_DEVICE_ID_NLM_ILK 0x1008 135#define PCI_DEVICE_ID_NLM_NAE 0x1009 136#define PCI_DEVICE_ID_NLM_POE 0x100A 137#define PCI_DEVICE_ID_NLM_FMN 0x100B 138#define PCI_DEVICE_ID_NLM_RAID 0x100D 139#define PCI_DEVICE_ID_NLM_SAE 0x100D 140#define PCI_DEVICE_ID_NLM_RSA 0x100E 141#define PCI_DEVICE_ID_NLM_CMP 0x100F 142#define PCI_DEVICE_ID_NLM_UART 0x1010 143#define PCI_DEVICE_ID_NLM_I2C 0x1011 144#define PCI_DEVICE_ID_NLM_NOR 0x1015 145#define PCI_DEVICE_ID_NLM_NAND 0x1016 146#define PCI_DEVICE_ID_NLM_MMC 0x1018 147 148#if !defined(LOCORE) && !defined(__ASSEMBLY__) 149 150#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) 151#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) 152 153extern uint64_t xlp_sys_base; 154extern uint64_t xlp_pic_base; 155 156static __inline__ int 157nlm_dev_exists(uint32_t devoffset) 158{ 159 uint64_t pcibase = nlm_pcicfg_base(devoffset); 160 161 return (nlm_read_reg(pcibase, XLP_PCI_CFGREG0) != 0xffffffff); 162} 163 164static __inline__ int 165nlm_qidstart(uint64_t pcibase) 166{ 167 return (nlm_read_reg(pcibase, XLP_PCI_MSGSTN_REG) & 0xffff); 168} 169 170static __inline__ int 171nlm_qnum(uint64_t pcibase) 172{ 173 return (nlm_read_reg(pcibase, XLP_PCI_MSGSTN_REG) >> 16); 174} 175 176static __inline__ int 177nlm_irtstart(uint64_t pcibase) 178{ 179 return (nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff); 180} 181 182static __inline__ int 183nlm_irtnum(uint64_t pcibase) 184{ 185 return (nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) >> 16); 186} 187 188static __inline__ int 189nlm_num_uengines(uint64_t pcibase) 190{ 191 return nlm_read_reg(pcibase, XLP_PCI_UCODEINFO_REG); 192} 193 194/* 195 * Find node on which a given Soc device is located. 196 * input is the pci device (slot) number. 197 */ 198static __inline__ int 199nlm_get_device_node(int device) 200{ 201 return (device / 8); 202} 203 204#endif /* !LOCORE or !__ASSEMBLY */ 205 206#endif /* __NLM_HAL_IOMAP_H__ */ 207