gbu.h revision 279387 
1/*-
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in
13 *    the documentation and/or other materials provided with the
14 *    distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/mips/nlm/hal/gbu.h 279387 2015-02-28 00:17:29Z jchandra $
29 */
30#ifndef _NLM_HAL_GBU_H__
31#define	_NLM_HAL_GBU_H__
32
33/* Global Bus Unit (GBU) for flash Specific registers */
34
35#define	GBU_CS_BASEADDR(cs)	(0x0+cs)
36#define	GBU_CS0_BASEADDR	0x0
37#define	GBU_CS1_BASEADDR	0x1
38#define	GBU_CS2_BASEADDR	0x2
39#define	GBU_CS3_BASEADDR	0x3
40#define	GBU_CS4_BASEADDR	0x4
41#define	GBU_CS5_BASEADDR	0x5
42#define	GBU_CS6_BASEADDR	0x6
43#define	GBU_CS7_BASEADDR	0x7
44#define	GBU_CS_BASELIMIT(cs)	(0x8+cs)
45#define	GBU_CS0_BASELIMIT	0x8
46#define	GBU_CS1_BASELIMIT	0x9
47#define	GBU_CS2_BASELIMIT	0xa
48#define	GBU_CS3_BASELIMIT	0xb
49#define	GBU_CS4_BASELIMIT	0xc
50#define	GBU_CS5_BASELIMIT	0xd
51#define	GBU_CS6_BASELIMIT	0xe
52#define	GBU_CS7_BASELIMIT	0xf
53#define	GBU_CS_DEVPARAM(cs)	(0x10+cs)
54#define	GBU_CS0_DEVPARAM	0x10
55#define	GBU_CS1_DEVPARAM	0x11
56#define	GBU_CS2_DEVPARAM	0x12
57#define	GBU_CS3_DEVPARAM	0x13
58#define	GBU_CS4_DEVPARAM	0x14
59#define	GBU_CS5_DEVPARAM	0x15
60#define	GBU_CS6_DEVPARAM	0x16
61#define	GBU_CS7_DEVPARAM	0x17
62#define	GBU_CS_DEVTIME0(cs)	(0x18+cs)
63#define	GBU_CS0_DEVTIME0	0x18
64#define	GBU_CS1_DEVTIME0	0x1a
65#define	GBU_CS2_DEVTIME0	0x1c
66#define	GBU_CS3_DEVTIME0	0x1e
67#define	GBU_CS4_DEVTIME0	0x20
68#define	GBU_CS5_DEVTIME0	0x22
69#define	GBU_CS6_DEVTIME0	0x24
70#define	GBU_CS7_DEVTIME0	0x26
71#define	GBU_CS_DEVTIME1(cs)	(0x19+cs)
72#define	GBU_CS0_DEVTIME1	0x19
73#define	GBU_CS1_DEVTIME1	0x1b
74#define	GBU_CS2_DEVTIME1	0x1d
75#define	GBU_CS3_DEVTIME1	0x1f
76#define	GBU_CS4_DEVTIME1	0x21
77#define	GBU_CS5_DEVTIME1	0x23
78#define	GBU_CS6_DEVTIME1	0x25
79#define	GBU_CS7_DEVTIME1	0x27
80#define	GBU_SYSCTRL		0x28
81#define	GBU_BYTESWAP		0x29
82#define	GBU_DI_TIMEOUT_VAL	0x2d
83#define	GBU_INTSTAT		0x2e
84#define	GBU_INTEN		0x2f
85#define	GBU_STATUS		0x30
86#define	GBU_ERRLOG0		0x2a
87#define	GBU_ERRLOG1		0x2b
88#define	GBU_ERRLOG2		0x2c
89
90#if !defined(LOCORE) && !defined(__ASSEMBLY__)
91
92#define	nlm_read_gbu_reg(b, r)		nlm_read_reg(b, r)
93#define	nlm_write_gbu_reg(b, r, v)	nlm_write_reg(b, r, v)
94#define	nlm_get_gbu_pcibase(node)	\
95				nlm_pcicfg_base(XLP_IO_NOR_OFFSET(node))
96#define	nlm_get_gbu_regbase(node)	\
97				(nlm_get_gbu_pcibase(node) + XLP_IO_PCI_HDRSZ)
98
99#endif /* !LOCORE && !__ASSEMBLY__ */
100#endif /* _NLM_HAL_GBU_H__ */
101