uart_dev_mtk.h revision 297669
1/*- 2 * Copyright (c) 2010 Aleksandr Rybalko. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or 6 * without modification, are permitted provided that the following 7 * conditions are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above 11 * copyright notice, this list of conditions and the following 12 * disclaimer in the documentation and/or other materials provided 13 * with the distribution. 14 * 3. The names of the authors may not be used to endorse or promote 15 * products derived from this software without specific prior 16 * written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 20 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 21 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 25 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 27 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 29 * OF SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/mips/mediatek/uart_dev_mtk.h 297669 2016-04-07 11:16:32Z sgalabov $ 32 */ 33#ifndef _MTKUART_H 34#define _MTKUART_H 35 36#undef uart_getreg 37#undef uart_setreg 38#define uart_getreg(bas, reg) \ 39 bus_space_read_4((bas)->bst, (bas)->bsh, reg) 40#define uart_setreg(bas, reg, value) \ 41 bus_space_write_4((bas)->bst, (bas)->bsh, reg, value) 42 43/* UART registers */ 44#define UART_RX_REG 0x00 45#define UART_TX_REG 0x04 46 47#define UART_IER_REG 0x08 48#define UART_IER_EDSSI (1<<3) /* Only full UART */ 49#define UART_IER_ELSI (1<<2) 50#define UART_IER_ETBEI (1<<1) 51#define UART_IER_ERBFI (1<<0) 52 53#define UART_IIR_REG 0x0c 54#define UART_IIR_RXFIFO (1<<7) 55#define UART_IIR_TXFIFO (1<<6) 56#define UART_IIR_ID_MST 0 57#define UART_IIR_ID_THRE 1 58#define UART_IIR_ID_DR 2 59#define UART_IIR_ID_LINESTATUS 3 60#define UART_IIR_ID_DR2 6 61#define UART_IIR_ID_SHIFT 1 62#define UART_IIR_ID_MASK 0x0000000e 63#define UART_IIR_INTP (1<<0) 64 65#define UART_FCR_REG 0x10 66#define UART_FCR_RXTGR_1 (0<<6) 67#define UART_FCR_RXTGR_4 (1<<6) 68#define UART_FCR_RXTGR_8 (2<<6) 69#define UART_FCR_RXTGR_12 (3<<6) 70#define UART_FCR_TXTGR_1 (0<<4) 71#define UART_FCR_TXTGR_4 (1<<4) 72#define UART_FCR_TXTGR_8 (2<<4) 73#define UART_FCR_TXTGR_12 (3<<4) 74#define UART_FCR_DMA (1<<3) 75#define UART_FCR_TXRST (1<<2) 76#define UART_FCR_RXRST (1<<1) 77#define UART_FCR_FIFOEN (1<<0) 78 79#define UART_LCR_REG 0x14 80#define UART_LCR_DLAB (1<<7) 81#define UART_LCR_BRK (1<<6) 82#define UART_LCR_FPAR (1<<5) 83#define UART_LCR_EVEN (1<<4) 84#define UART_LCR_PEN (1<<3) 85#define UART_LCR_STB_15 (1<<2) 86#define UART_LCR_5B 0 87#define UART_LCR_6B 1 88#define UART_LCR_7B 2 89#define UART_LCR_8B 3 90 91#define UART_MCR_REG 0x18 92#define UART_MCR_LOOP (1<<4) 93#define UART_MCR_OUT2_L (1<<3) /* Only full UART */ 94#define UART_MCR_OUT1_L (1<<2) /* Only full UART */ 95#define UART_MCR_RTS_L (1<<1) /* Only full UART */ 96#define UART_MCR_DTR_L (1<<0) /* Only full UART */ 97 98#define UART_LSR_REG 0x1c 99#define UART_LSR_ERINF (1<<7) 100#define UART_LSR_TEMT (1<<6) 101#define UART_LSR_THRE (1<<5) 102#define UART_LSR_BI (1<<4) 103#define UART_LSR_FE (1<<3) 104#define UART_LSR_PE (1<<2) 105#define UART_LSR_OE (1<<1) 106#define UART_LSR_DR (1<<0) 107 108#define UART_MSR_REG 0x20 /* Only full UART */ 109#define UART_MSR_DCD (1<<7) /* Only full UART */ 110#define UART_MSR_RI (1<<6) /* Only full UART */ 111#define UART_MSR_DSR (1<<5) /* Only full UART */ 112#define UART_MSR_CTS (1<<4) /* Only full UART */ 113#define UART_MSR_DDCD (1<<3) /* Only full UART */ 114#define UART_MSR_TERI (1<<2) /* Only full UART */ 115#define UART_MSR_DDSR (1<<1) /* Only full UART */ 116#define UART_MSR_DCTS (1<<0) /* Only full UART */ 117 118#define UART_CDDL_REG 0x28 119#define UART_CDDLL_REG 0x2c 120#define UART_CDDLH_REG 0x30 121 122#define UART_IFCTL_REG 0x34 123#define UART_IFCTL_IFCTL (1<<0) 124 125int uart_cnattach(void); 126#endif /* _MTKUART_H */ 127