1297717Ssgalabov/*- 2297717Ssgalabov * Copyright (c) 2016 Stanislav Galabov. 3297717Ssgalabov * All rights reserved. 4297717Ssgalabov * 5297717Ssgalabov * Redistribution and use in source and binary forms, with or without 6297717Ssgalabov * modification, are permitted provided that the following conditions 7297717Ssgalabov * are met: 8297717Ssgalabov * 1. Redistributions of source code must retain the above copyright 9297717Ssgalabov * notice, this list of conditions and the following disclaimer. 10297717Ssgalabov * 2. Redistributions in binary form must reproduce the above copyright 11297717Ssgalabov * notice, this list of conditions and the following disclaimer in the 12297717Ssgalabov * documentation and/or other materials provided with the distribution. 13297717Ssgalabov * 14297717Ssgalabov * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15297717Ssgalabov * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16297717Ssgalabov * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17297717Ssgalabov * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18297717Ssgalabov * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19297717Ssgalabov * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20297717Ssgalabov * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21297717Ssgalabov * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22297717Ssgalabov * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23297717Ssgalabov * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24297717Ssgalabov * SUCH DAMAGE. 25297717Ssgalabov * 26297717Ssgalabov * $FreeBSD: releng/11.0/sys/mips/mediatek/mtk_pcie.h 297850 2016-04-12 07:21:22Z sgalabov $ 27297717Ssgalabov */ 28297717Ssgalabov#ifndef __MTK_PCIE_H__ 29297717Ssgalabov#define __MTK_PCIE_H__ 30297717Ssgalabov 31297717Ssgalabov#define MTK_PCI_NIRQS 3 32297717Ssgalabov#define MTK_PCI_BASESLOT 0 33297717Ssgalabov 34297717Ssgalabovstruct mtk_pci_softc { 35297717Ssgalabov device_t sc_dev; 36297717Ssgalabov 37297717Ssgalabov struct resource * pci_res[MTK_PCI_NIRQS + 1]; 38297717Ssgalabov void * pci_intrhand[MTK_PCI_NIRQS]; 39297717Ssgalabov 40297717Ssgalabov int sc_busno; 41297717Ssgalabov int sc_cur_secbus; 42297717Ssgalabov 43297717Ssgalabov struct rman sc_mem_rman; 44297717Ssgalabov struct rman sc_io_rman; 45297717Ssgalabov struct rman sc_irq_rman; 46297717Ssgalabov 47297717Ssgalabov uint32_t sc_num_irq; 48297717Ssgalabov uint32_t sc_irq_start; 49297717Ssgalabov uint32_t sc_irq_end; 50297717Ssgalabov 51297717Ssgalabov bus_addr_t sc_mem_base; 52297717Ssgalabov bus_addr_t sc_mem_size; 53297717Ssgalabov 54297717Ssgalabov bus_addr_t sc_io_base; 55297717Ssgalabov bus_addr_t sc_io_size; 56297717Ssgalabov 57297717Ssgalabov struct intr_event *sc_eventstab[MTK_PCI_NIRQS]; 58297717Ssgalabov 59297717Ssgalabov uint32_t pcie_link_status; 60297717Ssgalabov uint32_t num_slots; 61297717Ssgalabov uint32_t socid; 62297717Ssgalabov uint32_t addr_mask; 63297717Ssgalabov}; 64297717Ssgalabov 65297717Ssgalabov#define MTK_PCI_PCICFG 0x0000 66297717Ssgalabov#define MTK_PCI_RESET (1<<1) 67297717Ssgalabov#define MTK_PCI_PCIINT 0x0008 68297717Ssgalabov#define MTK_PCI_PCIENA 0x000C 69297717Ssgalabov#define MTK_PCI_CFGADDR 0x0020 70297717Ssgalabov#define MTK_PCI_CFGDATA 0x0024 71297717Ssgalabov#define MTK_PCI_MEMBASE 0x0028 72297717Ssgalabov#define MTK_PCI_IOBASE 0x002C 73297717Ssgalabov#define MTK_PCI_ARBCTL 0x0080 74297717Ssgalabov#define MTK_PCI_PHY0_CFG 0x0090 75297717Ssgalabov 76297717Ssgalabov#define MTK_PCI_PCIE0_BAR0SETUP 0x2010 77297717Ssgalabov#define MTK_PCI_PCIE0_BAR1SETUP 0x2014 78297717Ssgalabov#define MTK_PCI_PCIE0_IMBASEBAR0 0x2018 79297717Ssgalabov#define MTK_PCI_PCIE0_ID 0x2030 80297717Ssgalabov#define MTK_PCI_PCIE0_CLASS 0x2034 81297717Ssgalabov#define MTK_PCI_PCIE0_SUBID 0x2038 82297717Ssgalabov#define MTK_PCI_PCIE0_STATUS 0x2050 83297717Ssgalabov#define MTK_PCI_PCIE0_DLECR 0x2060 84297717Ssgalabov#define MTK_PCI_PCIE0_ECRC 0x2064 85297717Ssgalabov 86297717Ssgalabov#define MTK_PCIE_BAR0SETUP(_s) (MTK_PCI_PCIE0_BAR0SETUP + (_s)*0x1000) 87297717Ssgalabov#define MTK_PCIE_BAR1SETUP(_s) (MTK_PCI_PCIE0_BAR1SETUP + (_s)*0x1000) 88297717Ssgalabov#define MTK_PCIE_IMBASEBAR0(_s) (MTK_PCI_PCIE0_IMBASEBAR0 + (_s)*0x1000) 89297717Ssgalabov#define MTK_PCIE_ID(_s) (MTK_PCI_PCIE0_ID + (_s)*0x1000) 90297717Ssgalabov#define MTK_PCIE_CLASS(_s) (MTK_PCI_PCIE0_CLASS + (_s)*0x1000) 91297717Ssgalabov#define MTK_PCIE_SUBID(_s) (MTK_PCI_PCIE0_SUBID + (_s)*0x1000) 92297717Ssgalabov#define MTK_PCIE_STATUS(_s) (MTK_PCI_PCIE0_STATUS + (_s)*0x1000) 93297717Ssgalabov 94297717Ssgalabov#define MTK_PCIE0_IRQ 20 95297717Ssgalabov#define MTK_PCIE1_IRQ 21 96297717Ssgalabov#define MTK_PCIE2_IRQ 22 97297717Ssgalabov 98297717Ssgalabov#define MTK_PCI_INTR_PIN 2 99297717Ssgalabov 100297717Ssgalabov/* Chip specific defines */ 101297717Ssgalabov#define MT7620_MAX_RETRIES 10 102297717Ssgalabov#define MT7620_PCIE_PHY_CFG 0x90 103297717Ssgalabov#define PHY_BUSY (1<<31) 104297717Ssgalabov#define PHY_MODE_WRITE (1<<23) 105297717Ssgalabov#define PHY_ADDR_OFFSET 8 106297717Ssgalabov#define MT7620_PPLL_CFG0 0x98 107297717Ssgalabov#define PPLL_SW_SET (1<<31) 108297717Ssgalabov#define MT7620_PPLL_CFG1 0x9c 109297717Ssgalabov#define PPLL_PD (1<<26) 110297717Ssgalabov#define PPLL_LOCKED (1<<23) 111297717Ssgalabov#define MT7620_PPLL_DRV 0xa0 112297717Ssgalabov#define PDRV_SW_SET (1<<31) 113297717Ssgalabov#define LC_CKDRVPD (1<<19) 114297717Ssgalabov#define LC_CKDRVOHZ (1<<18) 115297717Ssgalabov#define LC_CKDRVHZ (1<<17) 116297717Ssgalabov#define MT7620_PERST_GPIO_MODE (3<<16) 117297717Ssgalabov#define MT7620_PERST (0<<16) 118297717Ssgalabov#define MT7620_GPIO (2<<16) 119297717Ssgalabov#define MT7620_PKG_BGA (1<<16) 120297717Ssgalabov 121297717Ssgalabov#define MT7628_PERST_GPIO_MODE (1<<16) 122297717Ssgalabov#define MT7628_PERST (0<<16) 123297717Ssgalabov 124297717Ssgalabov#define MT7621_PERST_GPIO_MODE (3<<10) 125297717Ssgalabov#define MT7621_PERST_GPIO (1<<10) 126297717Ssgalabov#define MT7621_UARTL3_GPIO_MODE (3<<3) 127297717Ssgalabov#define MT7621_UARTL3_GPIO (1<<3) 128297717Ssgalabov#define MT7621_PCIE0_RST (1<<19) 129297717Ssgalabov#define MT7621_PCIE1_RST (1<<8) 130297717Ssgalabov#define MT7621_PCIE2_RST (1<<7) 131297717Ssgalabov#define MT7621_PCIE_RST (MT7621_PCIE0_RST | MT7621_PCIE1_RST | \ 132297717Ssgalabov MT7621_PCIE2_RST) 133297717Ssgalabov 134297717Ssgalabov#define RT3883_PCI_RST (1<<24) 135297717Ssgalabov#define RT3883_PCI_CLK (1<<19) 136297717Ssgalabov#define RT3883_PCI_HOST_MODE (1<<7) 137297717Ssgalabov#define RT3883_PCIE_RC_MODE (1<<8) 138297717Ssgalabov/* End of chip specific defines */ 139297717Ssgalabov 140297717Ssgalabov#define MT_WRITE32(sc, off, val) \ 141297717Ssgalabov bus_write_4((sc)->pci_res[0], (off), (val)) 142297717Ssgalabov#define MT_WRITE16(sc, off, val) \ 143297717Ssgalabov bus_write_2((sc)->pci_res[0], (off), (val)) 144297717Ssgalabov#define MT_WRITE8(sc, off, val) \ 145297717Ssgalabov bus_write_1((sc)->pci_res[0], (off), (val)) 146297717Ssgalabov#define MT_READ32(sc, off) \ 147297717Ssgalabov bus_read_4((sc)->pci_res[0], (off)) 148297717Ssgalabov#define MT_READ16(sc, off) \ 149297717Ssgalabov bus_read_2((sc)->pci_res[0], (off)) 150297717Ssgalabov#define MT_READ8(sc, off) \ 151297717Ssgalabov bus_read_1((sc)->pci_res[0], (off)) 152297717Ssgalabov 153297717Ssgalabov#define MT_CLR_SET32(sc, off, clr, set) \ 154297717Ssgalabov MT_WRITE32((sc), (off), ((MT_READ32((sc), (off)) & ~(clr)) | (off))) 155297717Ssgalabov 156297717Ssgalabov#endif /* __MTK_PCIE_H__ */ 157