maltareg.h revision 303975
165793Smsmith/* $NetBSD: maltareg.h,v 1.1 2002/03/07 14:44:04 simonb Exp $ */ 265793Smsmith 381082Sscottl/* 465793Smsmith * Copyright 2002 Wasabi Systems, Inc. 581150Sscottl * All rights reserved. 665793Smsmith * 765793Smsmith * Written by Simon Burge for Wasabi Systems, Inc. 865793Smsmith * 965793Smsmith * Redistribution and use in source and binary forms, with or without 1065793Smsmith * modification, are permitted provided that the following conditions 1165793Smsmith * are met: 1265793Smsmith * 1. Redistributions of source code must retain the above copyright 1365793Smsmith * notice, this list of conditions and the following disclaimer. 1465793Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1565793Smsmith * notice, this list of conditions and the following disclaimer in the 1665793Smsmith * documentation and/or other materials provided with the distribution. 1765793Smsmith * 3. All advertising materials mentioning features or use of this software 1865793Smsmith * must display the following acknowledgement: 1965793Smsmith * This product includes software developed for the NetBSD Project by 2065793Smsmith * Wasabi Systems, Inc. 2165793Smsmith * 4. The name of Wasabi Systems, Inc. may not be used to endorse 2265793Smsmith * or promote products derived from this software without specific prior 2365793Smsmith * written permission. 2465793Smsmith * 2565793Smsmith * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 2665793Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2765793Smsmith * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2865793Smsmith * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 2965793Smsmith * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30119418Sobrien * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31119418Sobrien * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32119418Sobrien * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 3365793Smsmith * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3465793Smsmith * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3565793Smsmith * POSSIBILITY OF SUCH DAMAGE. 3665793Smsmith * 3781151Sscottl * $FreeBSD: releng/11.0/sys/mips/malta/maltareg.h 202175 2010-01-12 21:36:08Z imp $ 3881151Sscottl */ 3965793Smsmith 4065793Smsmith/* 4165793Smsmith Memory Map 42129879Sphk 4365793Smsmith 0000.0000 * 128MB Typically SDRAM (on Core Board) 44111691Sscottl 0800.0000 * 256MB Typically PCI 4565793Smsmith 1800.0000 * 62MB Typically PCI 4665793Smsmith 1be0.0000 * 2MB Typically System controller's internal registers 4765793Smsmith 1c00.0000 * 32MB Typically not used 4865793Smsmith 1e00.0000 4MB Monitor Flash 4965793Smsmith 1e40.0000 12MB reserved 5065793Smsmith 1f00.0000 12MB Switches 5165793Smsmith LEDs 5265793Smsmith ASCII display 53119273Simp Soft reset 54119273Simp FPGA revision number 5565793Smsmith CBUS UART (tty2) 5665793Smsmith General Purpose I/O 57138635Sscottl I2C controller 5865793Smsmith 1f10.0000 * 11MB Typically System Controller specific 5965793Smsmith 1fc0.0000 4MB Maps to Monitor Flash 6083114Sscottl 1fd0.0000 * 3MB Typically System Controller specific 6183114Sscottl 6265793Smsmith * depends on implementation of the Core Board and of software 63247570Smarius */ 64247570Smarius 65247570Smarius/* 66247570Smarius CPU interrupts 67247570Smarius 6865793Smsmith NMI South Bridge or NMI button 6983114Sscottl 0 South Bridge INTR 7083114Sscottl 1 South Bridge SMI 7183114Sscottl 2 CBUS UART (tty2) 7283114Sscottl 3 COREHI (Core Card) 7383114Sscottl 4 CORELO (Core Card) 7483114Sscottl 5 Not used, driven inactive (typically CPU internal timer interrupt 7565793Smsmith 76227843Smarius IRQ mapping (as used by YAMON) 7765793Smsmith 7865793Smsmith 0 Timer South Bridge 7965793Smsmith 1 Keyboard SuperIO 8065793Smsmith 2 Reserved by South Bridge (for cascading) 8165793Smsmith 3 UART (tty1) SuperIO 8265793Smsmith 4 UART (tty0) SuperIO 8365793Smsmith 5 Not used 8465793Smsmith 6 Floppy Disk SuperIO 8589112Smsmith 7 Parallel Port SuperIO 8689112Smsmith 8 Real Time Clock South Bridge 87247570Smarius 9 I2C bus South Bridge 88165102Smjacob 10 PCI A,B,eth PCI slot 1..4, Ethernet 8965793Smsmith 11 PCI C,audio PCI slot 1..4, Audio, USB (South Bridge) 90247570Smarius PCI D,USB 9165793Smsmith 12 Mouse SuperIO 9283114Sscottl 13 Reserved by South Bridge 9383114Sscottl 14 Primary IDE Primary IDE slot 9483114Sscottl 15 Secondary IDE Secondary IDE slot/Compact flash connector 9583114Sscottl */ 9683114Sscottl 9795536Sscottl#define MALTA_SYSTEMRAM_BASE 0x00000000ul /* System RAM: */ 98247570Smarius#define MALTA_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */ 9965793Smsmith 100112679Sscottl#define MALTA_PCIMEM1_BASE 0x08000000ul /* PCI 1 memory: */ 10195536Sscottl#define MALTA_PCIMEM1_SIZE 0x08000000 /* 128 MByte */ 102112679Sscottl 10395536Sscottl#define MALTA_PCIMEM2_BASE 0x10000000ul /* PCI 2 memory: */ 104112679Sscottl#define MALTA_PCIMEM2_SIZE 0x08000000 /* 128 MByte */ 10595536Sscottl 106112679Sscottl#define MALTA_PCIMEM3_BASE 0x18000000ul /* PCI 3 memory */ 10795536Sscottl#define MALTA_PCIMEM3_SIZE 0x03e00000 /* 62 MByte */ 108112679Sscottl 10995536Sscottl#define MALTA_CORECTRL_BASE 0x1be00000ul /* Core control: */ 110112679Sscottl#define MALTA_CORECTRL_SIZE 0x00200000 /* 2 MByte */ 11195536Sscottl 112112679Sscottl#define MALTA_RESERVED_BASE1 0x1c000000ul /* Reserved: */ 11395536Sscottl#define MALTA_RESERVED_SIZE1 0x02000000 /* 32 MByte */ 114112679Sscottl 11595536Sscottl#define MALTA_MONITORFLASH_BASE 0x1e000000ul /* Monitor Flash: */ 116112679Sscottl#define MALTA_MONITORFLASH_SIZE 0x003e0000 /* 4 MByte */ 11795536Sscottl#define MALTA_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ 118112679Sscottl 11995536Sscottl#define MALTA_FILEFLASH_BASE 0x1e3e0000ul /* File Flash (for monitor): */ 120117361Sscottl#define MALTA_FILEFLASH_SIZE 0x00020000 /* 128 KByte */ 121117361Sscottl 122112679Sscottl#define MALTA_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ 123112679Sscottl 124112679Sscottl#define MALTA_RESERVED_BASE2 0x1e400000ul /* Reserved: */ 125107797Sscottl#define MALTA_RESERVED_SIZE2 0x00c00000 /* 12 MByte */ 126112679Sscottl 127112679Sscottl#define MALTA_FPGA_BASE 0x1f000000ul /* FPGA: */ 128112679Sscottl#define MALTA_FPGA_SIZE 0x00c00000 /* 12 MByte */ 129112679Sscottl 130112679Sscottl#define MALTA_NMISTATUS (MALTA_FPGA_BASE + 0x24) 131112679Sscottl#define MALTA_NMI_SB 0x2 /* Pending NMI from the South Bridge */ 132115409Sscottl#define MALTA_NMI_ONNMI 0x1 /* Pending NMI from the ON/NMI push button */ 133159702Sbrueffer 134127242Sscottl#define MALTA_NMIACK (MALTA_FPGA_BASE + 0x104) 135127242Sscottl#define MALTA_NMIACK_ONNMI 0x1 /* Write 1 to acknowledge ON/NMI */ 136127242Sscottl 137159702Sbrueffer#define MALTA_SWITCH (MALTA_FPGA_BASE + 0x200) 138136756Sscottl#define MALTA_SWITCH_MASK 0xff /* settings of DIP switch S2 */ 139159702Sbrueffer 140148866Sps#define MALTA_STATUS (MALTA_FPGA_BASE + 0x208) 141148866Sps#define MALTA_ST_MFWR 0x10 /* Monitor Flash is write protected (JP1) */ 142254004Smarius#define MALTA_S54 0x08 /* switch S5-4 - set YAMON factory default mode */ 143138884Sscottl#define MALTA_S53 0x04 /* switch S5-3 */ 144133606Sscottl#define MALTA_BIGEND 0x02 /* switch S5-2 - big endian mode */ 145133606Sscottl 146151086Sscottl#define MALTA_JMPRS (MALTA_FPGA_BASE + 0x210) 147151086Sscottl#define MALTA_JMPRS_PCICLK 0x1c /* PCI clock frequency */ 148151086Sscottl#define MALTA_JMPRS_EELOCK 0x02 /* I2C EEPROM is write protected */ 149151086Sscottl 150151086Sscottl#define MALTA_LEDBAR (MALTA_FPGA_BASE + 0x408) 151151086Sscottl#define MALTA_ASCIIWORD (MALTA_FPGA_BASE + 0x410) 152151086Sscottl#define MALTA_ASCII_BASE (MALTA_FPGA_BASE + 0x418) 153151086Sscottl#define MALTA_ASCIIPOS0 0x00 154151086Sscottl#define MALTA_ASCIIPOS1 0x08 155151086Sscottl#define MALTA_ASCIIPOS2 0x10 156151086Sscottl#define MALTA_ASCIIPOS3 0x18 157151086Sscottl#define MALTA_ASCIIPOS4 0x20 158151086Sscottl#define MALTA_ASCIIPOS5 0x28 159151086Sscottl#define MALTA_ASCIIPOS6 0x30 160254004Smarius#define MALTA_ASCIIPOS7 0x38 161151086Sscottl 162151086Sscottl#define MALTA_SOFTRES (MALTA_FPGA_BASE + 0x500) 163151086Sscottl#define MALTA_GORESET 0x42 /* write this to MALTA_SOFTRES for board reset */ 164151086Sscottl 165151086Sscottl/* 166151086Sscottl * BRKRES is the number of milliseconds before a "break" on tty will 167159702Sbrueffer * trigger a reset. A value of 0 will disable the reset. 168151086Sscottl */ 169159702Sbrueffer#define MALTA_BRKRES (MALTA_FPGA_BASE + 0x508) 170151086Sscottl#define MALTA_BRKRES_MASK 0xff 171151086Sscottl 172151086Sscottl#define MALTA_CBUSUART (MALTA_FPGA_BASE + 0x900) 173151086Sscottl/* 16C550C UART, 8 bit registers on 8 byte boundaries */ 174151086Sscottl/* RXTX 0x00 */ 175151086Sscottl/* INTEN 0x08 */ 176151086Sscottl/* IIFIFO 0x10 */ 177151086Sscottl/* LCTRL 0x18 */ 178172653Semaste/* MCTRL 0x20 */ 179172653Semaste/* LSTAT 0x28 */ 180151086Sscottl/* MSTAT 0x30 */ 181206540Semaste/* SCRATCH 0x38 */ 182151086Sscottl#define MALTA_CBUSUART_INTR 2 183151086Sscottl 184151086Sscottl#define MALTA_GPIO_BASE (MALTA_FPGA_BASE + 0xa00) 185151086Sscottl#define MALTA_GPOUT 0x0 186151086Sscottl#define MALTA_GPINP 0x8 187151086Sscottl 188151086Sscottl#define MALTA_I2C_BASE (MALTA_FPGA_BASE + 0xb00) 189151086Sscottl#define MALTA_I2CINP 0x00 190151086Sscottl#define MALTA_I2COE 0x08 191159702Sbrueffer#define MALTA_I2COUT 0x10 192151086Sscottl#define MALTA_I2CSEL 0x18 193159702Sbrueffer 194151086Sscottl#define MALTA_BOOTROM_BASE 0x1fc00000ul /* Boot ROM: */ 195159702Sbrueffer#define MALTA_BOOTROM_SIZE 0x00400000 /* 4 MByte */ 196151086Sscottl 197159702Sbrueffer#define MALTA_REVISION 0x1fc00010ul 198172653Semaste#define MALTA_REV_FPGRV 0xff0000 /* CBUS FPGA revision */ 199172653Semaste#define MALTA_REV_CORID 0x00fc00 /* Core Board ID */ 200172653Semaste#define MALTA_REV_CORRV 0x000300 /* Core Board Revision */ 201172653Semaste#define MALTA_REV_PROID 0x0000f0 /* Product ID */ 202172653Semaste#define MALTA_REV_PRORV 0x00000f /* Product Revision */ 203172653Semaste 204172653Semaste/* PCI definitions */ 205172653Semaste#define MALTA_SOUTHBRIDGE_INTR 0 206172653Semaste 207172653Semaste#define MALTA_PCI0_IO_BASE MALTA_PCIMEM3_BASE 208172653Semaste#define MALTA_PCI0_ADDR( addr ) (MALTA_PCI0_IO_BASE + (addr)) 209172653Semaste 210172653Semaste#define MALTA_RTCADR 0x70 // MALTA_PCI_IO_ADDR8(0x70) 211172653Semaste#define MALTA_RTCDAT 0x71 // MALTA_PCI_IO_ADDR8(0x71) 212171940Semaste 213171940Semaste#define MALTA_SMSC_COM1_ADR 0x3f8 214171940Semaste#define MALTA_SMSC_COM2_ADR 0x2f8 215171940Semaste#define MALTA_UART0ADR MALTA_PCI0_ADDR(MALTA_SMSC_COM1_ADR) 216172653Semaste#define MALTA_UART1ADR MALTA_SMSC_COM2_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_COM2_ADR) 217172653Semaste 218172653Semaste#define MALTA_SMSC_1284_ADR 0x378 219172653Semaste#define MALTA_1284ADR MALTA_SMSC_1284_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_1284_ADR) 220172653Semaste 221172653Semaste#define MALTA_SMSC_FDD_ADR 0x3f0 222172653Semaste#define MALTA_FDDADR MALTA_SMSC_FDD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_FDD_ADR) 223172653Semaste 224172653Semaste#define MALTA_SMSC_KYBD_ADR 0x60 /* Fixed 0x60, 0x64 */ 225172653Semaste#define MALTA_KYBDADR MALTA_SMSC_KYBD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_KYBD_ADR) 226172653Semaste#define MALTA_SMSC_MOUSE_ADR MALTA_SMSC_KYBD_ADR 227172653Semaste#define MALTA_MOUSEADR MALTA_KYBDADR 228172653Semaste 229172653Semaste 230172653Semaste#define MALTA_DMA_PCI_PCIBASE 0x00000000UL 231172653Semaste#define MALTA_DMA_PCI_PHYSBASE 0x00000000UL 232172653Semaste#define MALTA_DMA_PCI_SIZE (256 * 1024 * 1024) 233172653Semaste 234172653Semaste#define MALTA_DMA_ISA_PCIBASE 0x00800000UL 235172653Semaste#define MALTA_DMA_ISA_PHYSBASE 0x00000000UL 236172653Semaste#define MALTA_DMA_ISA_SIZE (8 * 1024 * 1024) 237172653Semaste 238172653Semaste#ifndef _LOCORE 239172653Semastevoid led_bar(uint8_t); 240174368Semastevoid led_display_word(uint32_t); 241174368Semastevoid led_display_str(const char *); 242174368Semastevoid led_display_char(int, uint8_t); 243174368Semaste#endif 244174368Semaste