cpu.h revision 209996
1/* $OpenBSD: cpu.h,v 1.4 1998/09/15 10:50:12 pefo Exp $ */ 2 3/*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * Copyright (C) 1989 Digital Equipment Corporation. 35 * Permission to use, copy, modify, and distribute this software and 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 * JNPR: cpu.h,v 1.9.2.2 2007/09/10 08:23:46 girish 44 * $FreeBSD: head/sys/mips/include/cpu.h 209996 2010-07-13 15:29:37Z imp $ 45 */ 46 47#ifndef _MACHINE_CPU_H_ 48#define _MACHINE_CPU_H_ 49 50#include <machine/endian.h> 51 52/* 53 * Status register. 54 */ 55#define SR_COP_USABILITY 0xf0000000 56#define SR_COP_0_BIT 0x10000000 57#define SR_COP_1_BIT 0x20000000 58#define SR_COP_2_BIT 0x40000000 59#define SR_RP 0x08000000 60#define SR_FR_32 0x04000000 61#define SR_RE 0x02000000 62#define SR_PX 0x00800000 63#define SR_BOOT_EXC_VEC 0x00400000 64#define SR_TLB_SHUTDOWN 0x00200000 65#define SR_SOFT_RESET 0x00100000 66#define SR_DIAG_CH 0x00040000 67#define SR_DIAG_CE 0x00020000 68#define SR_DIAG_DE 0x00010000 69#define SR_KX 0x00000080 70#define SR_SX 0x00000040 71#define SR_UX 0x00000020 72#define SR_KSU_MASK 0x00000018 73#define SR_KSU_USER 0x00000010 74#define SR_KSU_SUPER 0x00000008 75#define SR_KSU_KERNEL 0x00000000 76#define SR_ERL 0x00000004 77#define SR_EXL 0x00000002 78#define SR_INT_ENAB 0x00000001 79 80#define SR_INT_MASK 0x0000ff00 81#define SOFT_INT_MASK_0 0x00000100 82#define SOFT_INT_MASK_1 0x00000200 83#define SR_INT_MASK_0 0x00000400 84#define SR_INT_MASK_1 0x00000800 85#define SR_INT_MASK_2 0x00001000 86#define SR_INT_MASK_3 0x00002000 87#define SR_INT_MASK_4 0x00004000 88#define SR_INT_MASK_5 0x00008000 89#define ALL_INT_MASK SR_INT_MASK 90#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 91#define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK) 92 93#define soft_int_mask(softintr) (1 << ((softintr) + 8)) 94#define hard_int_mask(hardintr) (1 << ((hardintr) + 10)) 95 96/* 97 * The bits in the cause register. 98 * 99 * CR_BR_DELAY Exception happened in branch delay slot. 100 * CR_COP_ERR Coprocessor error. 101 * CR_IP Interrupt pending bits defined below. 102 * CR_EXC_CODE The exception type (see exception codes below). 103 */ 104#define CR_BR_DELAY 0x80000000 105#define CR_COP_ERR 0x30000000 106#define CR_EXC_CODE 0x0000007c 107#define CR_EXC_CODE_SHIFT 2 108#define CR_IPEND 0x0000ff00 109 110/* 111 * Cause Register Format: 112 * 113 * 31 30 29 28 27 26 25 24 23 8 7 6 2 1 0 114 * ---------------------------------------------------------------------- 115 * | BD | 0| CE | 0| W2| W1| IV| IP15 - IP0 | 0| Exc Code | 0| 116 * |______________________________________________________________________ 117 */ 118 119#define CR_INT_SOFT0 0x00000100 120#define CR_INT_SOFT1 0x00000200 121#define CR_INT_0 0x00000400 122#define CR_INT_1 0x00000800 123#define CR_INT_2 0x00001000 124#define CR_INT_3 0x00002000 125#define CR_INT_4 0x00004000 126#define CR_INT_5 0x00008000 127 128#define CR_INT_UART CR_INT_1 129#define CR_INT_IPI CR_INT_2 130#define CR_INT_CLOCK CR_INT_5 131 132/* 133 * The bits in the CONFIG register 134 */ 135#define CFG_K0_UNCACHED 2 136#define CFG_K0_CACHED 3 137#define CFG_K0_MASK 0x7 138 139/* 140 * The bits in the context register. 141 */ 142#define CNTXT_PTE_BASE 0xff800000 143#define CNTXT_BAD_VPN2 0x007ffff0 144 145/* 146 * Location of exception vectors. 147 */ 148#define RESET_EXC_VEC ((intptr_t)(int32_t)0xbfc00000) 149#define TLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000) 150#define XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080) 151#define CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100) 152#define GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180) 153 154/* 155 * Coprocessor 0 registers: 156 */ 157#define COP_0_TLB_INDEX $0 158#define COP_0_TLB_RANDOM $1 159#define COP_0_TLB_LO0 $2 160#define COP_0_TLB_LO1 $3 161#define COP_0_TLB_CONTEXT $4 162#define COP_0_TLB_PG_MASK $5 163#define COP_0_TLB_WIRED $6 164#define COP_0_INFO $7 165#define COP_0_BAD_VADDR $8 166#define COP_0_COUNT $9 167#define COP_0_TLB_HI $10 168#define COP_0_COMPARE $11 169#define COP_0_STATUS_REG $12 170#define COP_0_CAUSE_REG $13 171#define COP_0_EXC_PC $14 172#define COP_0_PRID $15 173#define COP_0_CONFIG $16 174#define COP_0_LLADDR $17 175#define COP_0_WATCH_LO $18 176#define COP_0_WATCH_HI $19 177#define COP_0_TLB_XCONTEXT $20 178#define COP_0_ECC $26 179#define COP_0_CACHE_ERR $27 180#define COP_0_TAG_LO $28 181#define COP_0_TAG_HI $29 182#define COP_0_ERROR_PC $30 183 184/* 185 * Coprocessor 0 Set 1 186 */ 187#define C0P_1_IPLLO $18 188#define C0P_1_IPLHI $19 189#define C0P_1_INTCTL $20 190#define C0P_1_DERRADDR0 $26 191#define C0P_1_DERRADDR1 $27 192 193/* 194 * Values for the code field in a break instruction. 195 */ 196#define BREAK_INSTR 0x0000000d 197#define BREAK_VAL_MASK 0x03ffffc0 198#define BREAK_VAL_SHIFT 16 199#define BREAK_KDB_VAL 512 200#define BREAK_SSTEP_VAL 513 201#define BREAK_BRKPT_VAL 514 202#define BREAK_SOVER_VAL 515 203#define BREAK_DDB_VAL 516 204#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 205#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 206#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 207#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 208#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) 209 210/* 211 * Mininum and maximum cache sizes. 212 */ 213#define MIN_CACHE_SIZE (16 * 1024) 214#define MAX_CACHE_SIZE (256 * 1024) 215 216/* 217 * The floating point version and status registers. 218 */ 219#define FPC_ID $0 220#define FPC_CSR $31 221 222/* 223 * The floating point coprocessor status register bits. 224 */ 225#define FPC_ROUNDING_BITS 0x00000003 226#define FPC_ROUND_RN 0x00000000 227#define FPC_ROUND_RZ 0x00000001 228#define FPC_ROUND_RP 0x00000002 229#define FPC_ROUND_RM 0x00000003 230#define FPC_STICKY_BITS 0x0000007c 231#define FPC_STICKY_INEXACT 0x00000004 232#define FPC_STICKY_UNDERFLOW 0x00000008 233#define FPC_STICKY_OVERFLOW 0x00000010 234#define FPC_STICKY_DIV0 0x00000020 235#define FPC_STICKY_INVALID 0x00000040 236#define FPC_ENABLE_BITS 0x00000f80 237#define FPC_ENABLE_INEXACT 0x00000080 238#define FPC_ENABLE_UNDERFLOW 0x00000100 239#define FPC_ENABLE_OVERFLOW 0x00000200 240#define FPC_ENABLE_DIV0 0x00000400 241#define FPC_ENABLE_INVALID 0x00000800 242#define FPC_EXCEPTION_BITS 0x0003f000 243#define FPC_EXCEPTION_INEXACT 0x00001000 244#define FPC_EXCEPTION_UNDERFLOW 0x00002000 245#define FPC_EXCEPTION_OVERFLOW 0x00004000 246#define FPC_EXCEPTION_DIV0 0x00008000 247#define FPC_EXCEPTION_INVALID 0x00010000 248#define FPC_EXCEPTION_UNIMPL 0x00020000 249#define FPC_COND_BIT 0x00800000 250#define FPC_FLUSH_BIT 0x01000000 251#define FPC_MBZ_BITS 0xfe7c0000 252 253/* 254 * Constants to determine if have a floating point instruction. 255 */ 256#define OPCODE_SHIFT 26 257#define OPCODE_C1 0x11 258 259/* 260 * The first TLB entry that write random hits. 261 * TLB entry 0 maps the kernel stack of the currently running thread 262 * TLB entry 1 maps the pcpu area of processor (only for SMP builds) 263 */ 264#define KSTACK_TLB_ENTRY 0 265#ifdef SMP 266#define PCPU_TLB_ENTRY 1 267#define VMWIRED_ENTRIES 2 268#else 269#define VMWIRED_ENTRIES 1 270#endif /* SMP */ 271 272/* 273 * The number of process id entries. 274 */ 275#define VMNUM_PIDS 256 276 277/* 278 * Exported definitions unique to mips cpu support. 279 */ 280 281#define cpu_swapout(p) panic("cpu_swapout: can't get here"); 282 283#ifndef _LOCORE 284#include <machine/cpufunc.h> 285#include <machine/frame.h> 286 287/* 288 * Arguments to hardclock and gatherstats encapsulate the previous 289 * machine state in an opaque clockframe. 290 */ 291#define clockframe trapframe /* Use normal trap frame */ 292 293#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 294#define CLKF_PC(framep) ((framep)->pc) 295#define CLKF_INTR(framep) (0) 296#define MIPS_CLKF_INTR() (intr_nesting_level >= 1) 297#define TRAPF_USERMODE(framep) (((framep)->sr & SR_KSU_USER) != 0) 298#define TRAPF_PC(framep) ((framep)->pc) 299#define cpu_getstack(td) ((td)->td_frame->sp) 300 301/* 302 * A machine-independent interface to the CPU's counter. 303 */ 304#define get_cyclecount() mips_rd_count() 305 306/* 307 * CPU identification, from PRID register. 308 */ 309union cpuprid { 310 int cpuprid; 311 struct { 312#if BYTE_ORDER == BIG_ENDIAN 313 u_int pad1:8; /* reserved */ 314 u_int cp_vendor:8; /* company identifier */ 315 u_int cp_imp:8; /* implementation identifier */ 316 u_int cp_majrev:4; /* major revision identifier */ 317 u_int cp_minrev:4; /* minor revision identifier */ 318#else 319 u_int cp_minrev:4; /* minor revision identifier */ 320 u_int cp_majrev:4; /* major revision identifier */ 321 u_int cp_imp:8; /* implementation identifier */ 322 u_int cp_vendor:8; /* company identifier */ 323 u_int pad1:8; /* reserved */ 324#endif 325 } cpu; 326}; 327 328#endif /* !_LOCORE */ 329 330/* 331 * CTL_MACHDEP definitions. 332 */ 333#define CPU_CONSDEV 1 /* dev_t: console terminal device */ 334#define CPU_ADJKERNTZ 2 /* int: timezone offset (seconds) */ 335#define CPU_DISRTCSET 3 /* int: disable resettodr() call */ 336#define CPU_BOOTINFO 4 /* struct: bootinfo */ 337#define CPU_WALLCLOCK 5 /* int: indicates wall CMOS clock */ 338#define CPU_MAXID 6 /* number of valid machdep ids */ 339 340#define CTL_MACHDEP_NAMES { \ 341 { 0, 0 }, \ 342 { "console_device", CTLTYPE_STRUCT }, \ 343 { "adjkerntz", CTLTYPE_INT }, \ 344 { "disable_rtc_set", CTLTYPE_INT }, \ 345 { "bootinfo", CTLTYPE_STRUCT }, \ 346 { "wall_cmos_clock", CTLTYPE_INT }, \ 347} 348 349/* 350 * MIPS CPU types (cp_imp). 351 */ 352#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 353#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 354#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 355#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 356#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 357#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 358#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 359#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 360#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 361#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 362#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ 363#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 364#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 365#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 366#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 367#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 368#define MIPS_RM7000 0x27 /* QED RM7000 CPU ISA IV */ 369#define MIPS_RM52X0 0x28 /* QED RM52X0 CPU ISA IV */ 370#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ 371#define MIPS_RM9000 0x34 /* E9000 CPU */ 372 373/* 374 * MIPS FPU types 375 */ 376#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 377#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 378#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 379#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 380#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 381#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */ 382#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 383#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ 384#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */ 385#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */ 386#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 387#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 388#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */ 389#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 390#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */ 391#define MIPS_RM7000 0x27 /* QED RM7000 FPU ISA IV */ 392#define MIPS_RM5230 0x28 /* QED RM52X0 based FPU ISA IV */ 393#define MIPS_RM52XX 0x28 /* QED RM52X0 based FPU ISA IV */ 394#define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+ */ 395 396#if defined(_KERNEL) && !defined(_LOCORE) 397 398struct user; 399 400int Mips_ConfigCache(void); 401 402void Mips_SyncCache(void); 403void Mips_SyncDCache(vm_offset_t, int); 404void Mips_HitSyncDCache(vm_offset_t, int); 405void Mips_HitSyncSCache(vm_offset_t, int); 406void Mips_IOSyncDCache(vm_offset_t, int, int); 407void Mips_HitInvalidateDCache(vm_offset_t, int); 408void Mips_SyncICache(vm_offset_t, int); 409void Mips_InvalidateICache(vm_offset_t, int); 410 411void wbflush(void); 412 413extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */ 414extern u_int32_t cpu_counter_last; /* Last compare value loaded */ 415extern int num_tlbentries; 416extern char btext[]; 417extern char etext[]; 418extern int intr_nesting_level; 419 420#define func_0args_asmmacro(func, in) \ 421 __asm __volatile ( "jalr %0" \ 422 : "=r" (in) /* outputs */ \ 423 : "r" (func) /* inputs */ \ 424 : "$31", "$4"); 425 426#define func_1args_asmmacro(func, arg0) \ 427 __asm __volatile ("move $4, %1;" \ 428 "jalr %0" \ 429 : /* outputs */ \ 430 : "r" (func), "r" (arg0) /* inputs */ \ 431 : "$31", "$4"); 432 433#define func_2args_asmmacro(func, arg0, arg1) \ 434 __asm __volatile ("move $4, %1;" \ 435 "move $5, %2;" \ 436 "jalr %0" \ 437 : /* outputs */ \ 438 : "r" (func), "r" (arg0), "r" (arg1) /* inputs */ \ 439 : "$31", "$4", "$5"); 440 441#define func_3args_asmmacro(func, arg0, arg1, arg2) \ 442 __asm __volatile ( "move $4, %1;" \ 443 "move $5, %2;" \ 444 "move $6, %3;" \ 445 "jalr %0" \ 446 : /* outputs */ \ 447 : "r" (func), "r" (arg0), "r" (arg1), "r" (arg2) /* inputs */ \ 448 : "$31", "$4", "$5", "$6"); 449 450/* 451 * Enable realtime clock (always enabled). 452 */ 453#define enablertclock() 454 455/* 456 * Are we in an interrupt handler? required by JunOS 457 */ 458#define IN_INT_HANDLER() \ 459 (curthread->td_intr_nesting_level != 0 || \ 460 (curthread->td_pflags & TDP_ITHREAD)) 461 462/* 463 * Low level access routines to CPU registers 464 */ 465 466void swi_vm(void *); 467void cpu_halt(void); 468void cpu_reset(void); 469 470u_int32_t set_intr_mask(u_int32_t); 471u_int32_t get_intr_mask(void); 472 473#define cpu_spinwait() /* nothing */ 474 475#endif /* _KERNEL */ 476#endif /* !_MACHINE_CPU_H_ */ 477