cpu.h revision 178172
1204431Sraj/* $OpenBSD: cpu.h,v 1.4 1998/09/15 10:50:12 pefo Exp $ */ 2204431Sraj 3204431Sraj/*- 4204431Sraj * Copyright (c) 1992, 1993 5204431Sraj * The Regents of the University of California. All rights reserved. 6204431Sraj * 7204431Sraj * This code is derived from software contributed to Berkeley by 8204431Sraj * Ralph Campbell and Rick Macklem. 9204431Sraj * 10204431Sraj * Redistribution and use in source and binary forms, with or without 11204431Sraj * modification, are permitted provided that the following conditions 12204431Sraj * are met: 13204431Sraj * 1. Redistributions of source code must retain the above copyright 14204431Sraj * notice, this list of conditions and the following disclaimer. 15204431Sraj * 2. Redistributions in binary form must reproduce the above copyright 16204431Sraj * notice, this list of conditions and the following disclaimer in the 17204431Sraj * documentation and/or other materials provided with the distribution. 18204431Sraj * 4. Neither the name of the University nor the names of its contributors 19204431Sraj * may be used to endorse or promote products derived from this software 20204431Sraj * without specific prior written permission. 21204431Sraj * 22204431Sraj * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23204431Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24204431Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25204431Sraj * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26204431Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27204431Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28204431Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29204431Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30204431Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31204431Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32204431Sraj * SUCH DAMAGE. 33204431Sraj * 34204431Sraj * Copyright (C) 1989 Digital Equipment Corporation. 35204431Sraj * Permission to use, copy, modify, and distribute this software and 36204431Sraj * its documentation for any purpose and without fee is hereby granted, 37204431Sraj * provided that the above copyright notice appears in all copies. 38204431Sraj * Digital Equipment Corporation makes no representations about the 39204431Sraj * suitability of this software for any purpose. It is provided "as is" 40204431Sraj * without express or implied warranty. 41204431Sraj * 42204431Sraj * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43204431Sraj * JNPR: cpu.h,v 1.9.2.2 2007/09/10 08:23:46 girish 44204431Sraj * $FreeBSD: head/sys/mips/include/cpu.h 178172 2008-04-13 07:27:37Z imp $ 45204431Sraj */ 46204431Sraj 47204431Sraj#ifndef _MACHINE_CPU_H_ 48204431Sraj#define _MACHINE_CPU_H_ 49204431Sraj 50204431Sraj#include <machine/psl.h> 51204431Sraj#include <machine/endian.h> 52204431Sraj 53204431Sraj#define MIPS_CACHED_MEMORY_ADDR 0x80000000 54204431Sraj#define MIPS_UNCACHED_MEMORY_ADDR 0xa0000000 55204431Sraj#define MIPS_MAX_MEM_ADDR 0xbe000000 56204431Sraj#define MIPS_RESERVED_ADDR 0xbfc80000 57204431Sraj 58204431Sraj#define MIPS_KSEG0_LARGEST_PHYS 0x20000000 59204431Sraj#define MIPS_CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 60204431Sraj#define MIPS_PHYS_TO_CACHED(x) ((unsigned)(x) | MIPS_CACHED_MEMORY_ADDR) 61#define MIPS_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 62#define MIPS_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MIPS_UNCACHED_MEMORY_ADDR) 63 64#define MIPS_PHYS_MASK (0x1fffffff) 65#define MIPS_PA_2_K1VA(x) (MIPS_KSEG1_START | ((x) & MIPS_PHYS_MASK)) 66 67#define MIPS_VA_TO_CINDEX(x) ((unsigned)(x) & 0xffffff | MIPS_CACHED_MEMORY_ADDR) 68#define MIPS_CACHED_TO_UNCACHED(x) (MIPS_PHYS_TO_UNCACHED(MIPS_CACHED_TO_PHYS(x))) 69 70#define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START) 71#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START) 72#define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) 73#define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) 74 75/* 76 * Status register. 77 */ 78#define SR_COP_USABILITY 0xf0000000 79#define SR_COP_0_BIT 0x10000000 80#define SR_COP_1_BIT 0x20000000 81#define SR_COP_2_BIT 0x40000000 82#define SR_RP 0x08000000 83#define SR_FR_32 0x04000000 84#define SR_RE 0x02000000 85#define SR_PX 0x00800000 86#define SR_BOOT_EXC_VEC 0x00400000 87#define SR_TLB_SHUTDOWN 0x00200000 88#define SR_SOFT_RESET 0x00100000 89#define SR_DIAG_CH 0x00040000 90#define SR_DIAG_CE 0x00020000 91#define SR_DIAG_DE 0x00010000 92#define SR_KX 0x00000080 93#define SR_SX 0x00000040 94#define SR_UX 0x00000020 95#define SR_KSU_MASK 0x00000018 96#define SR_KSU_USER 0x00000010 97#define SR_KSU_SUPER 0x00000008 98#define SR_KSU_KERNEL 0x00000000 99#define SR_ERL 0x00000004 100#define SR_EXL 0x00000002 101#define SR_INT_ENAB 0x00000001 102 103#define SR_INT_MASK 0x0000ff00 104#define SOFT_INT_MASK_0 0x00000100 105#define SOFT_INT_MASK_1 0x00000200 106#define SR_INT_MASK_0 0x00000400 107#define SR_INT_MASK_1 0x00000800 108#define SR_INT_MASK_2 0x00001000 109#define SR_INT_MASK_3 0x00002000 110#define SR_INT_MASK_4 0x00004000 111#define SR_INT_MASK_5 0x00008000 112#define ALL_INT_MASK SR_INT_MASK 113#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 114#define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK) 115 116 117/* 118 * The bits in the cause register. 119 * 120 * CR_BR_DELAY Exception happened in branch delay slot. 121 * CR_COP_ERR Coprocessor error. 122 * CR_IP Interrupt pending bits defined below. 123 * CR_EXC_CODE The exception type (see exception codes below). 124 */ 125#define CR_BR_DELAY 0x80000000 126#define CR_COP_ERR 0x30000000 127#define CR_EXC_CODE 0x0000007c 128#define CR_EXC_CODE_SHIFT 2 129#define CR_IPEND 0x0000ff00 130 131/* 132 * Cause Register Format: 133 * 134 * 31 30 29 28 27 26 25 24 23 8 7 6 2 1 0 135 * ---------------------------------------------------------------------- 136 * | BD | 0| CE | 0| W2| W1| IV| IP15 - IP0 | 0| Exc Code | 0| 137 * |______________________________________________________________________ 138 */ 139 140#define CR_INT_SOFT0 0x00000100 141#define CR_INT_SOFT1 0x00000200 142#define CR_INT_0 0x00000400 143#define CR_INT_1 0x00000800 144#define CR_INT_2 0x00001000 145#define CR_INT_3 0x00002000 146#define CR_INT_4 0x00004000 147#define CR_INT_5 0x00008000 148 149#define CR_INT_UART CR_INT_1 150#define CR_INT_IPI CR_INT_2 151#define CR_INT_CLOCK CR_INT_5 152 153/* 154 * The bits in the CONFIG register 155 */ 156#define CFG_K0_UNCACHED 2 157#define CFG_K0_CACHED 3 158 159/* 160 * The bits in the context register. 161 */ 162#define CNTXT_PTE_BASE 0xff800000 163#define CNTXT_BAD_VPN2 0x007ffff0 164 165/* 166 * Location of exception vectors. 167 */ 168#define RESET_EXC_VEC 0xbfc00000 169#define TLB_MISS_EXC_VEC 0x80000000 170#define XTLB_MISS_EXC_VEC 0x80000080 171#define CACHE_ERR_EXC_VEC 0x80000100 172#define GEN_EXC_VEC 0x80000180 173 174/* 175 * Coprocessor 0 registers: 176 */ 177#define COP_0_TLB_INDEX $0 178#define COP_0_TLB_RANDOM $1 179#define COP_0_TLB_LO0 $2 180#define COP_0_TLB_LO1 $3 181#define COP_0_TLB_CONTEXT $4 182#define COP_0_TLB_PG_MASK $5 183#define COP_0_TLB_WIRED $6 184#define COP_0_INFO $7 185#define COP_0_BAD_VADDR $8 186#define COP_0_COUNT $9 187#define COP_0_TLB_HI $10 188#define COP_0_COMPARE $11 189#define COP_0_STATUS_REG $12 190#define COP_0_CAUSE_REG $13 191#define COP_0_EXC_PC $14 192#define COP_0_PRID $15 193#define COP_0_CONFIG $16 194#define COP_0_LLADDR $17 195#define COP_0_WATCH_LO $18 196#define COP_0_WATCH_HI $19 197#define COP_0_TLB_XCONTEXT $20 198#define COP_0_ECC $26 199#define COP_0_CACHE_ERR $27 200#define COP_0_TAG_LO $28 201#define COP_0_TAG_HI $29 202#define COP_0_ERROR_PC $30 203 204/* 205 * Coprocessor 0 Set 1 206 */ 207#define C0P_1_IPLLO $18 208#define C0P_1_IPLHI $19 209#define C0P_1_INTCTL $20 210#define C0P_1_DERRADDR0 $26 211#define C0P_1_DERRADDR1 $27 212 213/* 214 * Values for the code field in a break instruction. 215 */ 216#define BREAK_INSTR 0x0000000d 217#define BREAK_VAL_MASK 0x03ffffc0 218#define BREAK_VAL_SHIFT 16 219#define BREAK_KDB_VAL 512 220#define BREAK_SSTEP_VAL 513 221#define BREAK_BRKPT_VAL 514 222#define BREAK_SOVER_VAL 515 223#define BREAK_DDB_VAL 516 224#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 225#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 226#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 227#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 228#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) 229 230/* 231 * Mininum and maximum cache sizes. 232 */ 233#define MIN_CACHE_SIZE (16 * 1024) 234#define MAX_CACHE_SIZE (256 * 1024) 235 236/* 237 * The floating point version and status registers. 238 */ 239#define FPC_ID $0 240#define FPC_CSR $31 241 242/* 243 * The floating point coprocessor status register bits. 244 */ 245#define FPC_ROUNDING_BITS 0x00000003 246#define FPC_ROUND_RN 0x00000000 247#define FPC_ROUND_RZ 0x00000001 248#define FPC_ROUND_RP 0x00000002 249#define FPC_ROUND_RM 0x00000003 250#define FPC_STICKY_BITS 0x0000007c 251#define FPC_STICKY_INEXACT 0x00000004 252#define FPC_STICKY_UNDERFLOW 0x00000008 253#define FPC_STICKY_OVERFLOW 0x00000010 254#define FPC_STICKY_DIV0 0x00000020 255#define FPC_STICKY_INVALID 0x00000040 256#define FPC_ENABLE_BITS 0x00000f80 257#define FPC_ENABLE_INEXACT 0x00000080 258#define FPC_ENABLE_UNDERFLOW 0x00000100 259#define FPC_ENABLE_OVERFLOW 0x00000200 260#define FPC_ENABLE_DIV0 0x00000400 261#define FPC_ENABLE_INVALID 0x00000800 262#define FPC_EXCEPTION_BITS 0x0003f000 263#define FPC_EXCEPTION_INEXACT 0x00001000 264#define FPC_EXCEPTION_UNDERFLOW 0x00002000 265#define FPC_EXCEPTION_OVERFLOW 0x00004000 266#define FPC_EXCEPTION_DIV0 0x00008000 267#define FPC_EXCEPTION_INVALID 0x00010000 268#define FPC_EXCEPTION_UNIMPL 0x00020000 269#define FPC_COND_BIT 0x00800000 270#define FPC_FLUSH_BIT 0x01000000 271#define FPC_MBZ_BITS 0xfe7c0000 272 273/* 274 * Constants to determine if have a floating point instruction. 275 */ 276#define OPCODE_SHIFT 26 277#define OPCODE_C1 0x11 278 279/* 280 * The low part of the TLB entry. 281 */ 282#define VMTLB_PF_NUM 0x3fffffc0 283#define VMTLB_ATTR_MASK 0x00000038 284#define VMTLB_MOD_BIT 0x00000004 285#define VMTLB_VALID_BIT 0x00000002 286#define VMTLB_GLOBAL_BIT 0x00000001 287 288#define VMTLB_PHYS_PAGE_SHIFT 6 289 290/* 291 * The high part of the TLB entry. 292 */ 293#define VMTLB_VIRT_PAGE_NUM 0xffffe000 294#define VMTLB_PID 0x000000ff 295#define VMTLB_PID_R9K 0x00000fff 296#define VMTLB_PID_SHIFT 0 297#define VMTLB_VIRT_PAGE_SHIFT 12 298#define VMTLB_VIRT_PAGE_SHIFT_R9K 13 299 300/* 301 * The first TLB entry that write random hits. 302 */ 303#define VMWIRED_ENTRIES 1 304 305/* 306 * The number of process id entries. 307 */ 308#define VMNUM_PIDS 256 309 310/* 311 * TLB probe return codes. 312 */ 313#define VMTLB_NOT_FOUND 0 314#define VMTLB_FOUND 1 315#define VMTLB_FOUND_WITH_PATCH 2 316#define VMTLB_PROBE_ERROR 3 317 318/* 319 * Exported definitions unique to mips cpu support. 320 */ 321 322/* 323 * definitions of cpu-dependent requirements 324 * referenced in generic code 325 */ 326#define COPY_SIGCODE /* copy sigcode above user stack in exec */ 327 328#define cpu_swapout(p) panic("cpu_swapout: can't get here"); 329 330#ifndef _LOCORE 331#include <machine/frame.h> 332/* 333 * Arguments to hardclock and gatherstats encapsulate the previous 334 * machine state in an opaque clockframe. 335 */ 336#define clockframe trapframe /* Use normal trap frame */ 337 338#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 339#define CLKF_BASEPRI(framep) ((framep)->cpl == 0) 340#define CLKF_PC(framep) ((framep)->pc) 341#define CLKF_INTR(framep) (0) 342#define MIPS_CLKF_INTR() (intr_nesting_level >= 1) 343#define TRAPF_USERMODE(framep) (((framep)->sr & SR_KSU_USER) != 0) 344#define TRAPF_PC(framep) ((framep)->pc) 345#define cpu_getstack(td) ((td)->td_frame->sp) 346 347/* 348 * CPU identification, from PRID register. 349 */ 350union cpuprid { 351 int cpuprid; 352 struct { 353#if BYTE_ORDER == BIG_ENDIAN 354 u_int pad1:8; /* reserved */ 355 u_int cp_vendor:8; /* company identifier */ 356 u_int cp_imp:8; /* implementation identifier */ 357 u_int cp_majrev:4; /* major revision identifier */ 358 u_int cp_minrev:4; /* minor revision identifier */ 359#else 360 u_int cp_minrev:4; /* minor revision identifier */ 361 u_int cp_majrev:4; /* major revision identifier */ 362 u_int cp_imp:8; /* implementation identifier */ 363 u_int cp_vendor:8; /* company identifier */ 364 u_int pad1:8; /* reserved */ 365#endif 366 } cpu; 367}; 368 369#endif /* !_LOCORE */ 370 371/* 372 * CTL_MACHDEP definitions. 373 */ 374#define CPU_CONSDEV 1 /* dev_t: console terminal device */ 375#define CPU_ADJKERNTZ 2 /* int: timezone offset (seconds) */ 376#define CPU_DISRTCSET 3 /* int: disable resettodr() call */ 377#define CPU_BOOTINFO 4 /* struct: bootinfo */ 378#define CPU_WALLCLOCK 5 /* int: indicates wall CMOS clock */ 379#define CPU_MAXID 6 /* number of valid machdep ids */ 380 381#define CTL_MACHDEP_NAMES { \ 382 { 0, 0 }, \ 383 { "console_device", CTLTYPE_STRUCT }, \ 384 { "adjkerntz", CTLTYPE_INT }, \ 385 { "disable_rtc_set", CTLTYPE_INT }, \ 386 { "bootinfo", CTLTYPE_STRUCT }, \ 387 { "wall_cmos_clock", CTLTYPE_INT }, \ 388} 389 390/* 391 * MIPS CPU types (cp_imp). 392 */ 393#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 394#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 395#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 396#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 397#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 398#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 399#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 400#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 401#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 402#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 403#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ 404#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 405#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 406#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 407#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 408#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 409#define MIPS_RM7000 0x27 /* QED RM7000 CPU ISA IV */ 410#define MIPS_RM52X0 0x28 /* QED RM52X0 CPU ISA IV */ 411#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ 412#define MIPS_RM9000 0x34 /* E9000 CPU */ 413 414/* 415 * MIPS FPU types 416 */ 417#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 418#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 419#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 420#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 421#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 422#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */ 423#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 424#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ 425#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */ 426#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */ 427#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 428#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 429#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */ 430#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 431#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */ 432#define MIPS_RM7000 0x27 /* QED RM7000 FPU ISA IV */ 433#define MIPS_RM5230 0x28 /* QED RM52X0 based FPU ISA IV */ 434#define MIPS_RM52XX 0x28 /* QED RM52X0 based FPU ISA IV */ 435#define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+ */ 436 437#ifndef _LOCORE 438extern union cpuprid cpu_id; 439 440#define mips_proc_type() ((cpu_id.cpu.cp_vendor << 8) | cpu_id.cpu.cp_imp) 441#define mips_set_proc_type(type) (cpu_id.cpu.cp_vendor = (type) >> 8, \ 442 cpu_id.cpu.cp_imp = ((type) & 0x00ff)) 443#endif /* !_LOCORE */ 444 445#if defined(_KERNEL) && !defined(_LOCORE) 446extern union cpuprid fpu_id; 447 448struct tlb; 449struct user; 450 451u_int32_t mips_cp0_config1_read(void); 452int Mips_ConfigCache(void); 453void Mips_SetWIRED(int); 454void Mips_SetPID(int); 455u_int Mips_GetCOUNT(void); 456void Mips_SetCOMPARE(u_int); 457u_int Mips_GetCOMPARE(void); 458 459void Mips_SyncCache(void); 460void Mips_SyncDCache(vm_offset_t, int); 461void Mips_HitSyncDCache(vm_offset_t, int); 462void Mips_HitSyncSCache(vm_offset_t, int); 463void Mips_IOSyncDCache(vm_offset_t, int, int); 464void Mips_HitInvalidateDCache(vm_offset_t, int); 465void Mips_SyncICache(vm_offset_t, int); 466void Mips_InvalidateICache(vm_offset_t, int); 467 468void Mips_TLBFlush(int); 469void Mips_TLBFlushAddr(vm_offset_t); 470void Mips_TLBWriteIndexed(int, struct tlb *); 471void Mips_TLBUpdate(vm_offset_t, unsigned); 472void Mips_TLBRead(int, struct tlb *); 473void mips_TBIAP(int); 474void wbflush(void); 475 476extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */ 477extern u_int32_t cpu_counter_last; /* Last compare value loaded */ 478extern int num_tlbentries; 479extern char btext[]; 480extern char etext[]; 481extern int intr_nesting_level; 482 483#define func_0args_asmmacro(func, in) \ 484 __asm __volatile ( "jalr %0" \ 485 : "=r" (in) /* outputs */ \ 486 : "r" (func) /* inputs */ \ 487 : "$31", "$4"); 488 489#define func_1args_asmmacro(func, arg0) \ 490 __asm __volatile ("move $4, %1;" \ 491 "jalr %0" \ 492 : /* outputs */ \ 493 : "r" (func), "r" (arg0) /* inputs */ \ 494 : "$31", "$4"); 495 496#define func_2args_asmmacro(func, arg0, arg1) \ 497 __asm __volatile ("move $4, %1;" \ 498 "move $5, %2;" \ 499 "jalr %0" \ 500 : /* outputs */ \ 501 : "r" (func), "r" (arg0), "r" (arg1) /* inputs */ \ 502 : "$31", "$4", "$5"); 503 504#define func_3args_asmmacro(func, arg0, arg1, arg2) \ 505 __asm __volatile ( "move $4, %1;" \ 506 "move $5, %2;" \ 507 "move $6, %3;" \ 508 "jalr %0" \ 509 : /* outputs */ \ 510 : "r" (func), "r" (arg0), "r" (arg1), "r" (arg2) /* inputs */ \ 511 : "$31", "$4", "$5", "$6"); 512 513#define MachSetPID Mips_SetPID 514#define MachTLBUpdate Mips_TLBUpdate 515#define mips_TBIS Mips_TLBFlushAddr 516#define MIPS_TBIAP() mips_TBIAP(num_tlbentries) 517#define MachSetWIRED(index) Mips_SetWIRED(index) 518#define MachTLBFlush(count) Mips_TLBFlush(count) 519#define MachTLBGetPID(pid) (pid = Mips_TLBGetPID()) 520#define MachTLBRead(tlbno, tlbp) Mips_TLBRead(tlbno, tlbp) 521#define MachFPTrap(sr, cause, pc) MipsFPTrap(sr, cause, pc) 522 523/* 524 * Enable realtime clock (always enabled). 525 */ 526#define enablertclock() 527 528/* 529 * Are we in an interrupt handler? required by JunOS 530 */ 531#define IN_INT_HANDLER() \ 532 (curthread->td_intr_nesting_level != 0 || \ 533 (curthread->td_pflags & TDP_ITHREAD)) 534 535/* 536 * Low level access routines to CPU registers 537 */ 538 539void setsoftintr0(void); 540void clearsoftintr0(void); 541void setsoftintr1(void); 542void clearsoftintr1(void); 543 544 545u_int32_t mips_cp0_status_read(void); 546void mips_cp0_status_write(u_int32_t); 547 548int disableintr(void); 549void restoreintr(int); 550int enableintr(void); 551int Mips_TLBGetPID(void); 552 553void swi_vm(void *); 554void cpu_halt(void); 555void cpu_reset(void); 556 557u_int32_t set_intr_mask(u_int32_t); 558u_int32_t get_intr_mask(void); 559u_int32_t get_cyclecount(void); 560 561#define cpu_spinwait() /* nothing */ 562 563#endif /* _KERNEL */ 564#endif /* !_MACHINE_CPU_H_ */ 565