cpu.h revision 202031
1178172Simp/* $OpenBSD: cpu.h,v 1.4 1998/09/15 10:50:12 pefo Exp $ */ 2178172Simp 3178172Simp/*- 4178172Simp * Copyright (c) 1992, 1993 5178172Simp * The Regents of the University of California. All rights reserved. 6178172Simp * 7178172Simp * This code is derived from software contributed to Berkeley by 8178172Simp * Ralph Campbell and Rick Macklem. 9178172Simp * 10178172Simp * Redistribution and use in source and binary forms, with or without 11178172Simp * modification, are permitted provided that the following conditions 12178172Simp * are met: 13178172Simp * 1. Redistributions of source code must retain the above copyright 14178172Simp * notice, this list of conditions and the following disclaimer. 15178172Simp * 2. Redistributions in binary form must reproduce the above copyright 16178172Simp * notice, this list of conditions and the following disclaimer in the 17178172Simp * documentation and/or other materials provided with the distribution. 18178172Simp * 4. Neither the name of the University nor the names of its contributors 19178172Simp * may be used to endorse or promote products derived from this software 20178172Simp * without specific prior written permission. 21178172Simp * 22178172Simp * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23178172Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24178172Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25178172Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26178172Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27178172Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28178172Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29178172Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30178172Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31178172Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32178172Simp * SUCH DAMAGE. 33178172Simp * 34178172Simp * Copyright (C) 1989 Digital Equipment Corporation. 35178172Simp * Permission to use, copy, modify, and distribute this software and 36178172Simp * its documentation for any purpose and without fee is hereby granted, 37178172Simp * provided that the above copyright notice appears in all copies. 38178172Simp * Digital Equipment Corporation makes no representations about the 39178172Simp * suitability of this software for any purpose. It is provided "as is" 40178172Simp * without express or implied warranty. 41178172Simp * 42178172Simp * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43178172Simp * JNPR: cpu.h,v 1.9.2.2 2007/09/10 08:23:46 girish 44178172Simp * $FreeBSD: head/sys/mips/include/cpu.h 202031 2010-01-10 19:50:24Z imp $ 45178172Simp */ 46178172Simp 47178172Simp#ifndef _MACHINE_CPU_H_ 48178172Simp#define _MACHINE_CPU_H_ 49178172Simp 50178172Simp#include <machine/psl.h> 51178172Simp#include <machine/endian.h> 52178172Simp 53178172Simp#define MIPS_CACHED_MEMORY_ADDR 0x80000000 54178172Simp#define MIPS_UNCACHED_MEMORY_ADDR 0xa0000000 55178172Simp#define MIPS_MAX_MEM_ADDR 0xbe000000 56178172Simp#define MIPS_RESERVED_ADDR 0xbfc80000 57178172Simp 58178172Simp#define MIPS_KSEG0_LARGEST_PHYS 0x20000000 59202031Simp#define MIPS_CACHED_TO_PHYS(x) ((uintptr_t)(x) & 0x1fffffff) 60202031Simp#define MIPS_PHYS_TO_CACHED(x) ((uintptr_t)(x) | MIPS_CACHED_MEMORY_ADDR) 61202031Simp#define MIPS_UNCACHED_TO_PHYS(x) ((uintptr_t)(x) & 0x1fffffff) 62202031Simp#define MIPS_PHYS_TO_UNCACHED(x) ((uintptr_t)(x) | MIPS_UNCACHED_MEMORY_ADDR) 63178172Simp 64178172Simp#define MIPS_PHYS_MASK (0x1fffffff) 65178172Simp#define MIPS_PA_2_K1VA(x) (MIPS_KSEG1_START | ((x) & MIPS_PHYS_MASK)) 66178172Simp 67202031Simp#define MIPS_VA_TO_CINDEX(x) ((uintptr_t)(x) & 0xffffff | MIPS_CACHED_MEMORY_ADDR) 68178172Simp#define MIPS_CACHED_TO_UNCACHED(x) (MIPS_PHYS_TO_UNCACHED(MIPS_CACHED_TO_PHYS(x))) 69178172Simp 70202031Simp#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) 71202031Simp#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START) 72202031Simp#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 73202031Simp#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 74178172Simp 75202031Simp#define MIPS_IS_KSEG0_ADDR(x) \ 76202031Simp (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \ 77202031Simp ((vm_offset_t)(x) <= MIPS_KSEG0_END)) 78202031Simp#define MIPS_IS_KSEG1_ADDR(x) \ 79202031Simp (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \ 80202031Simp ((vm_offset_t)(x) <= MIPS_KSEG1_END)) 81202031Simp#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \ 82202031Simp MIPS_IS_KSEG1_ADDR(x)) 83202031Simp 84178172Simp/* 85178172Simp * Status register. 86178172Simp */ 87178172Simp#define SR_COP_USABILITY 0xf0000000 88178172Simp#define SR_COP_0_BIT 0x10000000 89178172Simp#define SR_COP_1_BIT 0x20000000 90178172Simp#define SR_COP_2_BIT 0x40000000 91178172Simp#define SR_RP 0x08000000 92178172Simp#define SR_FR_32 0x04000000 93178172Simp#define SR_RE 0x02000000 94178172Simp#define SR_PX 0x00800000 95178172Simp#define SR_BOOT_EXC_VEC 0x00400000 96178172Simp#define SR_TLB_SHUTDOWN 0x00200000 97178172Simp#define SR_SOFT_RESET 0x00100000 98178172Simp#define SR_DIAG_CH 0x00040000 99178172Simp#define SR_DIAG_CE 0x00020000 100178172Simp#define SR_DIAG_DE 0x00010000 101178172Simp#define SR_KX 0x00000080 102178172Simp#define SR_SX 0x00000040 103178172Simp#define SR_UX 0x00000020 104178172Simp#define SR_KSU_MASK 0x00000018 105178172Simp#define SR_KSU_USER 0x00000010 106178172Simp#define SR_KSU_SUPER 0x00000008 107178172Simp#define SR_KSU_KERNEL 0x00000000 108178172Simp#define SR_ERL 0x00000004 109178172Simp#define SR_EXL 0x00000002 110178172Simp#define SR_INT_ENAB 0x00000001 111178172Simp 112178172Simp#define SR_INT_MASK 0x0000ff00 113178172Simp#define SOFT_INT_MASK_0 0x00000100 114178172Simp#define SOFT_INT_MASK_1 0x00000200 115178172Simp#define SR_INT_MASK_0 0x00000400 116178172Simp#define SR_INT_MASK_1 0x00000800 117178172Simp#define SR_INT_MASK_2 0x00001000 118178172Simp#define SR_INT_MASK_3 0x00002000 119178172Simp#define SR_INT_MASK_4 0x00004000 120178172Simp#define SR_INT_MASK_5 0x00008000 121178172Simp#define ALL_INT_MASK SR_INT_MASK 122178172Simp#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 123178172Simp#define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK) 124178172Simp 125178172Simp 126178172Simp/* 127178172Simp * The bits in the cause register. 128178172Simp * 129178172Simp * CR_BR_DELAY Exception happened in branch delay slot. 130178172Simp * CR_COP_ERR Coprocessor error. 131178172Simp * CR_IP Interrupt pending bits defined below. 132178172Simp * CR_EXC_CODE The exception type (see exception codes below). 133178172Simp */ 134178172Simp#define CR_BR_DELAY 0x80000000 135178172Simp#define CR_COP_ERR 0x30000000 136178172Simp#define CR_EXC_CODE 0x0000007c 137178172Simp#define CR_EXC_CODE_SHIFT 2 138178172Simp#define CR_IPEND 0x0000ff00 139178172Simp 140178172Simp/* 141178172Simp * Cause Register Format: 142178172Simp * 143178172Simp * 31 30 29 28 27 26 25 24 23 8 7 6 2 1 0 144178172Simp * ---------------------------------------------------------------------- 145178172Simp * | BD | 0| CE | 0| W2| W1| IV| IP15 - IP0 | 0| Exc Code | 0| 146178172Simp * |______________________________________________________________________ 147178172Simp */ 148178172Simp 149178172Simp#define CR_INT_SOFT0 0x00000100 150178172Simp#define CR_INT_SOFT1 0x00000200 151178172Simp#define CR_INT_0 0x00000400 152178172Simp#define CR_INT_1 0x00000800 153178172Simp#define CR_INT_2 0x00001000 154178172Simp#define CR_INT_3 0x00002000 155178172Simp#define CR_INT_4 0x00004000 156178172Simp#define CR_INT_5 0x00008000 157178172Simp 158178172Simp#define CR_INT_UART CR_INT_1 159178172Simp#define CR_INT_IPI CR_INT_2 160178172Simp#define CR_INT_CLOCK CR_INT_5 161178172Simp 162178172Simp/* 163178172Simp * The bits in the CONFIG register 164178172Simp */ 165178172Simp#define CFG_K0_UNCACHED 2 166202031Simp#if defined(CPU_SB1) 167202031Simp#define CFG_K0_COHERENT 5 /* cacheable coherent */ 168202031Simp#else 169178172Simp#define CFG_K0_CACHED 3 170202031Simp#endif 171178172Simp 172178172Simp/* 173178172Simp * The bits in the context register. 174178172Simp */ 175178172Simp#define CNTXT_PTE_BASE 0xff800000 176178172Simp#define CNTXT_BAD_VPN2 0x007ffff0 177178172Simp 178178172Simp/* 179178172Simp * Location of exception vectors. 180178172Simp */ 181178172Simp#define RESET_EXC_VEC 0xbfc00000 182178172Simp#define TLB_MISS_EXC_VEC 0x80000000 183178172Simp#define XTLB_MISS_EXC_VEC 0x80000080 184178172Simp#define CACHE_ERR_EXC_VEC 0x80000100 185178172Simp#define GEN_EXC_VEC 0x80000180 186178172Simp 187178172Simp/* 188178172Simp * Coprocessor 0 registers: 189178172Simp */ 190178172Simp#define COP_0_TLB_INDEX $0 191178172Simp#define COP_0_TLB_RANDOM $1 192178172Simp#define COP_0_TLB_LO0 $2 193178172Simp#define COP_0_TLB_LO1 $3 194178172Simp#define COP_0_TLB_CONTEXT $4 195178172Simp#define COP_0_TLB_PG_MASK $5 196178172Simp#define COP_0_TLB_WIRED $6 197178172Simp#define COP_0_INFO $7 198178172Simp#define COP_0_BAD_VADDR $8 199178172Simp#define COP_0_COUNT $9 200178172Simp#define COP_0_TLB_HI $10 201178172Simp#define COP_0_COMPARE $11 202178172Simp#define COP_0_STATUS_REG $12 203178172Simp#define COP_0_CAUSE_REG $13 204178172Simp#define COP_0_EXC_PC $14 205178172Simp#define COP_0_PRID $15 206178172Simp#define COP_0_CONFIG $16 207178172Simp#define COP_0_LLADDR $17 208178172Simp#define COP_0_WATCH_LO $18 209178172Simp#define COP_0_WATCH_HI $19 210178172Simp#define COP_0_TLB_XCONTEXT $20 211178172Simp#define COP_0_ECC $26 212178172Simp#define COP_0_CACHE_ERR $27 213178172Simp#define COP_0_TAG_LO $28 214178172Simp#define COP_0_TAG_HI $29 215178172Simp#define COP_0_ERROR_PC $30 216178172Simp 217178172Simp/* 218178172Simp * Coprocessor 0 Set 1 219178172Simp */ 220178172Simp#define C0P_1_IPLLO $18 221178172Simp#define C0P_1_IPLHI $19 222178172Simp#define C0P_1_INTCTL $20 223178172Simp#define C0P_1_DERRADDR0 $26 224178172Simp#define C0P_1_DERRADDR1 $27 225178172Simp 226178172Simp/* 227178172Simp * Values for the code field in a break instruction. 228178172Simp */ 229178172Simp#define BREAK_INSTR 0x0000000d 230178172Simp#define BREAK_VAL_MASK 0x03ffffc0 231178172Simp#define BREAK_VAL_SHIFT 16 232178172Simp#define BREAK_KDB_VAL 512 233178172Simp#define BREAK_SSTEP_VAL 513 234178172Simp#define BREAK_BRKPT_VAL 514 235178172Simp#define BREAK_SOVER_VAL 515 236178172Simp#define BREAK_DDB_VAL 516 237178172Simp#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 238178172Simp#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 239178172Simp#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 240178172Simp#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 241178172Simp#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) 242178172Simp 243178172Simp/* 244178172Simp * Mininum and maximum cache sizes. 245178172Simp */ 246178172Simp#define MIN_CACHE_SIZE (16 * 1024) 247178172Simp#define MAX_CACHE_SIZE (256 * 1024) 248178172Simp 249178172Simp/* 250178172Simp * The floating point version and status registers. 251178172Simp */ 252178172Simp#define FPC_ID $0 253178172Simp#define FPC_CSR $31 254178172Simp 255178172Simp/* 256178172Simp * The floating point coprocessor status register bits. 257178172Simp */ 258178172Simp#define FPC_ROUNDING_BITS 0x00000003 259178172Simp#define FPC_ROUND_RN 0x00000000 260178172Simp#define FPC_ROUND_RZ 0x00000001 261178172Simp#define FPC_ROUND_RP 0x00000002 262178172Simp#define FPC_ROUND_RM 0x00000003 263178172Simp#define FPC_STICKY_BITS 0x0000007c 264178172Simp#define FPC_STICKY_INEXACT 0x00000004 265178172Simp#define FPC_STICKY_UNDERFLOW 0x00000008 266178172Simp#define FPC_STICKY_OVERFLOW 0x00000010 267178172Simp#define FPC_STICKY_DIV0 0x00000020 268178172Simp#define FPC_STICKY_INVALID 0x00000040 269178172Simp#define FPC_ENABLE_BITS 0x00000f80 270178172Simp#define FPC_ENABLE_INEXACT 0x00000080 271178172Simp#define FPC_ENABLE_UNDERFLOW 0x00000100 272178172Simp#define FPC_ENABLE_OVERFLOW 0x00000200 273178172Simp#define FPC_ENABLE_DIV0 0x00000400 274178172Simp#define FPC_ENABLE_INVALID 0x00000800 275178172Simp#define FPC_EXCEPTION_BITS 0x0003f000 276178172Simp#define FPC_EXCEPTION_INEXACT 0x00001000 277178172Simp#define FPC_EXCEPTION_UNDERFLOW 0x00002000 278178172Simp#define FPC_EXCEPTION_OVERFLOW 0x00004000 279178172Simp#define FPC_EXCEPTION_DIV0 0x00008000 280178172Simp#define FPC_EXCEPTION_INVALID 0x00010000 281178172Simp#define FPC_EXCEPTION_UNIMPL 0x00020000 282178172Simp#define FPC_COND_BIT 0x00800000 283178172Simp#define FPC_FLUSH_BIT 0x01000000 284178172Simp#define FPC_MBZ_BITS 0xfe7c0000 285178172Simp 286178172Simp/* 287178172Simp * Constants to determine if have a floating point instruction. 288178172Simp */ 289178172Simp#define OPCODE_SHIFT 26 290178172Simp#define OPCODE_C1 0x11 291178172Simp 292178172Simp/* 293178172Simp * The low part of the TLB entry. 294178172Simp */ 295178172Simp#define VMTLB_PF_NUM 0x3fffffc0 296178172Simp#define VMTLB_ATTR_MASK 0x00000038 297178172Simp#define VMTLB_MOD_BIT 0x00000004 298178172Simp#define VMTLB_VALID_BIT 0x00000002 299178172Simp#define VMTLB_GLOBAL_BIT 0x00000001 300178172Simp 301178172Simp#define VMTLB_PHYS_PAGE_SHIFT 6 302178172Simp 303178172Simp/* 304178172Simp * The high part of the TLB entry. 305178172Simp */ 306178172Simp#define VMTLB_VIRT_PAGE_NUM 0xffffe000 307178172Simp#define VMTLB_PID 0x000000ff 308178172Simp#define VMTLB_PID_R9K 0x00000fff 309178172Simp#define VMTLB_PID_SHIFT 0 310178172Simp#define VMTLB_VIRT_PAGE_SHIFT 12 311178172Simp#define VMTLB_VIRT_PAGE_SHIFT_R9K 13 312178172Simp 313178172Simp/* 314178172Simp * The first TLB entry that write random hits. 315178172Simp */ 316178172Simp#define VMWIRED_ENTRIES 1 317178172Simp 318178172Simp/* 319178172Simp * The number of process id entries. 320178172Simp */ 321178172Simp#define VMNUM_PIDS 256 322178172Simp 323178172Simp/* 324178172Simp * TLB probe return codes. 325178172Simp */ 326178172Simp#define VMTLB_NOT_FOUND 0 327178172Simp#define VMTLB_FOUND 1 328178172Simp#define VMTLB_FOUND_WITH_PATCH 2 329178172Simp#define VMTLB_PROBE_ERROR 3 330178172Simp 331178172Simp/* 332178172Simp * Exported definitions unique to mips cpu support. 333178172Simp */ 334178172Simp 335178172Simp/* 336178172Simp * definitions of cpu-dependent requirements 337178172Simp * referenced in generic code 338178172Simp */ 339178172Simp#define COPY_SIGCODE /* copy sigcode above user stack in exec */ 340178172Simp 341178172Simp#define cpu_swapout(p) panic("cpu_swapout: can't get here"); 342178172Simp 343178172Simp#ifndef _LOCORE 344178172Simp#include <machine/frame.h> 345178172Simp/* 346178172Simp * Arguments to hardclock and gatherstats encapsulate the previous 347178172Simp * machine state in an opaque clockframe. 348178172Simp */ 349178172Simp#define clockframe trapframe /* Use normal trap frame */ 350178172Simp 351178172Simp#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 352178172Simp#define CLKF_BASEPRI(framep) ((framep)->cpl == 0) 353178172Simp#define CLKF_PC(framep) ((framep)->pc) 354178172Simp#define CLKF_INTR(framep) (0) 355178172Simp#define MIPS_CLKF_INTR() (intr_nesting_level >= 1) 356178172Simp#define TRAPF_USERMODE(framep) (((framep)->sr & SR_KSU_USER) != 0) 357178172Simp#define TRAPF_PC(framep) ((framep)->pc) 358178172Simp#define cpu_getstack(td) ((td)->td_frame->sp) 359178172Simp 360178172Simp/* 361178172Simp * CPU identification, from PRID register. 362178172Simp */ 363178172Simpunion cpuprid { 364178172Simp int cpuprid; 365178172Simp struct { 366178172Simp#if BYTE_ORDER == BIG_ENDIAN 367178172Simp u_int pad1:8; /* reserved */ 368178172Simp u_int cp_vendor:8; /* company identifier */ 369178172Simp u_int cp_imp:8; /* implementation identifier */ 370178172Simp u_int cp_majrev:4; /* major revision identifier */ 371178172Simp u_int cp_minrev:4; /* minor revision identifier */ 372178172Simp#else 373178172Simp u_int cp_minrev:4; /* minor revision identifier */ 374178172Simp u_int cp_majrev:4; /* major revision identifier */ 375178172Simp u_int cp_imp:8; /* implementation identifier */ 376178172Simp u_int cp_vendor:8; /* company identifier */ 377178172Simp u_int pad1:8; /* reserved */ 378178172Simp#endif 379178172Simp } cpu; 380178172Simp}; 381178172Simp 382178172Simp#endif /* !_LOCORE */ 383178172Simp 384178172Simp/* 385178172Simp * CTL_MACHDEP definitions. 386178172Simp */ 387178172Simp#define CPU_CONSDEV 1 /* dev_t: console terminal device */ 388178172Simp#define CPU_ADJKERNTZ 2 /* int: timezone offset (seconds) */ 389178172Simp#define CPU_DISRTCSET 3 /* int: disable resettodr() call */ 390178172Simp#define CPU_BOOTINFO 4 /* struct: bootinfo */ 391178172Simp#define CPU_WALLCLOCK 5 /* int: indicates wall CMOS clock */ 392178172Simp#define CPU_MAXID 6 /* number of valid machdep ids */ 393178172Simp 394178172Simp#define CTL_MACHDEP_NAMES { \ 395178172Simp { 0, 0 }, \ 396178172Simp { "console_device", CTLTYPE_STRUCT }, \ 397178172Simp { "adjkerntz", CTLTYPE_INT }, \ 398178172Simp { "disable_rtc_set", CTLTYPE_INT }, \ 399178172Simp { "bootinfo", CTLTYPE_STRUCT }, \ 400178172Simp { "wall_cmos_clock", CTLTYPE_INT }, \ 401178172Simp} 402178172Simp 403178172Simp/* 404178172Simp * MIPS CPU types (cp_imp). 405178172Simp */ 406178172Simp#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 407178172Simp#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 408178172Simp#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 409178172Simp#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 410178172Simp#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 411178172Simp#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 412178172Simp#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 413178172Simp#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 414178172Simp#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 415178172Simp#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 416178172Simp#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ 417178172Simp#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 418178172Simp#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 419178172Simp#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 420178172Simp#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 421178172Simp#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 422178172Simp#define MIPS_RM7000 0x27 /* QED RM7000 CPU ISA IV */ 423178172Simp#define MIPS_RM52X0 0x28 /* QED RM52X0 CPU ISA IV */ 424178172Simp#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ 425178172Simp#define MIPS_RM9000 0x34 /* E9000 CPU */ 426178172Simp 427178172Simp/* 428178172Simp * MIPS FPU types 429178172Simp */ 430178172Simp#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 431178172Simp#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 432178172Simp#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 433178172Simp#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 434178172Simp#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 435178172Simp#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */ 436178172Simp#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 437178172Simp#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ 438178172Simp#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */ 439178172Simp#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */ 440178172Simp#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 441178172Simp#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 442178172Simp#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */ 443178172Simp#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 444178172Simp#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */ 445178172Simp#define MIPS_RM7000 0x27 /* QED RM7000 FPU ISA IV */ 446178172Simp#define MIPS_RM5230 0x28 /* QED RM52X0 based FPU ISA IV */ 447178172Simp#define MIPS_RM52XX 0x28 /* QED RM52X0 based FPU ISA IV */ 448178172Simp#define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+ */ 449178172Simp 450178172Simp#ifndef _LOCORE 451178172Simpextern union cpuprid cpu_id; 452178172Simp 453178172Simp#define mips_proc_type() ((cpu_id.cpu.cp_vendor << 8) | cpu_id.cpu.cp_imp) 454178172Simp#define mips_set_proc_type(type) (cpu_id.cpu.cp_vendor = (type) >> 8, \ 455178172Simp cpu_id.cpu.cp_imp = ((type) & 0x00ff)) 456178172Simp#endif /* !_LOCORE */ 457178172Simp 458178172Simp#if defined(_KERNEL) && !defined(_LOCORE) 459178172Simpextern union cpuprid fpu_id; 460178172Simp 461178172Simpstruct tlb; 462178172Simpstruct user; 463178172Simp 464178172Simpu_int32_t mips_cp0_config1_read(void); 465178172Simpint Mips_ConfigCache(void); 466178172Simpvoid Mips_SetWIRED(int); 467178172Simpvoid Mips_SetPID(int); 468178172Simpu_int Mips_GetCOUNT(void); 469178172Simpvoid Mips_SetCOMPARE(u_int); 470178172Simpu_int Mips_GetCOMPARE(void); 471178172Simp 472178172Simpvoid Mips_SyncCache(void); 473178172Simpvoid Mips_SyncDCache(vm_offset_t, int); 474178172Simpvoid Mips_HitSyncDCache(vm_offset_t, int); 475178172Simpvoid Mips_HitSyncSCache(vm_offset_t, int); 476178172Simpvoid Mips_IOSyncDCache(vm_offset_t, int, int); 477178172Simpvoid Mips_HitInvalidateDCache(vm_offset_t, int); 478178172Simpvoid Mips_SyncICache(vm_offset_t, int); 479178172Simpvoid Mips_InvalidateICache(vm_offset_t, int); 480178172Simp 481178172Simpvoid Mips_TLBFlush(int); 482178172Simpvoid Mips_TLBFlushAddr(vm_offset_t); 483178172Simpvoid Mips_TLBWriteIndexed(int, struct tlb *); 484178172Simpvoid Mips_TLBUpdate(vm_offset_t, unsigned); 485178172Simpvoid Mips_TLBRead(int, struct tlb *); 486178172Simpvoid mips_TBIAP(int); 487178172Simpvoid wbflush(void); 488178172Simp 489178172Simpextern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */ 490178172Simpextern u_int32_t cpu_counter_last; /* Last compare value loaded */ 491178172Simpextern int num_tlbentries; 492178172Simpextern char btext[]; 493178172Simpextern char etext[]; 494178172Simpextern int intr_nesting_level; 495178172Simp 496178172Simp#define func_0args_asmmacro(func, in) \ 497178172Simp __asm __volatile ( "jalr %0" \ 498178172Simp : "=r" (in) /* outputs */ \ 499178172Simp : "r" (func) /* inputs */ \ 500178172Simp : "$31", "$4"); 501178172Simp 502178172Simp#define func_1args_asmmacro(func, arg0) \ 503178172Simp __asm __volatile ("move $4, %1;" \ 504178172Simp "jalr %0" \ 505178172Simp : /* outputs */ \ 506178172Simp : "r" (func), "r" (arg0) /* inputs */ \ 507178172Simp : "$31", "$4"); 508178172Simp 509178172Simp#define func_2args_asmmacro(func, arg0, arg1) \ 510178172Simp __asm __volatile ("move $4, %1;" \ 511178172Simp "move $5, %2;" \ 512178172Simp "jalr %0" \ 513178172Simp : /* outputs */ \ 514178172Simp : "r" (func), "r" (arg0), "r" (arg1) /* inputs */ \ 515178172Simp : "$31", "$4", "$5"); 516178172Simp 517178172Simp#define func_3args_asmmacro(func, arg0, arg1, arg2) \ 518178172Simp __asm __volatile ( "move $4, %1;" \ 519178172Simp "move $5, %2;" \ 520178172Simp "move $6, %3;" \ 521178172Simp "jalr %0" \ 522178172Simp : /* outputs */ \ 523178172Simp : "r" (func), "r" (arg0), "r" (arg1), "r" (arg2) /* inputs */ \ 524178172Simp : "$31", "$4", "$5", "$6"); 525178172Simp 526178172Simp#define MachSetPID Mips_SetPID 527178172Simp#define MachTLBUpdate Mips_TLBUpdate 528178172Simp#define mips_TBIS Mips_TLBFlushAddr 529178172Simp#define MIPS_TBIAP() mips_TBIAP(num_tlbentries) 530178172Simp#define MachSetWIRED(index) Mips_SetWIRED(index) 531178172Simp#define MachTLBFlush(count) Mips_TLBFlush(count) 532178172Simp#define MachTLBGetPID(pid) (pid = Mips_TLBGetPID()) 533178172Simp#define MachTLBRead(tlbno, tlbp) Mips_TLBRead(tlbno, tlbp) 534178172Simp#define MachFPTrap(sr, cause, pc) MipsFPTrap(sr, cause, pc) 535178172Simp 536178172Simp/* 537178172Simp * Enable realtime clock (always enabled). 538178172Simp */ 539178172Simp#define enablertclock() 540178172Simp 541178172Simp/* 542178172Simp * Are we in an interrupt handler? required by JunOS 543178172Simp */ 544178172Simp#define IN_INT_HANDLER() \ 545178172Simp (curthread->td_intr_nesting_level != 0 || \ 546178172Simp (curthread->td_pflags & TDP_ITHREAD)) 547178172Simp 548178172Simp/* 549178172Simp * Low level access routines to CPU registers 550178172Simp */ 551178172Simp 552178172Simpvoid setsoftintr0(void); 553178172Simpvoid clearsoftintr0(void); 554178172Simpvoid setsoftintr1(void); 555178172Simpvoid clearsoftintr1(void); 556178172Simp 557178172Simp 558178172Simpu_int32_t mips_cp0_status_read(void); 559178172Simpvoid mips_cp0_status_write(u_int32_t); 560178172Simp 561178172Simpint disableintr(void); 562178172Simpvoid restoreintr(int); 563178172Simpint enableintr(void); 564178172Simpint Mips_TLBGetPID(void); 565178172Simp 566178172Simpvoid swi_vm(void *); 567178172Simpvoid cpu_halt(void); 568178172Simpvoid cpu_reset(void); 569178172Simp 570178172Simpu_int32_t set_intr_mask(u_int32_t); 571178172Simpu_int32_t get_intr_mask(void); 572178172Simpu_int32_t get_cyclecount(void); 573178172Simp 574178172Simp#define cpu_spinwait() /* nothing */ 575178172Simp 576178172Simp#endif /* _KERNEL */ 577178172Simp#endif /* !_MACHINE_CPU_H_ */ 578