cache.h revision 178172
1/* $NetBSD: cache.h,v 1.6 2003/02/17 11:35:01 simonb Exp $ */ 2 3/* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * 37 * $FreeBSD: head/sys/mips/include/cache.h 178172 2008-04-13 07:27:37Z imp $ 38 */ 39 40/* 41 * Cache operations. 42 * 43 * We define the following primitives: 44 * 45 * --- Instruction cache synchronization (mandatory): 46 * 47 * icache_sync_all Synchronize I-cache 48 * 49 * icache_sync_range Synchronize I-cache range 50 * 51 * icache_sync_range_index (index ops) 52 * 53 * --- Primary data cache (mandatory): 54 * 55 * pdcache_wbinv_all Write-back Invalidate primary D-cache 56 * 57 * pdcache_wbinv_range Write-back Invalidate primary D-cache range 58 * 59 * pdcache_wbinv_range_index (index ops) 60 * 61 * pdcache_inv_range Invalidate primary D-cache range 62 * 63 * pdcache_wb_range Write-back primary D-cache range 64 * 65 * --- Secondary data cache (optional): 66 * 67 * sdcache_wbinv_all Write-back Invalidate secondary D-cache 68 * 69 * sdcache_wbinv_range Write-back Invalidate secondary D-cache range 70 * 71 * sdcache_wbinv_range_index (index ops) 72 * 73 * sdcache_inv_range Invalidate secondary D-cache range 74 * 75 * sdcache_wb_range Write-back secondary D-cache range 76 * 77 * There are some rules that must be followed: 78 * 79 * I-cache Synch (all or range): 80 * The goal is to synchronize the instruction stream, 81 * so you may need to write-back dirty data cache 82 * blocks first. If a range is requested, and you 83 * can't synchronize just a range, you have to hit 84 * the whole thing. 85 * 86 * D-cache Write-back Invalidate range: 87 * If you can't WB-Inv a range, you must WB-Inv the 88 * entire D-cache. 89 * 90 * D-cache Invalidate: 91 * If you can't Inv the D-cache without doing a 92 * Write-back, YOU MUST PANIC. This is to catch 93 * errors in calling code. Callers must be aware 94 * of this scenario, and must handle it appropriately 95 * (consider the bus_dma(9) operations). 96 * 97 * D-cache Write-back: 98 * If you can't Write-back without doing an invalidate, 99 * that's fine. Then treat this as a WB-Inv. Skipping 100 * the invalidate is merely an optimization. 101 * 102 * All operations: 103 * Valid virtual addresses must be passed to the 104 * cache operation. 105 * 106 * Finally, these primitives are grouped together in reasonable 107 * ways. For all operations described here, first the primary 108 * cache is frobbed, then the secondary cache frobbed, if the 109 * operation for the secondary cache exists. 110 * 111 * mips_icache_sync_all Synchronize I-cache 112 * 113 * mips_icache_sync_range Synchronize I-cache range 114 * 115 * mips_icache_sync_range_index (index ops) 116 * 117 * mips_dcache_wbinv_all Write-back Invalidate D-cache 118 * 119 * mips_dcache_wbinv_range Write-back Invalidate D-cache range 120 * 121 * mips_dcache_wbinv_range_index (index ops) 122 * 123 * mips_dcache_inv_range Invalidate D-cache range 124 * 125 * mips_dcache_wb_range Write-back D-cache range 126 */ 127 128struct mips_cache_ops { 129 void (*mco_icache_sync_all)(void); 130 void (*mco_icache_sync_range)(vm_offset_t, vm_size_t); 131 void (*mco_icache_sync_range_index)(vm_offset_t, vm_size_t); 132 133 void (*mco_pdcache_wbinv_all)(void); 134 void (*mco_pdcache_wbinv_range)(vm_offset_t, vm_size_t); 135 void (*mco_pdcache_wbinv_range_index)(vm_offset_t, vm_size_t); 136 void (*mco_pdcache_inv_range)(vm_offset_t, vm_size_t); 137 void (*mco_pdcache_wb_range)(vm_offset_t, vm_size_t); 138 139 /* These are called only by the (mipsNN) icache functions. */ 140 void (*mco_intern_pdcache_wbinv_all)(void); 141 void (*mco_intern_pdcache_wbinv_range_index)(vm_offset_t, vm_size_t); 142 void (*mco_intern_pdcache_wb_range)(vm_offset_t, vm_size_t); 143 144 void (*mco_sdcache_wbinv_all)(void); 145 void (*mco_sdcache_wbinv_range)(vm_offset_t, vm_size_t); 146 void (*mco_sdcache_wbinv_range_index)(vm_offset_t, vm_size_t); 147 void (*mco_sdcache_inv_range)(vm_offset_t, vm_size_t); 148 void (*mco_sdcache_wb_range)(vm_offset_t, vm_size_t); 149 150 /* These are called only by the (mipsNN) icache functions. */ 151 void (*mco_intern_sdcache_wbinv_all)(void); 152 void (*mco_intern_sdcache_wbinv_range_index)(vm_offset_t, vm_size_t); 153 void (*mco_intern_sdcache_wb_range)(vm_offset_t, vm_size_t); 154}; 155 156extern struct mips_cache_ops mips_cache_ops; 157 158/* PRIMARY CACHE VARIABLES */ 159extern u_int mips_picache_size; 160extern u_int mips_picache_line_size; 161extern u_int mips_picache_ways; 162extern u_int mips_picache_way_size; 163extern u_int mips_picache_way_mask; 164 165extern u_int mips_pdcache_size; /* and unified */ 166extern u_int mips_pdcache_line_size; 167extern u_int mips_pdcache_ways; 168extern u_int mips_pdcache_way_size; 169extern u_int mips_pdcache_way_mask; 170extern int mips_pdcache_write_through; 171 172extern int mips_pcache_unified; 173 174/* SECONDARY CACHE VARIABLES */ 175extern u_int mips_sicache_size; 176extern u_int mips_sicache_line_size; 177extern u_int mips_sicache_ways; 178extern u_int mips_sicache_way_size; 179extern u_int mips_sicache_way_mask; 180 181extern u_int mips_sdcache_size; /* and unified */ 182extern u_int mips_sdcache_line_size; 183extern u_int mips_sdcache_ways; 184extern u_int mips_sdcache_way_size; 185extern u_int mips_sdcache_way_mask; 186extern int mips_sdcache_write_through; 187 188extern int mips_scache_unified; 189 190/* TERTIARY CACHE VARIABLES */ 191extern u_int mips_tcache_size; /* always unified */ 192extern u_int mips_tcache_line_size; 193extern u_int mips_tcache_ways; 194extern u_int mips_tcache_way_size; 195extern u_int mips_tcache_way_mask; 196extern int mips_tcache_write_through; 197 198extern u_int mips_dcache_align; 199extern u_int mips_dcache_align_mask; 200 201extern u_int mips_cache_alias_mask; 202extern u_int mips_cache_prefer_mask; 203 204#define __mco_noargs(prefix, x) \ 205do { \ 206 (*mips_cache_ops.mco_ ## prefix ## p ## x )(); \ 207 if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \ 208 (*mips_cache_ops.mco_ ## prefix ## s ## x )(); \ 209} while (/*CONSTCOND*/0) 210 211#define __mco_2args(prefix, x, a, b) \ 212do { \ 213 (*mips_cache_ops.mco_ ## prefix ## p ## x )((a), (b)); \ 214 if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \ 215 (*mips_cache_ops.mco_ ## prefix ## s ## x )((a), (b)); \ 216} while (/*CONSTCOND*/0) 217 218#define mips_icache_sync_all() \ 219 (*mips_cache_ops.mco_icache_sync_all)() 220 221#define mips_icache_sync_range(v, s) \ 222 (*mips_cache_ops.mco_icache_sync_range)((v), (s)) 223 224#define mips_icache_sync_range_index(v, s) \ 225 (*mips_cache_ops.mco_icache_sync_range_index)((v), (s)) 226 227#define mips_dcache_wbinv_all() \ 228 __mco_noargs(, dcache_wbinv_all) 229 230#define mips_dcache_wbinv_range(v, s) \ 231 __mco_2args(, dcache_wbinv_range, (v), (s)) 232 233#define mips_dcache_wbinv_range_index(v, s) \ 234 __mco_2args(, dcache_wbinv_range_index, (v), (s)) 235 236#define mips_dcache_inv_range(v, s) \ 237 __mco_2args(, dcache_inv_range, (v), (s)) 238 239#define mips_dcache_wb_range(v, s) \ 240 __mco_2args(, dcache_wb_range, (v), (s)) 241 242/* 243 * Private D-cache functions only called from (currently only the 244 * mipsNN) I-cache functions. 245 */ 246#define mips_intern_dcache_wbinv_all() \ 247 __mco_noargs(intern_, dcache_wbinv_all) 248 249#define mips_intern_dcache_wbinv_range_index(v, s) \ 250 __mco_2args(intern_, dcache_wbinv_range_index, (v), (s)) 251 252#define mips_intern_dcache_wb_range(v, s) \ 253 __mco_2args(intern_, dcache_wb_range, (v), (s)) 254 255/* forward declaration */ 256struct mips_cpuinfo; 257 258void mips_config_cache(struct mips_cpuinfo *); 259void mips_dcache_compute_align(void); 260 261#include <machine/cache_mipsNN.h> 262