octeon_machdep.c revision 242273
1/*- 2 * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/mips/cavium/octeon_machdep.c 242273 2012-10-29 00:51:53Z jmallett $ 27 */ 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/mips/cavium/octeon_machdep.c 242273 2012-10-29 00:51:53Z jmallett $"); 30 31#include <sys/param.h> 32#include <sys/conf.h> 33#include <sys/kernel.h> 34#include <sys/systm.h> 35#include <sys/imgact.h> 36#include <sys/bio.h> 37#include <sys/buf.h> 38#include <sys/bus.h> 39#include <sys/cpu.h> 40#include <sys/cons.h> 41#include <sys/exec.h> 42#include <sys/ucontext.h> 43#include <sys/proc.h> 44#include <sys/kdb.h> 45#include <sys/ptrace.h> 46#include <sys/reboot.h> 47#include <sys/signalvar.h> 48#include <sys/sysent.h> 49#include <sys/sysproto.h> 50#include <sys/time.h> 51#include <sys/timetc.h> 52#include <sys/user.h> 53 54#include <vm/vm.h> 55#include <vm/vm_object.h> 56#include <vm/vm_page.h> 57#include <vm/vm_pager.h> 58 59#include <machine/atomic.h> 60#include <machine/cache.h> 61#include <machine/clock.h> 62#include <machine/cpu.h> 63#include <machine/cpuregs.h> 64#include <machine/cpufunc.h> 65#include <mips/cavium/octeon_pcmap_regs.h> 66#include <machine/hwfunc.h> 67#include <machine/intr_machdep.h> 68#include <machine/locore.h> 69#include <machine/md_var.h> 70#include <machine/pcpu.h> 71#include <machine/pte.h> 72#include <machine/trap.h> 73#include <machine/vmparam.h> 74 75#include <contrib/octeon-sdk/cvmx.h> 76#include <contrib/octeon-sdk/cvmx-bootmem.h> 77#include <contrib/octeon-sdk/cvmx-ebt3000.h> 78#include <contrib/octeon-sdk/cvmx-interrupt.h> 79#include <contrib/octeon-sdk/cvmx-version.h> 80 81#include <mips/cavium/octeon_irq.h> 82 83#if defined(__mips_n64) 84#define MAX_APP_DESC_ADDR 0xffffffffafffffff 85#else 86#define MAX_APP_DESC_ADDR 0xafffffff 87#endif 88 89#define OCTEON_CLOCK_DEFAULT (500 * 1000 * 1000) 90 91struct octeon_feature_description { 92 octeon_feature_t ofd_feature; 93 const char *ofd_string; 94}; 95 96extern int *edata; 97extern int *end; 98extern char cpu_model[]; 99extern char cpu_board[]; 100 101static const struct octeon_feature_description octeon_feature_descriptions[] = { 102 { OCTEON_FEATURE_SAAD, "SAAD" }, 103 { OCTEON_FEATURE_ZIP, "ZIP" }, 104 { OCTEON_FEATURE_CRYPTO, "CRYPTO" }, 105 { OCTEON_FEATURE_DORM_CRYPTO, "DORM_CRYPTO" }, 106 { OCTEON_FEATURE_PCIE, "PCIE" }, 107 { OCTEON_FEATURE_SRIO, "SRIO" }, 108 { OCTEON_FEATURE_KEY_MEMORY, "KEY_MEMORY" }, 109 { OCTEON_FEATURE_LED_CONTROLLER, "LED_CONTROLLER" }, 110 { OCTEON_FEATURE_TRA, "TRA" }, 111 { OCTEON_FEATURE_MGMT_PORT, "MGMT_PORT" }, 112 { OCTEON_FEATURE_RAID, "RAID" }, 113 { OCTEON_FEATURE_USB, "USB" }, 114 { OCTEON_FEATURE_NO_WPTR, "NO_WPTR" }, 115 { OCTEON_FEATURE_DFA, "DFA" }, 116 { OCTEON_FEATURE_MDIO_CLAUSE_45, "MDIO_CLAUSE_45" }, 117 { OCTEON_FEATURE_NPEI, "NPEI" }, 118 { OCTEON_FEATURE_ILK, "ILK" }, 119 { OCTEON_FEATURE_HFA, "HFA" }, 120 { OCTEON_FEATURE_DFM, "DFM" }, 121 { OCTEON_FEATURE_CIU2, "CIU2" }, 122 { OCTEON_FEATURE_DICI_MODE, "DICI_MODE" }, 123 { OCTEON_FEATURE_BIT_EXTRACTOR, "BIT_EXTRACTOR" }, 124 { OCTEON_FEATURE_NAND, "NAND" }, 125 { OCTEON_FEATURE_MMC, "MMC" }, 126 { OCTEON_FEATURE_PKND, "PKND" }, 127 { OCTEON_FEATURE_CN68XX_WQE, "CN68XX_WQE" }, 128 { 0, NULL } 129}; 130 131uint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip); 132void ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip); 133 134static uint64_t octeon_get_ticks(void); 135static unsigned octeon_get_timecount(struct timecounter *tc); 136 137static void octeon_boot_params_init(register_t ptr); 138 139static struct timecounter octeon_timecounter = { 140 octeon_get_timecount, /* get_timecount */ 141 0, /* no poll_pps */ 142 0xffffffffu, /* octeon_mask */ 143 0, /* frequency */ 144 "Octeon", /* name */ 145 900, /* quality (adjusted in code) */ 146}; 147 148void 149platform_cpu_init() 150{ 151 /* Nothing special yet */ 152} 153 154/* 155 * Perform a board-level soft-reset. 156 */ 157void 158platform_reset(void) 159{ 160 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 161} 162 163/* 164 * octeon_debug_symbol 165 * 166 * Does nothing. 167 * Used to mark the point for simulator to begin tracing 168 */ 169void 170octeon_debug_symbol(void) 171{ 172} 173 174/* 175 * octeon_ciu_reset 176 * 177 * Shutdown all CIU to IP2, IP3 mappings 178 */ 179void 180octeon_ciu_reset(void) 181{ 182 uint64_t cvmctl; 183 184 /* Disable all CIU interrupts by default */ 185 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0); 186 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0); 187 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0); 188 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0); 189 190#ifdef SMP 191 /* Enable the MBOX interrupts. */ 192 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 193 (1ull << (OCTEON_IRQ_MBOX0 - 8)) | 194 (1ull << (OCTEON_IRQ_MBOX1 - 8))); 195#endif 196 197 /* 198 * Move the Performance Counter interrupt to OCTEON_PMC_IRQ 199 */ 200 cvmctl = mips_rd_cvmctl(); 201 cvmctl &= ~(7 << 7); 202 cvmctl |= (OCTEON_PMC_IRQ + 2) << 7; 203 mips_wr_cvmctl(cvmctl); 204} 205 206static void 207octeon_memory_init(void) 208{ 209 vm_paddr_t phys_end; 210 int64_t addr; 211 unsigned i, j; 212 213 phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end)); 214 215 if (octeon_is_simulation()) { 216 /* Simulator we limit to 96 meg */ 217 phys_avail[0] = phys_end; 218 phys_avail[1] = 96 << 20; 219 220 dump_avail[0] = phys_avail[0]; 221 dump_avail[1] = phys_avail[1]; 222 223 realmem = physmem = btoc(phys_avail[1] - phys_avail[0]); 224 return; 225 } 226 227 /* 228 * Allocate memory from bootmem 1MB at a time and merge 229 * adjacent entries. 230 */ 231 i = 0; 232 while (i < PHYS_AVAIL_ENTRIES) { 233 /* 234 * If there is less than 2MB of memory available in 128-byte 235 * blocks, do not steal any more memory. We need to leave some 236 * memory for the command queues to be allocated out of. 237 */ 238 if (cvmx_bootmem_available_mem(128) < 2 << 20) 239 break; 240 241 addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end, 242 ~(vm_paddr_t)0, PAGE_SIZE, 0); 243 if (addr == -1) 244 break; 245 246 /* 247 * The SDK needs to be able to easily map any memory that might 248 * come to it e.g. in the form of an mbuf. Because on !n64 we 249 * can't direct-map some addresses and we don't want to manage 250 * temporary mappings within the SDK, don't feed memory that 251 * can't be direct-mapped to the kernel. 252 */ 253#if !defined(__mips_n64) 254 if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1)) 255 continue; 256#endif 257 258 physmem += btoc(1 << 20); 259 260 if (i > 0 && phys_avail[i - 1] == addr) { 261 phys_avail[i - 1] += 1 << 20; 262 continue; 263 } 264 265 phys_avail[i + 0] = addr; 266 phys_avail[i + 1] = addr + (1 << 20); 267 268 i += 2; 269 } 270 271 for (j = 0; j < i; j++) 272 dump_avail[j] = phys_avail[j]; 273 274 realmem = physmem; 275} 276 277void 278platform_start(__register_t a0, __register_t a1, __register_t a2 __unused, 279 __register_t a3) 280{ 281 const struct octeon_feature_description *ofd; 282 uint64_t platform_counter_freq; 283 284 /* 285 * XXX 286 * octeon_boot_params_init() should be called before anything else, 287 * certainly before any output; we may find out from the boot 288 * descriptor's flags that we're supposed to use the PCI or UART1 289 * consoles rather than UART0. No point doing that reorganization 290 * until we actually intercept UART_DEV_CONSOLE for the UART1 case 291 * and somehow handle the PCI console, which we lack code for 292 * entirely. 293 */ 294 295 mips_postboot_fixup(); 296 297 /* Initialize pcpu stuff */ 298 mips_pcpu0_init(); 299 mips_timer_early_init(OCTEON_CLOCK_DEFAULT); 300 cninit(); 301 302 octeon_ciu_reset(); 303 octeon_boot_params_init(a3); 304 /* 305 * XXX 306 * We can certainly parse command line arguments or U-Boot environment 307 * to determine whether to bootverbose / single user / ... I think 308 * stass has patches to add support for loader things to U-Boot even. 309 */ 310 bootverbose = 1; 311 312 /* 313 * For some reason on the cn38xx simulator ebase register is set to 314 * 0x80001000 at bootup time. Move it back to the default, but 315 * when we move to having support for multiple executives, we need 316 * to rethink this. 317 */ 318 mips_wr_ebase(0x80000000); 319 320 octeon_memory_init(); 321 init_param1(); 322 init_param2(physmem); 323 mips_cpu_init(); 324 pmap_bootstrap(); 325 mips_proc0_init(); 326 mutex_init(); 327 kdb_init(); 328#ifdef KDB 329 if (boothowto & RB_KDB) 330 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 331#endif 332 cpu_clock = cvmx_sysinfo_get()->cpu_clock_hz; 333 platform_counter_freq = cpu_clock; 334 octeon_timecounter.tc_frequency = cpu_clock; 335 platform_timecounter = &octeon_timecounter; 336 mips_timer_init_params(platform_counter_freq, 0); 337 set_cputicker(octeon_get_ticks, cpu_clock, 0); 338 339#ifdef SMP 340 /* 341 * Clear any pending IPIs. 342 */ 343 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff); 344#endif 345 346 printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING); 347 printf("Available Octeon features:"); 348 for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++) 349 if (octeon_has_feature(ofd->ofd_feature)) 350 printf(" %s", ofd->ofd_string); 351 printf("\n"); 352} 353 354static uint64_t 355octeon_get_ticks(void) 356{ 357 uint64_t cvmcount; 358 359 CVMX_MF_CYCLE(cvmcount); 360 return (cvmcount); 361} 362 363static unsigned 364octeon_get_timecount(struct timecounter *tc) 365{ 366 return ((unsigned)octeon_get_ticks()); 367} 368 369/** 370 * version of printf that works better in exception context. 371 * 372 * @param format 373 * 374 * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version. 375 */ 376void cvmx_safe_printf(const char *format, ...) 377{ 378 char buffer[256]; 379 char *ptr = buffer; 380 int count; 381 va_list args; 382 383 va_start(args, format); 384#ifndef __U_BOOT__ 385 count = vsnprintf(buffer, sizeof(buffer), format, args); 386#else 387 count = vsprintf(buffer, format, args); 388#endif 389 va_end(args); 390 391 while (count-- > 0) 392 { 393 cvmx_uart_lsr_t lsrval; 394 395 /* Spin until there is room */ 396 do 397 { 398 lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0)); 399#if !defined(CONFIG_OCTEON_SIM_SPEED) 400 if (lsrval.s.temt == 0) 401 cvmx_wait(10000); /* Just to reduce the load on the system */ 402#endif 403 } 404 while (lsrval.s.temt == 0); 405 406 if (*ptr == '\n') 407 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r'); 408 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++); 409 } 410} 411 412/* impSTART: This stuff should move back into the Cavium SDK */ 413/* 414 **************************************************************************************** 415 * 416 * APP/BOOT DESCRIPTOR STUFF 417 * 418 **************************************************************************************** 419 */ 420 421/* Define the struct that is initialized by the bootloader used by the 422 * startup code. 423 * 424 * Copyright (c) 2004, 2005, 2006 Cavium Networks. 425 * 426 * The authors hereby grant permission to use, copy, modify, distribute, 427 * and license this software and its documentation for any purpose, provided 428 * that existing copyright notices are retained in all copies and that this 429 * notice is included verbatim in any distributions. No written agreement, 430 * license, or royalty fee is required for any of the authorized uses. 431 * Modifications to this software may be copyrighted by their authors 432 * and need not follow the licensing terms described here, provided that 433 * the new terms are clearly indicated on the first page of each file where 434 * they apply. 435 */ 436 437#define OCTEON_CURRENT_DESC_VERSION 6 438#define OCTEON_ARGV_MAX_ARGS (64) 439#define OCTOEN_SERIAL_LEN 20 440 441typedef struct { 442 /* Start of block referenced by assembly code - do not change! */ 443 uint32_t desc_version; 444 uint32_t desc_size; 445 446 uint64_t stack_top; 447 uint64_t heap_base; 448 uint64_t heap_end; 449 uint64_t entry_point; /* Only used by bootloader */ 450 uint64_t desc_vaddr; 451 /* End of This block referenced by assembly code - do not change! */ 452 453 uint32_t exception_base_addr; 454 uint32_t stack_size; 455 uint32_t heap_size; 456 uint32_t argc; /* Argc count for application */ 457 uint32_t argv[OCTEON_ARGV_MAX_ARGS]; 458 uint32_t flags; 459 uint32_t core_mask; 460 uint32_t dram_size; /**< DRAM size in megabyes */ 461 uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/ 462 uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */ 463 uint32_t eclock_hz; /**< CPU clock speed, in hz */ 464 uint32_t dclock_hz; /**< DRAM clock speed, in hz */ 465 uint32_t spi_clock_hz; /**< SPI4 clock in hz */ 466 uint16_t board_type; 467 uint8_t board_rev_major; 468 uint8_t board_rev_minor; 469 uint16_t chip_type; 470 uint8_t chip_rev_major; 471 uint8_t chip_rev_minor; 472 char board_serial_number[OCTOEN_SERIAL_LEN]; 473 uint8_t mac_addr_base[6]; 474 uint8_t mac_addr_count; 475 uint64_t cvmx_desc_vaddr; 476} octeon_boot_descriptor_t; 477 478cvmx_bootinfo_t *octeon_bootinfo; 479 480static octeon_boot_descriptor_t *app_desc_ptr; 481 482int 483octeon_is_simulation(void) 484{ 485 switch (cvmx_sysinfo_get()->board_type) { 486 case CVMX_BOARD_TYPE_SIM: 487 return 1; 488 default: 489 return 0; 490 } 491} 492 493static void 494octeon_process_app_desc_ver_6(void) 495{ 496 /* XXX Why is 0x00000000ffffffffULL a bad value? */ 497 if (app_desc_ptr->cvmx_desc_vaddr == 0 || 498 app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful) 499 panic("Bad octeon_bootinfo %p", octeon_bootinfo); 500 501 octeon_bootinfo = 502 (cvmx_bootinfo_t *)(intptr_t)app_desc_ptr->cvmx_desc_vaddr; 503 octeon_bootinfo = 504 (cvmx_bootinfo_t *) ((intptr_t)octeon_bootinfo | MIPS_KSEG0_START); 505 if (octeon_bootinfo->major_version != 1) 506 panic("Incompatible CVMX descriptor from bootloader: %d.%d %p", 507 (int) octeon_bootinfo->major_version, 508 (int) octeon_bootinfo->minor_version, octeon_bootinfo); 509 510 cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr, 511 octeon_bootinfo->board_type, 512 octeon_bootinfo->board_rev_major, 513 octeon_bootinfo->board_rev_minor, 514 octeon_bootinfo->eclock_hz); 515 memcpy(cvmx_sysinfo_get()->mac_addr_base, octeon_bootinfo->mac_addr_base, 6); 516 cvmx_sysinfo_get()->mac_addr_count = octeon_bootinfo->mac_addr_count; 517 cvmx_sysinfo_get()->compact_flash_common_base_addr = 518 octeon_bootinfo->compact_flash_common_base_addr; 519 cvmx_sysinfo_get()->compact_flash_attribute_base_addr = 520 octeon_bootinfo->compact_flash_attribute_base_addr; 521 cvmx_sysinfo_get()->core_mask = octeon_bootinfo->core_mask; 522 cvmx_sysinfo_get()->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 523} 524 525static void 526octeon_boot_params_init(register_t ptr) 527{ 528 if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR) 529 panic("app descriptor passed at invalid address %#jx", 530 (uintmax_t)ptr); 531 532 app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr; 533 if (app_desc_ptr->desc_version < 6) 534 panic("Your boot code is too old to be supported."); 535 octeon_process_app_desc_ver_6(); 536 537 KASSERT(octeon_bootinfo != NULL, ("octeon_bootinfo should be set")); 538 539 if (cvmx_sysinfo_get()->led_display_base_addr != 0) { 540 /* 541 * Revision 1.x of the EBT3000 only supports 4 characters, but 542 * other devices support 8. 543 */ 544 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 && 545 cvmx_sysinfo_get()->board_rev_major == 1) 546 ebt3000_str_write("FBSD"); 547 else 548 ebt3000_str_write("FreeBSD!"); 549 } 550 551 if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0) 552 panic("Your boot loader did not supply a memory descriptor."); 553 cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr); 554 555 printf("Boot Descriptor Ver: %u -> %u/%u", 556 app_desc_ptr->desc_version, octeon_bootinfo->major_version, 557 octeon_bootinfo->minor_version); 558 printf(" CPU clock: %uMHz Core Mask: %#x\n", 559 cvmx_sysinfo_get()->cpu_clock_hz / 1000000, 560 cvmx_sysinfo_get()->core_mask); 561 printf(" Board Type: %u Revision: %u/%u\n", 562 cvmx_sysinfo_get()->board_type, 563 cvmx_sysinfo_get()->board_rev_major, 564 cvmx_sysinfo_get()->board_rev_minor); 565 566 printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n", 567 octeon_bootinfo->mac_addr_base[0], 568 octeon_bootinfo->mac_addr_base[1], 569 octeon_bootinfo->mac_addr_base[2], 570 octeon_bootinfo->mac_addr_base[3], 571 octeon_bootinfo->mac_addr_base[4], 572 octeon_bootinfo->mac_addr_base[5], 573 octeon_bootinfo->mac_addr_count); 574 575#if defined(OCTEON_BOARD_CAPK_0100ND) 576 strcpy(cpu_board, "CAPK-0100ND"); 577 if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) { 578 printf("Compiled for CAPK-0100ND, but board type is %s\n", 579 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 580 strcat(cpu_board, " hardwired, but type is "); 581 strcat(cpu_board, 582 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 583 } 584#else 585 strcpy(cpu_board, 586 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 587 printf("Board: %s\n", cpu_board); 588#endif 589 strcpy(cpu_model, octeon_model_get_string(cvmx_get_proc_id())); 590 printf("Model: %s\n", cpu_model); 591} 592/* impEND: This stuff should move back into the Cavium SDK */ 593