octeon_machdep.c revision 233417
1194140Simp/*- 2194140Simp * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org> 3194140Simp * All rights reserved. 4194140Simp * 5194140Simp * Redistribution and use in source and binary forms, with or without 6194140Simp * modification, are permitted provided that the following conditions 7194140Simp * are met: 8194140Simp * 1. Redistributions of source code must retain the above copyright 9194140Simp * notice, this list of conditions and the following disclaimer. 10194140Simp * 2. Redistributions in binary form must reproduce the above copyright 11194140Simp * notice, this list of conditions and the following disclaimer in the 12194140Simp * documentation and/or other materials provided with the distribution. 13194140Simp * 14194140Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15194140Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16194140Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17194140Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18194140Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19194140Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20194140Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21194140Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22194140Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23194140Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24194140Simp * SUCH DAMAGE. 25194140Simp * 26194140Simp * $FreeBSD: head/sys/mips/cavium/octeon_machdep.c 233417 2012-03-24 06:28:15Z gonzo $ 27194140Simp */ 28194140Simp#include <sys/cdefs.h> 29194140Simp__FBSDID("$FreeBSD: head/sys/mips/cavium/octeon_machdep.c 233417 2012-03-24 06:28:15Z gonzo $"); 30194140Simp 31194140Simp#include <sys/param.h> 32196262Simp#include <sys/conf.h> 33196262Simp#include <sys/kernel.h> 34194140Simp#include <sys/systm.h> 35196262Simp#include <sys/imgact.h> 36196262Simp#include <sys/bio.h> 37196262Simp#include <sys/buf.h> 38196262Simp#include <sys/bus.h> 39196262Simp#include <sys/cpu.h> 40196262Simp#include <sys/cons.h> 41196262Simp#include <sys/exec.h> 42196262Simp#include <sys/ucontext.h> 43196262Simp#include <sys/proc.h> 44196262Simp#include <sys/kdb.h> 45196262Simp#include <sys/ptrace.h> 46196262Simp#include <sys/reboot.h> 47196262Simp#include <sys/signalvar.h> 48196262Simp#include <sys/sysent.h> 49196262Simp#include <sys/sysproto.h> 50210311Sjmallett#include <sys/time.h> 51210311Sjmallett#include <sys/timetc.h> 52196262Simp#include <sys/user.h> 53196262Simp 54196262Simp#include <vm/vm.h> 55196262Simp#include <vm/vm_object.h> 56196262Simp#include <vm/vm_page.h> 57196262Simp#include <vm/vm_pager.h> 58196262Simp 59196262Simp#include <machine/atomic.h> 60196262Simp#include <machine/cache.h> 61196262Simp#include <machine/clock.h> 62196262Simp#include <machine/cpu.h> 63194140Simp#include <machine/cpuregs.h> 64194140Simp#include <machine/cpufunc.h> 65202063Simp#include <mips/cavium/octeon_pcmap_regs.h> 66196262Simp#include <machine/hwfunc.h> 67196262Simp#include <machine/intr_machdep.h> 68196262Simp#include <machine/locore.h> 69196262Simp#include <machine/md_var.h> 70194140Simp#include <machine/pcpu.h> 71196262Simp#include <machine/pte.h> 72196262Simp#include <machine/trap.h> 73196262Simp#include <machine/vmparam.h> 74194140Simp 75210311Sjmallett#include <contrib/octeon-sdk/cvmx.h> 76210311Sjmallett#include <contrib/octeon-sdk/cvmx-bootmem.h> 77210311Sjmallett#include <contrib/octeon-sdk/cvmx-interrupt.h> 78210311Sjmallett#include <contrib/octeon-sdk/cvmx-version.h> 79210311Sjmallett 80232812Sjmallett#include <mips/cavium/octeon_irq.h> 81232812Sjmallett 82194140Simp#if defined(__mips_n64) 83196262Simp#define MAX_APP_DESC_ADDR 0xffffffffafffffff 84194140Simp#else 85196262Simp#define MAX_APP_DESC_ADDR 0xafffffff 86194140Simp#endif 87194140Simp 88210311Sjmallett#define OCTEON_CLOCK_DEFAULT (500 * 1000 * 1000) 89210311Sjmallett 90210311Sjmallettstruct octeon_feature_description { 91210311Sjmallett octeon_feature_t ofd_feature; 92210311Sjmallett const char *ofd_string; 93210311Sjmallett}; 94210311Sjmallett 95196262Simpextern int *edata; 96196262Simpextern int *end; 97217518Simpextern char cpu_model[]; 98217518Simpextern char cpu_board[]; 99194140Simp 100210311Sjmallettstatic const struct octeon_feature_description octeon_feature_descriptions[] = { 101210311Sjmallett { OCTEON_FEATURE_SAAD, "SAAD" }, 102210311Sjmallett { OCTEON_FEATURE_ZIP, "ZIP" }, 103210311Sjmallett { OCTEON_FEATURE_CRYPTO, "CRYPTO" }, 104216069Sjmallett { OCTEON_FEATURE_DORM_CRYPTO, "DORM_CRYPTO" }, 105210311Sjmallett { OCTEON_FEATURE_PCIE, "PCIE" }, 106216069Sjmallett { OCTEON_FEATURE_SRIO, "SRIO" }, 107210311Sjmallett { OCTEON_FEATURE_KEY_MEMORY, "KEY_MEMORY" }, 108210311Sjmallett { OCTEON_FEATURE_LED_CONTROLLER, "LED_CONTROLLER" }, 109210311Sjmallett { OCTEON_FEATURE_TRA, "TRA" }, 110210311Sjmallett { OCTEON_FEATURE_MGMT_PORT, "MGMT_PORT" }, 111210311Sjmallett { OCTEON_FEATURE_RAID, "RAID" }, 112210311Sjmallett { OCTEON_FEATURE_USB, "USB" }, 113210311Sjmallett { OCTEON_FEATURE_NO_WPTR, "NO_WPTR" }, 114210311Sjmallett { OCTEON_FEATURE_DFA, "DFA" }, 115210311Sjmallett { OCTEON_FEATURE_MDIO_CLAUSE_45, "MDIO_CLAUSE_45" }, 116216069Sjmallett { OCTEON_FEATURE_NPEI, "NPEI" }, 117232812Sjmallett { OCTEON_FEATURE_ILK, "ILK" }, 118232812Sjmallett { OCTEON_FEATURE_HFA, "HFA" }, 119232812Sjmallett { OCTEON_FEATURE_DFM, "DFM" }, 120232812Sjmallett { OCTEON_FEATURE_CIU2, "CIU2" }, 121232812Sjmallett { OCTEON_FEATURE_DICI_MODE, "DICI_MODE" }, 122232812Sjmallett { OCTEON_FEATURE_BIT_EXTRACTOR, "BIT_EXTRACTOR" }, 123232812Sjmallett { OCTEON_FEATURE_NAND, "NAND" }, 124232812Sjmallett { OCTEON_FEATURE_MMC, "MMC" }, 125232812Sjmallett { OCTEON_FEATURE_PKND, "PKND" }, 126232812Sjmallett { OCTEON_FEATURE_CN68XX_WQE, "CN68XX_WQE" }, 127210311Sjmallett { 0, NULL } 128210311Sjmallett}; 129210311Sjmallett 130201530Simpuint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip); 131201530Simpvoid ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip); 132201530Simp 133210311Sjmallettstatic uint64_t octeon_get_ticks(void); 134210311Sjmallettstatic unsigned octeon_get_timecount(struct timecounter *tc); 135210311Sjmallett 136200344Simpstatic void octeon_boot_params_init(register_t ptr); 137200344Simp 138210311Sjmallettstatic struct timecounter octeon_timecounter = { 139210311Sjmallett octeon_get_timecount, /* get_timecount */ 140210311Sjmallett 0, /* no poll_pps */ 141210311Sjmallett 0xffffffffu, /* octeon_mask */ 142210311Sjmallett 0, /* frequency */ 143210311Sjmallett "Octeon", /* name */ 144210311Sjmallett 900, /* quality (adjusted in code) */ 145210311Sjmallett}; 146210311Sjmallett 147198669Srrsvoid 148198669Srrsplatform_cpu_init() 149198669Srrs{ 150198669Srrs /* Nothing special yet */ 151198669Srrs} 152196262Simp 153194140Simp/* 154194140Simp * Perform a board-level soft-reset. 155194140Simp */ 156196314Simpvoid 157196314Simpplatform_reset(void) 158194140Simp{ 159210311Sjmallett cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 160194140Simp} 161194140Simp 162201530Simpvoid 163201530Simpocteon_led_write_char(int char_position, char val) 164194140Simp{ 165201530Simp uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 166194140Simp 167210311Sjmallett if (octeon_is_simulation()) 168201530Simp return; 169194140Simp 170201530Simp char_position &= 0x7; /* only 8 chars */ 171201530Simp ptr += char_position; 172201530Simp oct_write8_x8(ptr, val); 173194140Simp} 174194140Simp 175201530Simpvoid 176201530Simpocteon_led_write_char0(char val) 177194140Simp{ 178201530Simp uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 179194140Simp 180210311Sjmallett if (octeon_is_simulation()) 181201530Simp return; 182201530Simp oct_write8_x8(ptr, val); 183194140Simp} 184194140Simp 185201530Simpvoid 186201530Simpocteon_led_write_hexchar(int char_position, char hexval) 187194140Simp{ 188201530Simp uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 189201530Simp char char1, char2; 190194140Simp 191210311Sjmallett if (octeon_is_simulation()) 192201530Simp return; 193194140Simp 194201530Simp char1 = (hexval >> 4) & 0x0f; char1 = (char1 < 10)?char1+'0':char1+'7'; 195201530Simp char2 = (hexval & 0x0f); char2 = (char2 < 10)?char2+'0':char2+'7'; 196201530Simp char_position &= 0x7; /* only 8 chars */ 197201530Simp if (char_position > 6) 198201530Simp char_position = 6; 199201530Simp ptr += char_position; 200201530Simp oct_write8_x8(ptr, char1); 201201530Simp ptr++; 202201530Simp oct_write8_x8(ptr, char2); 203194140Simp} 204194140Simp 205201530Simpvoid 206201530Simpocteon_led_write_string(const char *str) 207194140Simp{ 208201530Simp uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 209201530Simp int i; 210194140Simp 211210311Sjmallett if (octeon_is_simulation()) 212201530Simp return; 213194140Simp 214201530Simp for (i=0; i<8; i++, ptr++) { 215201530Simp if (str && *str) 216201530Simp oct_write8_x8(ptr, *str++); 217201530Simp else 218201530Simp oct_write8_x8(ptr, ' '); 219210311Sjmallett (void)cvmx_read_csr(CVMX_MIO_BOOT_BIST_STAT); 220201530Simp } 221194140Simp} 222194140Simp 223194140Simpstatic char progress[8] = { '-', '/', '|', '\\', '-', '/', '|', '\\'}; 224194140Simp 225201530Simpvoid 226201530Simpocteon_led_run_wheel(int *prog_count, int led_position) 227194140Simp{ 228210311Sjmallett if (octeon_is_simulation()) 229201530Simp return; 230201530Simp octeon_led_write_char(led_position, progress[*prog_count]); 231201530Simp *prog_count += 1; 232201530Simp *prog_count &= 0x7; 233194140Simp} 234194140Simp 235201530Simpvoid 236201530Simpocteon_led_write_hex(uint32_t wl) 237194140Simp{ 238201530Simp char nbuf[80]; 239194140Simp 240201530Simp sprintf(nbuf, "%X", wl); 241201530Simp octeon_led_write_string(nbuf); 242194140Simp} 243194140Simp 244194140Simp/* 245194140Simp * octeon_debug_symbol 246194140Simp * 247194140Simp * Does nothing. 248194140Simp * Used to mark the point for simulator to begin tracing 249194140Simp */ 250201530Simpvoid 251201530Simpocteon_debug_symbol(void) 252194140Simp{ 253194140Simp} 254194140Simp 255194140Simp/* 256194140Simp * octeon_ciu_reset 257194140Simp * 258194140Simp * Shutdown all CIU to IP2, IP3 mappings 259194140Simp */ 260201530Simpvoid 261201530Simpocteon_ciu_reset(void) 262194140Simp{ 263233417Sgonzo uint64_t cvmctl; 264233417Sgonzo 265210311Sjmallett /* Disable all CIU interrupts by default */ 266210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0); 267210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0); 268210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0); 269210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0); 270194140Simp 271210311Sjmallett#ifdef SMP 272210311Sjmallett /* Enable the MBOX interrupts. */ 273210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 274232812Sjmallett (1ull << (OCTEON_IRQ_MBOX0 - 8)) | 275232812Sjmallett (1ull << (OCTEON_IRQ_MBOX1 - 8))); 276210311Sjmallett#endif 277233417Sgonzo 278233417Sgonzo /* 279233417Sgonzo * Move the Performance Counter interrupt to OCTEON_PMC_IRQ 280233417Sgonzo */ 281233417Sgonzo cvmctl = mips_rd_cvmctl(); 282233417Sgonzo cvmctl &= ~(7 << 7); 283233417Sgonzo cvmctl |= (OCTEON_PMC_IRQ + 2) << 7; 284233417Sgonzo mips_wr_cvmctl(cvmctl); 285194140Simp} 286194140Simp 287210311Sjmallettstatic void 288210311Sjmallettocteon_memory_init(void) 289194140Simp{ 290210311Sjmallett vm_paddr_t phys_end; 291210311Sjmallett int64_t addr; 292216318Sgonzo unsigned i, j; 293194140Simp 294210311Sjmallett phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end)); 295194140Simp 296210311Sjmallett if (octeon_is_simulation()) { 297210311Sjmallett /* Simulator we limit to 96 meg */ 298210311Sjmallett phys_avail[0] = phys_end; 299210311Sjmallett phys_avail[1] = 96 << 20; 300194140Simp 301216318Sgonzo dump_avail[0] = phys_avail[0]; 302216320Sgonzo dump_avail[1] = phys_avail[1]; 303216318Sgonzo 304210311Sjmallett realmem = physmem = btoc(phys_avail[1] - phys_avail[0]); 305210311Sjmallett return; 306201530Simp } 307194140Simp 308210311Sjmallett /* 309210311Sjmallett * Allocate memory from bootmem 1MB at a time and merge 310210311Sjmallett * adjacent entries. 311210311Sjmallett */ 312210311Sjmallett i = 0; 313210311Sjmallett while (i < PHYS_AVAIL_ENTRIES) { 314216773Sjmallett /* 315216773Sjmallett * If there is less than 2MB of memory available in 128-byte 316216773Sjmallett * blocks, do not steal any more memory. We need to leave some 317216773Sjmallett * memory for the command queues to be allocated out of. 318216773Sjmallett */ 319216773Sjmallett if (cvmx_bootmem_available_mem(128) < 2 << 20) 320216773Sjmallett break; 321216773Sjmallett 322210311Sjmallett addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end, 323210311Sjmallett ~(vm_paddr_t)0, PAGE_SIZE, 0); 324210311Sjmallett if (addr == -1) 325210311Sjmallett break; 326194140Simp 327212842Sjmallett /* 328212842Sjmallett * The SDK needs to be able to easily map any memory that might 329212842Sjmallett * come to it e.g. in the form of an mbuf. Because on !n64 we 330212842Sjmallett * can't direct-map some addresses and we don't want to manage 331212842Sjmallett * temporary mappings within the SDK, don't feed memory that 332212842Sjmallett * can't be direct-mapped to the kernel. 333212842Sjmallett */ 334212842Sjmallett#if !defined(__mips_n64) 335212842Sjmallett if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1)) 336212842Sjmallett continue; 337212842Sjmallett#endif 338212842Sjmallett 339210311Sjmallett physmem += btoc(1 << 20); 340194140Simp 341210311Sjmallett if (i > 0 && phys_avail[i - 1] == addr) { 342210311Sjmallett phys_avail[i - 1] += 1 << 20; 343210311Sjmallett continue; 344210311Sjmallett } 345194140Simp 346210311Sjmallett phys_avail[i + 0] = addr; 347210311Sjmallett phys_avail[i + 1] = addr + (1 << 20); 348194140Simp 349210311Sjmallett i += 2; 350201530Simp } 351194140Simp 352216320Sgonzo for (j = 0; j < i; j++) 353216318Sgonzo dump_avail[j] = phys_avail[j]; 354216318Sgonzo 355202831Simp realmem = physmem; 356202831Simp} 357202831Simp 358196262Simpvoid 359201530Simpplatform_start(__register_t a0, __register_t a1, __register_t a2 __unused, 360201530Simp __register_t a3) 361196262Simp{ 362210311Sjmallett const struct octeon_feature_description *ofd; 363196262Simp uint64_t platform_counter_freq; 364194140Simp 365210311Sjmallett /* 366210311Sjmallett * XXX 367210311Sjmallett * octeon_boot_params_init() should be called before anything else, 368210311Sjmallett * certainly before any output; we may find out from the boot 369210311Sjmallett * descriptor's flags that we're supposed to use the PCI or UART1 370210311Sjmallett * consoles rather than UART0. No point doing that reorganization 371210311Sjmallett * until we actually intercept UART_DEV_CONSOLE for the UART1 case 372210311Sjmallett * and somehow handle the PCI console, which we lack code for 373210311Sjmallett * entirely. 374210311Sjmallett */ 375210311Sjmallett 376233331Sgonzo mips_postboot_fixup(); 377233331Sgonzo 378201845Simp /* Initialize pcpu stuff */ 379201881Simp mips_pcpu0_init(); 380202831Simp mips_timer_early_init(OCTEON_CLOCK_DEFAULT); 381202831Simp cninit(); 382201845Simp 383202831Simp octeon_ciu_reset(); 384200344Simp octeon_boot_params_init(a3); 385210311Sjmallett /* 386210311Sjmallett * XXX 387210311Sjmallett * We can certainly parse command line arguments or U-Boot environment 388210311Sjmallett * to determine whether to bootverbose / single user / ... I think 389210311Sjmallett * stass has patches to add support for loader things to U-Boot even. 390210311Sjmallett */ 391196262Simp bootverbose = 1; 392194140Simp 393202831Simp /* 394202831Simp * For some reason on the cn38xx simulator ebase register is set to 395202831Simp * 0x80001000 at bootup time. Move it back to the default, but 396202831Simp * when we move to having support for multiple executives, we need 397202831Simp * to rethink this. 398202831Simp */ 399202831Simp mips_wr_ebase(0x80000000); 400196262Simp 401202831Simp octeon_memory_init(); 402196262Simp init_param1(); 403196262Simp init_param2(physmem); 404196262Simp mips_cpu_init(); 405202831Simp pmap_bootstrap(); 406202831Simp mips_proc0_init(); 407196262Simp mutex_init(); 408196262Simp kdb_init(); 409202850Simp#ifdef KDB 410202850Simp if (boothowto & RB_KDB) 411202850Simp kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 412196262Simp#endif 413217518Simp cpu_clock = cvmx_sysinfo_get()->cpu_clock_hz; 414217518Simp platform_counter_freq = cpu_clock; 415217518Simp octeon_timecounter.tc_frequency = cpu_clock; 416210311Sjmallett platform_timecounter = &octeon_timecounter; 417206721Sjmallett mips_timer_init_params(platform_counter_freq, 0); 418217518Simp set_cputicker(octeon_get_ticks, cpu_clock, 0); 419206721Sjmallett 420206721Sjmallett#ifdef SMP 421206721Sjmallett /* 422210311Sjmallett * Clear any pending IPIs. 423206721Sjmallett */ 424210311Sjmallett cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff); 425206721Sjmallett#endif 426210311Sjmallett 427210311Sjmallett printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING); 428210311Sjmallett printf("Available Octeon features:"); 429210311Sjmallett for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++) 430210311Sjmallett if (octeon_has_feature(ofd->ofd_feature)) 431210311Sjmallett printf(" %s", ofd->ofd_string); 432210311Sjmallett printf("\n"); 433196262Simp} 434196262Simp 435210311Sjmallettstatic uint64_t 436210311Sjmallettocteon_get_ticks(void) 437210311Sjmallett{ 438210311Sjmallett uint64_t cvmcount; 439210311Sjmallett 440210311Sjmallett CVMX_MF_CYCLE(cvmcount); 441210311Sjmallett return (cvmcount); 442210311Sjmallett} 443210311Sjmallett 444210311Sjmallettstatic unsigned 445210311Sjmallettocteon_get_timecount(struct timecounter *tc) 446210311Sjmallett{ 447210311Sjmallett return ((unsigned)octeon_get_ticks()); 448210311Sjmallett} 449210311Sjmallett 450215990Sjmallett/** 451215990Sjmallett * version of printf that works better in exception context. 452215990Sjmallett * 453215990Sjmallett * @param format 454215990Sjmallett * 455215990Sjmallett * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version. 456215990Sjmallett */ 457215990Sjmallettvoid cvmx_safe_printf(const char *format, ...) 458215990Sjmallett{ 459215990Sjmallett char buffer[256]; 460215990Sjmallett char *ptr = buffer; 461215990Sjmallett int count; 462215990Sjmallett va_list args; 463215990Sjmallett 464215990Sjmallett va_start(args, format); 465215990Sjmallett#ifndef __U_BOOT__ 466215990Sjmallett count = vsnprintf(buffer, sizeof(buffer), format, args); 467215990Sjmallett#else 468215990Sjmallett count = vsprintf(buffer, format, args); 469215990Sjmallett#endif 470215990Sjmallett va_end(args); 471215990Sjmallett 472215990Sjmallett while (count-- > 0) 473215990Sjmallett { 474215990Sjmallett cvmx_uart_lsr_t lsrval; 475215990Sjmallett 476215990Sjmallett /* Spin until there is room */ 477215990Sjmallett do 478215990Sjmallett { 479215990Sjmallett lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0)); 480215990Sjmallett#if !defined(CONFIG_OCTEON_SIM_SPEED) 481215990Sjmallett if (lsrval.s.temt == 0) 482215990Sjmallett cvmx_wait(10000); /* Just to reduce the load on the system */ 483215990Sjmallett#endif 484215990Sjmallett } 485215990Sjmallett while (lsrval.s.temt == 0); 486215990Sjmallett 487215990Sjmallett if (*ptr == '\n') 488215990Sjmallett cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r'); 489215990Sjmallett cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++); 490215990Sjmallett } 491215990Sjmallett} 492215990Sjmallett 493202831Simp/* impSTART: This stuff should move back into the Cavium SDK */ 494194140Simp/* 495194140Simp **************************************************************************************** 496194140Simp * 497194140Simp * APP/BOOT DESCRIPTOR STUFF 498194140Simp * 499194140Simp **************************************************************************************** 500194140Simp */ 501194140Simp 502194140Simp/* Define the struct that is initialized by the bootloader used by the 503194140Simp * startup code. 504194140Simp * 505194140Simp * Copyright (c) 2004, 2005, 2006 Cavium Networks. 506194140Simp * 507194140Simp * The authors hereby grant permission to use, copy, modify, distribute, 508194140Simp * and license this software and its documentation for any purpose, provided 509194140Simp * that existing copyright notices are retained in all copies and that this 510194140Simp * notice is included verbatim in any distributions. No written agreement, 511194140Simp * license, or royalty fee is required for any of the authorized uses. 512194140Simp * Modifications to this software may be copyrighted by their authors 513194140Simp * and need not follow the licensing terms described here, provided that 514194140Simp * the new terms are clearly indicated on the first page of each file where 515194140Simp * they apply. 516194140Simp */ 517194140Simp 518194140Simp#define OCTEON_CURRENT_DESC_VERSION 6 519194140Simp#define OCTEON_ARGV_MAX_ARGS (64) 520194140Simp#define OCTOEN_SERIAL_LEN 20 521194140Simp 522194140Simptypedef struct { 523200344Simp /* Start of block referenced by assembly code - do not change! */ 524200344Simp uint32_t desc_version; 525200344Simp uint32_t desc_size; 526194140Simp 527200344Simp uint64_t stack_top; 528200344Simp uint64_t heap_base; 529200344Simp uint64_t heap_end; 530200344Simp uint64_t entry_point; /* Only used by bootloader */ 531200344Simp uint64_t desc_vaddr; 532200344Simp /* End of This block referenced by assembly code - do not change! */ 533194140Simp 534200344Simp uint32_t exception_base_addr; 535200344Simp uint32_t stack_size; 536200344Simp uint32_t heap_size; 537200344Simp uint32_t argc; /* Argc count for application */ 538200344Simp uint32_t argv[OCTEON_ARGV_MAX_ARGS]; 539200344Simp uint32_t flags; 540200344Simp uint32_t core_mask; 541200344Simp uint32_t dram_size; /**< DRAM size in megabyes */ 542200344Simp uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/ 543200344Simp uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */ 544200344Simp uint32_t eclock_hz; /**< CPU clock speed, in hz */ 545200344Simp uint32_t dclock_hz; /**< DRAM clock speed, in hz */ 546200344Simp uint32_t spi_clock_hz; /**< SPI4 clock in hz */ 547200344Simp uint16_t board_type; 548200344Simp uint8_t board_rev_major; 549200344Simp uint8_t board_rev_minor; 550200344Simp uint16_t chip_type; 551200344Simp uint8_t chip_rev_major; 552200344Simp uint8_t chip_rev_minor; 553200344Simp char board_serial_number[OCTOEN_SERIAL_LEN]; 554200344Simp uint8_t mac_addr_base[6]; 555200344Simp uint8_t mac_addr_count; 556200344Simp uint64_t cvmx_desc_vaddr; 557194140Simp} octeon_boot_descriptor_t; 558194140Simp 559210311Sjmallettcvmx_bootinfo_t *octeon_bootinfo; 560194140Simp 561194140Simpstatic octeon_boot_descriptor_t *app_desc_ptr; 562194140Simp 563200344Simpint 564210311Sjmallettocteon_is_simulation(void) 565194140Simp{ 566210311Sjmallett switch (cvmx_sysinfo_get()->board_type) { 567210311Sjmallett case CVMX_BOARD_TYPE_SIM: 568204777Sjmallett return 1; 569204777Sjmallett default: 570210311Sjmallett return 0; 571204777Sjmallett } 572194140Simp} 573194140Simp 574200344Simpstatic void 575210311Sjmallettocteon_process_app_desc_ver_6(void) 576194140Simp{ 577200344Simp /* XXX Why is 0x00000000ffffffffULL a bad value? */ 578200344Simp if (app_desc_ptr->cvmx_desc_vaddr == 0 || 579210311Sjmallett app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful) 580210311Sjmallett panic("Bad octeon_bootinfo %p", octeon_bootinfo); 581210311Sjmallett 582210311Sjmallett octeon_bootinfo = 583200344Simp (cvmx_bootinfo_t *)(intptr_t)app_desc_ptr->cvmx_desc_vaddr; 584210311Sjmallett octeon_bootinfo = 585210311Sjmallett (cvmx_bootinfo_t *) ((intptr_t)octeon_bootinfo | MIPS_KSEG0_START); 586210311Sjmallett if (octeon_bootinfo->major_version != 1) 587210311Sjmallett panic("Incompatible CVMX descriptor from bootloader: %d.%d %p", 588210311Sjmallett (int) octeon_bootinfo->major_version, 589210311Sjmallett (int) octeon_bootinfo->minor_version, octeon_bootinfo); 590194140Simp 591215990Sjmallett cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr, 592210311Sjmallett octeon_bootinfo->board_type, 593210311Sjmallett octeon_bootinfo->board_rev_major, 594210311Sjmallett octeon_bootinfo->board_rev_minor, 595210311Sjmallett octeon_bootinfo->eclock_hz); 596228088Sgonzo memcpy(cvmx_sysinfo_get()->mac_addr_base, octeon_bootinfo->mac_addr_base, 6); 597228088Sgonzo cvmx_sysinfo_get()->mac_addr_count = octeon_bootinfo->mac_addr_count; 598228853Sgonzo cvmx_sysinfo_get()->compact_flash_common_base_addr = 599228853Sgonzo octeon_bootinfo->compact_flash_common_base_addr; 600228872Sgonzo cvmx_sysinfo_get()->compact_flash_attribute_base_addr = 601228872Sgonzo octeon_bootinfo->compact_flash_attribute_base_addr; 602232402Sjmallett cvmx_sysinfo_get()->core_mask = octeon_bootinfo->core_mask; 603194140Simp} 604194140Simp 605200344Simpstatic void 606200344Simpocteon_boot_params_init(register_t ptr) 607194140Simp{ 608210311Sjmallett if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR) 609210311Sjmallett panic("app descriptor passed at invalid address %#jx", 610210311Sjmallett (uintmax_t)ptr); 611194140Simp 612210311Sjmallett app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr; 613210311Sjmallett if (app_desc_ptr->desc_version < 6) 614210311Sjmallett panic("Your boot code is too old to be supported."); 615210311Sjmallett octeon_process_app_desc_ver_6(); 616210311Sjmallett 617210311Sjmallett KASSERT(octeon_bootinfo != NULL, ("octeon_bootinfo should be set")); 618210311Sjmallett 619215990Sjmallett if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0) 620210311Sjmallett panic("Your boot loader did not supply a memory descriptor."); 621215990Sjmallett cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr); 622210311Sjmallett 623194140Simp printf("Boot Descriptor Ver: %u -> %u/%u", 624210311Sjmallett app_desc_ptr->desc_version, octeon_bootinfo->major_version, 625210311Sjmallett octeon_bootinfo->minor_version); 626210311Sjmallett printf(" CPU clock: %uMHz Core Mask: %#x\n", 627210311Sjmallett cvmx_sysinfo_get()->cpu_clock_hz / 1000000, 628210311Sjmallett cvmx_sysinfo_get()->core_mask); 629194140Simp printf(" Board Type: %u Revision: %u/%u\n", 630210311Sjmallett cvmx_sysinfo_get()->board_type, 631210311Sjmallett cvmx_sysinfo_get()->board_rev_major, 632210311Sjmallett cvmx_sysinfo_get()->board_rev_minor); 633194140Simp 634202831Simp printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n", 635210311Sjmallett octeon_bootinfo->mac_addr_base[0], 636210311Sjmallett octeon_bootinfo->mac_addr_base[1], 637210311Sjmallett octeon_bootinfo->mac_addr_base[2], 638210311Sjmallett octeon_bootinfo->mac_addr_base[3], 639210311Sjmallett octeon_bootinfo->mac_addr_base[4], 640210311Sjmallett octeon_bootinfo->mac_addr_base[5], 641210311Sjmallett octeon_bootinfo->mac_addr_count); 642210311Sjmallett 643210311Sjmallett#if defined(OCTEON_BOARD_CAPK_0100ND) 644217518Simp strcpy(cpu_board, "CAPK-0100ND"); 645217518Simp if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) { 646210311Sjmallett printf("Compiled for CAPK-0100ND, but board type is %s\n", 647210311Sjmallett cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 648217518Simp strcat(cpu_board, " hardwired, but type is "); 649217518Simp strcat(cpu_board, 650217518Simp cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 651217518Simp } 652210311Sjmallett#else 653217518Simp strcpy(cpu_board, 654210311Sjmallett cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 655217518Simp printf("Board: %s\n", cpu_board); 656210311Sjmallett#endif 657217518Simp strcpy(cpu_model, octeon_model_get_string(cvmx_get_proc_id())); 658217518Simp printf("Model: %s\n", cpu_model); 659194140Simp} 660202831Simp/* impEND: This stuff should move back into the Cavium SDK */ 661