octeon_machdep.c revision 216320
1194140Simp/*- 2194140Simp * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org> 3194140Simp * All rights reserved. 4194140Simp * 5194140Simp * Redistribution and use in source and binary forms, with or without 6194140Simp * modification, are permitted provided that the following conditions 7194140Simp * are met: 8194140Simp * 1. Redistributions of source code must retain the above copyright 9194140Simp * notice, this list of conditions and the following disclaimer. 10194140Simp * 2. Redistributions in binary form must reproduce the above copyright 11194140Simp * notice, this list of conditions and the following disclaimer in the 12194140Simp * documentation and/or other materials provided with the distribution. 13194140Simp * 14194140Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15194140Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16194140Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17194140Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18194140Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19194140Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20194140Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21194140Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22194140Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23194140Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24194140Simp * SUCH DAMAGE. 25194140Simp * 26194140Simp * $FreeBSD: head/sys/mips/cavium/octeon_machdep.c 216320 2010-12-09 07:47:40Z gonzo $ 27194140Simp */ 28194140Simp#include <sys/cdefs.h> 29194140Simp__FBSDID("$FreeBSD: head/sys/mips/cavium/octeon_machdep.c 216320 2010-12-09 07:47:40Z gonzo $"); 30194140Simp 31194140Simp#include <sys/param.h> 32196262Simp#include <sys/conf.h> 33196262Simp#include <sys/kernel.h> 34194140Simp#include <sys/systm.h> 35196262Simp#include <sys/imgact.h> 36196262Simp#include <sys/bio.h> 37196262Simp#include <sys/buf.h> 38196262Simp#include <sys/bus.h> 39196262Simp#include <sys/cpu.h> 40196262Simp#include <sys/cons.h> 41196262Simp#include <sys/exec.h> 42196262Simp#include <sys/ucontext.h> 43196262Simp#include <sys/proc.h> 44196262Simp#include <sys/kdb.h> 45196262Simp#include <sys/ptrace.h> 46196262Simp#include <sys/reboot.h> 47196262Simp#include <sys/signalvar.h> 48196262Simp#include <sys/sysent.h> 49196262Simp#include <sys/sysproto.h> 50210311Sjmallett#include <sys/time.h> 51210311Sjmallett#include <sys/timetc.h> 52196262Simp#include <sys/user.h> 53196262Simp 54196262Simp#include <vm/vm.h> 55196262Simp#include <vm/vm_object.h> 56196262Simp#include <vm/vm_page.h> 57196262Simp#include <vm/vm_pager.h> 58196262Simp 59196262Simp#include <machine/atomic.h> 60196262Simp#include <machine/cache.h> 61196262Simp#include <machine/clock.h> 62196262Simp#include <machine/cpu.h> 63194140Simp#include <machine/cpuregs.h> 64194140Simp#include <machine/cpufunc.h> 65202063Simp#include <mips/cavium/octeon_pcmap_regs.h> 66196262Simp#include <machine/hwfunc.h> 67196262Simp#include <machine/intr_machdep.h> 68196262Simp#include <machine/locore.h> 69196262Simp#include <machine/md_var.h> 70194140Simp#include <machine/pcpu.h> 71196262Simp#include <machine/pte.h> 72196262Simp#include <machine/trap.h> 73196262Simp#include <machine/vmparam.h> 74194140Simp 75210311Sjmallett#include <contrib/octeon-sdk/cvmx.h> 76210311Sjmallett#include <contrib/octeon-sdk/cvmx-bootmem.h> 77210311Sjmallett#include <contrib/octeon-sdk/cvmx-interrupt.h> 78210311Sjmallett#include <contrib/octeon-sdk/cvmx-version.h> 79210311Sjmallett 80194140Simp#if defined(__mips_n64) 81196262Simp#define MAX_APP_DESC_ADDR 0xffffffffafffffff 82194140Simp#else 83196262Simp#define MAX_APP_DESC_ADDR 0xafffffff 84194140Simp#endif 85194140Simp 86210311Sjmallett#define OCTEON_CLOCK_DEFAULT (500 * 1000 * 1000) 87210311Sjmallett 88210311Sjmallettstruct octeon_feature_description { 89210311Sjmallett octeon_feature_t ofd_feature; 90210311Sjmallett const char *ofd_string; 91210311Sjmallett}; 92210311Sjmallett 93196262Simpextern int *edata; 94196262Simpextern int *end; 95194140Simp 96210311Sjmallettstatic const struct octeon_feature_description octeon_feature_descriptions[] = { 97210311Sjmallett { OCTEON_FEATURE_SAAD, "SAAD" }, 98210311Sjmallett { OCTEON_FEATURE_ZIP, "ZIP" }, 99210311Sjmallett { OCTEON_FEATURE_CRYPTO, "CRYPTO" }, 100216069Sjmallett { OCTEON_FEATURE_DORM_CRYPTO, "DORM_CRYPTO" }, 101210311Sjmallett { OCTEON_FEATURE_PCIE, "PCIE" }, 102216069Sjmallett { OCTEON_FEATURE_SRIO, "SRIO" }, 103210311Sjmallett { OCTEON_FEATURE_KEY_MEMORY, "KEY_MEMORY" }, 104210311Sjmallett { OCTEON_FEATURE_LED_CONTROLLER, "LED_CONTROLLER" }, 105210311Sjmallett { OCTEON_FEATURE_TRA, "TRA" }, 106210311Sjmallett { OCTEON_FEATURE_MGMT_PORT, "MGMT_PORT" }, 107210311Sjmallett { OCTEON_FEATURE_RAID, "RAID" }, 108210311Sjmallett { OCTEON_FEATURE_USB, "USB" }, 109210311Sjmallett { OCTEON_FEATURE_NO_WPTR, "NO_WPTR" }, 110210311Sjmallett { OCTEON_FEATURE_DFA, "DFA" }, 111210311Sjmallett { OCTEON_FEATURE_MDIO_CLAUSE_45, "MDIO_CLAUSE_45" }, 112216069Sjmallett { OCTEON_FEATURE_NPEI, "NPEI" }, 113210311Sjmallett { 0, NULL } 114210311Sjmallett}; 115210311Sjmallett 116201530Simpuint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip); 117201530Simpvoid ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip); 118201530Simp 119210311Sjmallettstatic uint64_t octeon_get_ticks(void); 120210311Sjmallettstatic unsigned octeon_get_timecount(struct timecounter *tc); 121210311Sjmallett 122200344Simpstatic void octeon_boot_params_init(register_t ptr); 123200344Simp 124210311Sjmallettstatic struct timecounter octeon_timecounter = { 125210311Sjmallett octeon_get_timecount, /* get_timecount */ 126210311Sjmallett 0, /* no poll_pps */ 127210311Sjmallett 0xffffffffu, /* octeon_mask */ 128210311Sjmallett 0, /* frequency */ 129210311Sjmallett "Octeon", /* name */ 130210311Sjmallett 900, /* quality (adjusted in code) */ 131210311Sjmallett}; 132210311Sjmallett 133198669Srrsvoid 134198669Srrsplatform_cpu_init() 135198669Srrs{ 136198669Srrs /* Nothing special yet */ 137198669Srrs} 138196262Simp 139194140Simp/* 140194140Simp * Perform a board-level soft-reset. 141194140Simp */ 142196314Simpvoid 143196314Simpplatform_reset(void) 144194140Simp{ 145210311Sjmallett cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 146194140Simp} 147194140Simp 148201530Simpvoid 149201530Simpocteon_led_write_char(int char_position, char val) 150194140Simp{ 151201530Simp uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 152194140Simp 153210311Sjmallett if (octeon_is_simulation()) 154201530Simp return; 155194140Simp 156201530Simp char_position &= 0x7; /* only 8 chars */ 157201530Simp ptr += char_position; 158201530Simp oct_write8_x8(ptr, val); 159194140Simp} 160194140Simp 161201530Simpvoid 162201530Simpocteon_led_write_char0(char val) 163194140Simp{ 164201530Simp uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 165194140Simp 166210311Sjmallett if (octeon_is_simulation()) 167201530Simp return; 168201530Simp oct_write8_x8(ptr, val); 169194140Simp} 170194140Simp 171201530Simpvoid 172201530Simpocteon_led_write_hexchar(int char_position, char hexval) 173194140Simp{ 174201530Simp uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 175201530Simp char char1, char2; 176194140Simp 177210311Sjmallett if (octeon_is_simulation()) 178201530Simp return; 179194140Simp 180201530Simp char1 = (hexval >> 4) & 0x0f; char1 = (char1 < 10)?char1+'0':char1+'7'; 181201530Simp char2 = (hexval & 0x0f); char2 = (char2 < 10)?char2+'0':char2+'7'; 182201530Simp char_position &= 0x7; /* only 8 chars */ 183201530Simp if (char_position > 6) 184201530Simp char_position = 6; 185201530Simp ptr += char_position; 186201530Simp oct_write8_x8(ptr, char1); 187201530Simp ptr++; 188201530Simp oct_write8_x8(ptr, char2); 189194140Simp} 190194140Simp 191201530Simpvoid 192201530Simpocteon_led_write_string(const char *str) 193194140Simp{ 194201530Simp uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 195201530Simp int i; 196194140Simp 197210311Sjmallett if (octeon_is_simulation()) 198201530Simp return; 199194140Simp 200201530Simp for (i=0; i<8; i++, ptr++) { 201201530Simp if (str && *str) 202201530Simp oct_write8_x8(ptr, *str++); 203201530Simp else 204201530Simp oct_write8_x8(ptr, ' '); 205210311Sjmallett (void)cvmx_read_csr(CVMX_MIO_BOOT_BIST_STAT); 206201530Simp } 207194140Simp} 208194140Simp 209194140Simpstatic char progress[8] = { '-', '/', '|', '\\', '-', '/', '|', '\\'}; 210194140Simp 211201530Simpvoid 212201530Simpocteon_led_run_wheel(int *prog_count, int led_position) 213194140Simp{ 214210311Sjmallett if (octeon_is_simulation()) 215201530Simp return; 216201530Simp octeon_led_write_char(led_position, progress[*prog_count]); 217201530Simp *prog_count += 1; 218201530Simp *prog_count &= 0x7; 219194140Simp} 220194140Simp 221201530Simpvoid 222201530Simpocteon_led_write_hex(uint32_t wl) 223194140Simp{ 224201530Simp char nbuf[80]; 225194140Simp 226201530Simp sprintf(nbuf, "%X", wl); 227201530Simp octeon_led_write_string(nbuf); 228194140Simp} 229194140Simp 230194140Simp/* 231194140Simp * octeon_debug_symbol 232194140Simp * 233194140Simp * Does nothing. 234194140Simp * Used to mark the point for simulator to begin tracing 235194140Simp */ 236201530Simpvoid 237201530Simpocteon_debug_symbol(void) 238194140Simp{ 239194140Simp} 240194140Simp 241194140Simp/* 242194140Simp * octeon_ciu_reset 243194140Simp * 244194140Simp * Shutdown all CIU to IP2, IP3 mappings 245194140Simp */ 246201530Simpvoid 247201530Simpocteon_ciu_reset(void) 248194140Simp{ 249210311Sjmallett /* Disable all CIU interrupts by default */ 250210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0); 251210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0); 252210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0); 253210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0); 254194140Simp 255210311Sjmallett#ifdef SMP 256210311Sjmallett /* Enable the MBOX interrupts. */ 257210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 258210311Sjmallett (1ull << (CVMX_IRQ_MBOX0 - 8)) | 259210311Sjmallett (1ull << (CVMX_IRQ_MBOX1 - 8))); 260210311Sjmallett#endif 261194140Simp} 262194140Simp 263210311Sjmallettstatic void 264210311Sjmallettocteon_memory_init(void) 265194140Simp{ 266210311Sjmallett vm_paddr_t phys_end; 267210311Sjmallett int64_t addr; 268216318Sgonzo unsigned i, j; 269194140Simp 270210311Sjmallett phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end)); 271194140Simp 272210311Sjmallett if (octeon_is_simulation()) { 273210311Sjmallett /* Simulator we limit to 96 meg */ 274210311Sjmallett phys_avail[0] = phys_end; 275210311Sjmallett phys_avail[1] = 96 << 20; 276194140Simp 277216318Sgonzo dump_avail[0] = phys_avail[0]; 278216320Sgonzo dump_avail[1] = phys_avail[1]; 279216318Sgonzo 280210311Sjmallett realmem = physmem = btoc(phys_avail[1] - phys_avail[0]); 281210311Sjmallett return; 282201530Simp } 283194140Simp 284210311Sjmallett /* 285210311Sjmallett * Allocate memory from bootmem 1MB at a time and merge 286210311Sjmallett * adjacent entries. 287210311Sjmallett */ 288210311Sjmallett i = 0; 289210311Sjmallett while (i < PHYS_AVAIL_ENTRIES) { 290210311Sjmallett addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end, 291210311Sjmallett ~(vm_paddr_t)0, PAGE_SIZE, 0); 292210311Sjmallett if (addr == -1) 293210311Sjmallett break; 294194140Simp 295212842Sjmallett /* 296212842Sjmallett * The SDK needs to be able to easily map any memory that might 297212842Sjmallett * come to it e.g. in the form of an mbuf. Because on !n64 we 298212842Sjmallett * can't direct-map some addresses and we don't want to manage 299212842Sjmallett * temporary mappings within the SDK, don't feed memory that 300212842Sjmallett * can't be direct-mapped to the kernel. 301212842Sjmallett */ 302212842Sjmallett#if !defined(__mips_n64) 303212842Sjmallett if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1)) 304212842Sjmallett continue; 305212842Sjmallett#endif 306212842Sjmallett 307210311Sjmallett physmem += btoc(1 << 20); 308194140Simp 309210311Sjmallett if (i > 0 && phys_avail[i - 1] == addr) { 310210311Sjmallett phys_avail[i - 1] += 1 << 20; 311210311Sjmallett continue; 312210311Sjmallett } 313194140Simp 314210311Sjmallett phys_avail[i + 0] = addr; 315210311Sjmallett phys_avail[i + 1] = addr + (1 << 20); 316194140Simp 317210311Sjmallett i += 2; 318201530Simp } 319194140Simp 320216320Sgonzo for (j = 0; j < i; j++) 321216318Sgonzo dump_avail[j] = phys_avail[j]; 322216318Sgonzo 323202831Simp realmem = physmem; 324202831Simp} 325202831Simp 326196262Simpvoid 327201530Simpplatform_start(__register_t a0, __register_t a1, __register_t a2 __unused, 328201530Simp __register_t a3) 329196262Simp{ 330210311Sjmallett const struct octeon_feature_description *ofd; 331196262Simp uint64_t platform_counter_freq; 332194140Simp 333210311Sjmallett /* 334210311Sjmallett * XXX 335210311Sjmallett * octeon_boot_params_init() should be called before anything else, 336210311Sjmallett * certainly before any output; we may find out from the boot 337210311Sjmallett * descriptor's flags that we're supposed to use the PCI or UART1 338210311Sjmallett * consoles rather than UART0. No point doing that reorganization 339210311Sjmallett * until we actually intercept UART_DEV_CONSOLE for the UART1 case 340210311Sjmallett * and somehow handle the PCI console, which we lack code for 341210311Sjmallett * entirely. 342210311Sjmallett */ 343210311Sjmallett 344201845Simp /* Initialize pcpu stuff */ 345201881Simp mips_pcpu0_init(); 346202831Simp mips_timer_early_init(OCTEON_CLOCK_DEFAULT); 347202831Simp cninit(); 348201845Simp 349202831Simp octeon_ciu_reset(); 350200344Simp octeon_boot_params_init(a3); 351210311Sjmallett /* 352210311Sjmallett * XXX 353210311Sjmallett * We can certainly parse command line arguments or U-Boot environment 354210311Sjmallett * to determine whether to bootverbose / single user / ... I think 355210311Sjmallett * stass has patches to add support for loader things to U-Boot even. 356210311Sjmallett */ 357196262Simp bootverbose = 1; 358194140Simp 359202831Simp /* 360202831Simp * For some reason on the cn38xx simulator ebase register is set to 361202831Simp * 0x80001000 at bootup time. Move it back to the default, but 362202831Simp * when we move to having support for multiple executives, we need 363202831Simp * to rethink this. 364202831Simp */ 365202831Simp mips_wr_ebase(0x80000000); 366196262Simp 367202831Simp octeon_memory_init(); 368196262Simp init_param1(); 369196262Simp init_param2(physmem); 370196262Simp mips_cpu_init(); 371202831Simp pmap_bootstrap(); 372202831Simp mips_proc0_init(); 373196262Simp mutex_init(); 374196262Simp kdb_init(); 375202850Simp#ifdef KDB 376202850Simp if (boothowto & RB_KDB) 377202850Simp kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 378196262Simp#endif 379210311Sjmallett platform_counter_freq = cvmx_sysinfo_get()->cpu_clock_hz; 380210311Sjmallett 381210311Sjmallett octeon_timecounter.tc_frequency = cvmx_sysinfo_get()->cpu_clock_hz; 382210311Sjmallett platform_timecounter = &octeon_timecounter; 383210311Sjmallett 384206721Sjmallett mips_timer_init_params(platform_counter_freq, 0); 385206721Sjmallett 386210311Sjmallett set_cputicker(octeon_get_ticks, cvmx_sysinfo_get()->cpu_clock_hz, 0); 387210311Sjmallett 388206721Sjmallett#ifdef SMP 389206721Sjmallett /* 390210311Sjmallett * Clear any pending IPIs. 391206721Sjmallett */ 392210311Sjmallett cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff); 393206721Sjmallett#endif 394210311Sjmallett 395210311Sjmallett printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING); 396210311Sjmallett printf("Available Octeon features:"); 397210311Sjmallett for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++) 398210311Sjmallett if (octeon_has_feature(ofd->ofd_feature)) 399210311Sjmallett printf(" %s", ofd->ofd_string); 400210311Sjmallett printf("\n"); 401196262Simp} 402196262Simp 403210311Sjmallettstatic uint64_t 404210311Sjmallettocteon_get_ticks(void) 405210311Sjmallett{ 406210311Sjmallett uint64_t cvmcount; 407210311Sjmallett 408210311Sjmallett CVMX_MF_CYCLE(cvmcount); 409210311Sjmallett return (cvmcount); 410210311Sjmallett} 411210311Sjmallett 412210311Sjmallettstatic unsigned 413210311Sjmallettocteon_get_timecount(struct timecounter *tc) 414210311Sjmallett{ 415210311Sjmallett return ((unsigned)octeon_get_ticks()); 416210311Sjmallett} 417210311Sjmallett 418215990Sjmallett/** 419215990Sjmallett * version of printf that works better in exception context. 420215990Sjmallett * 421215990Sjmallett * @param format 422215990Sjmallett * 423215990Sjmallett * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version. 424215990Sjmallett */ 425215990Sjmallettvoid cvmx_safe_printf(const char *format, ...) 426215990Sjmallett{ 427215990Sjmallett char buffer[256]; 428215990Sjmallett char *ptr = buffer; 429215990Sjmallett int count; 430215990Sjmallett va_list args; 431215990Sjmallett 432215990Sjmallett va_start(args, format); 433215990Sjmallett#ifndef __U_BOOT__ 434215990Sjmallett count = vsnprintf(buffer, sizeof(buffer), format, args); 435215990Sjmallett#else 436215990Sjmallett count = vsprintf(buffer, format, args); 437215990Sjmallett#endif 438215990Sjmallett va_end(args); 439215990Sjmallett 440215990Sjmallett while (count-- > 0) 441215990Sjmallett { 442215990Sjmallett cvmx_uart_lsr_t lsrval; 443215990Sjmallett 444215990Sjmallett /* Spin until there is room */ 445215990Sjmallett do 446215990Sjmallett { 447215990Sjmallett lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0)); 448215990Sjmallett#if !defined(CONFIG_OCTEON_SIM_SPEED) 449215990Sjmallett if (lsrval.s.temt == 0) 450215990Sjmallett cvmx_wait(10000); /* Just to reduce the load on the system */ 451215990Sjmallett#endif 452215990Sjmallett } 453215990Sjmallett while (lsrval.s.temt == 0); 454215990Sjmallett 455215990Sjmallett if (*ptr == '\n') 456215990Sjmallett cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r'); 457215990Sjmallett cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++); 458215990Sjmallett } 459215990Sjmallett} 460215990Sjmallett 461202831Simp/* impSTART: This stuff should move back into the Cavium SDK */ 462194140Simp/* 463194140Simp **************************************************************************************** 464194140Simp * 465194140Simp * APP/BOOT DESCRIPTOR STUFF 466194140Simp * 467194140Simp **************************************************************************************** 468194140Simp */ 469194140Simp 470194140Simp/* Define the struct that is initialized by the bootloader used by the 471194140Simp * startup code. 472194140Simp * 473194140Simp * Copyright (c) 2004, 2005, 2006 Cavium Networks. 474194140Simp * 475194140Simp * The authors hereby grant permission to use, copy, modify, distribute, 476194140Simp * and license this software and its documentation for any purpose, provided 477194140Simp * that existing copyright notices are retained in all copies and that this 478194140Simp * notice is included verbatim in any distributions. No written agreement, 479194140Simp * license, or royalty fee is required for any of the authorized uses. 480194140Simp * Modifications to this software may be copyrighted by their authors 481194140Simp * and need not follow the licensing terms described here, provided that 482194140Simp * the new terms are clearly indicated on the first page of each file where 483194140Simp * they apply. 484194140Simp */ 485194140Simp 486194140Simp#define OCTEON_CURRENT_DESC_VERSION 6 487194140Simp#define OCTEON_ARGV_MAX_ARGS (64) 488194140Simp#define OCTOEN_SERIAL_LEN 20 489194140Simp 490194140Simptypedef struct { 491200344Simp /* Start of block referenced by assembly code - do not change! */ 492200344Simp uint32_t desc_version; 493200344Simp uint32_t desc_size; 494194140Simp 495200344Simp uint64_t stack_top; 496200344Simp uint64_t heap_base; 497200344Simp uint64_t heap_end; 498200344Simp uint64_t entry_point; /* Only used by bootloader */ 499200344Simp uint64_t desc_vaddr; 500200344Simp /* End of This block referenced by assembly code - do not change! */ 501194140Simp 502200344Simp uint32_t exception_base_addr; 503200344Simp uint32_t stack_size; 504200344Simp uint32_t heap_size; 505200344Simp uint32_t argc; /* Argc count for application */ 506200344Simp uint32_t argv[OCTEON_ARGV_MAX_ARGS]; 507200344Simp uint32_t flags; 508200344Simp uint32_t core_mask; 509200344Simp uint32_t dram_size; /**< DRAM size in megabyes */ 510200344Simp uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/ 511200344Simp uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */ 512200344Simp uint32_t eclock_hz; /**< CPU clock speed, in hz */ 513200344Simp uint32_t dclock_hz; /**< DRAM clock speed, in hz */ 514200344Simp uint32_t spi_clock_hz; /**< SPI4 clock in hz */ 515200344Simp uint16_t board_type; 516200344Simp uint8_t board_rev_major; 517200344Simp uint8_t board_rev_minor; 518200344Simp uint16_t chip_type; 519200344Simp uint8_t chip_rev_major; 520200344Simp uint8_t chip_rev_minor; 521200344Simp char board_serial_number[OCTOEN_SERIAL_LEN]; 522200344Simp uint8_t mac_addr_base[6]; 523200344Simp uint8_t mac_addr_count; 524200344Simp uint64_t cvmx_desc_vaddr; 525194140Simp} octeon_boot_descriptor_t; 526194140Simp 527210311Sjmallettcvmx_bootinfo_t *octeon_bootinfo; 528194140Simp 529194140Simpstatic octeon_boot_descriptor_t *app_desc_ptr; 530194140Simp 531200344Simpint 532210311Sjmallettocteon_is_simulation(void) 533194140Simp{ 534210311Sjmallett switch (cvmx_sysinfo_get()->board_type) { 535210311Sjmallett case CVMX_BOARD_TYPE_SIM: 536204777Sjmallett return 1; 537204777Sjmallett default: 538210311Sjmallett return 0; 539204777Sjmallett } 540194140Simp} 541194140Simp 542200344Simpstatic void 543210311Sjmallettocteon_process_app_desc_ver_6(void) 544194140Simp{ 545200344Simp /* XXX Why is 0x00000000ffffffffULL a bad value? */ 546200344Simp if (app_desc_ptr->cvmx_desc_vaddr == 0 || 547210311Sjmallett app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful) 548210311Sjmallett panic("Bad octeon_bootinfo %p", octeon_bootinfo); 549210311Sjmallett 550210311Sjmallett octeon_bootinfo = 551200344Simp (cvmx_bootinfo_t *)(intptr_t)app_desc_ptr->cvmx_desc_vaddr; 552210311Sjmallett octeon_bootinfo = 553210311Sjmallett (cvmx_bootinfo_t *) ((intptr_t)octeon_bootinfo | MIPS_KSEG0_START); 554210311Sjmallett if (octeon_bootinfo->major_version != 1) 555210311Sjmallett panic("Incompatible CVMX descriptor from bootloader: %d.%d %p", 556210311Sjmallett (int) octeon_bootinfo->major_version, 557210311Sjmallett (int) octeon_bootinfo->minor_version, octeon_bootinfo); 558194140Simp 559215990Sjmallett cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr, 560210311Sjmallett octeon_bootinfo->board_type, 561210311Sjmallett octeon_bootinfo->board_rev_major, 562210311Sjmallett octeon_bootinfo->board_rev_minor, 563210311Sjmallett octeon_bootinfo->eclock_hz); 564194140Simp} 565194140Simp 566200344Simpstatic void 567200344Simpocteon_boot_params_init(register_t ptr) 568194140Simp{ 569210311Sjmallett if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR) 570210311Sjmallett panic("app descriptor passed at invalid address %#jx", 571210311Sjmallett (uintmax_t)ptr); 572194140Simp 573210311Sjmallett app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr; 574210311Sjmallett if (app_desc_ptr->desc_version < 6) 575210311Sjmallett panic("Your boot code is too old to be supported."); 576210311Sjmallett octeon_process_app_desc_ver_6(); 577210311Sjmallett 578210311Sjmallett KASSERT(octeon_bootinfo != NULL, ("octeon_bootinfo should be set")); 579210311Sjmallett 580215990Sjmallett if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0) 581210311Sjmallett panic("Your boot loader did not supply a memory descriptor."); 582215990Sjmallett cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr); 583210311Sjmallett 584194140Simp printf("Boot Descriptor Ver: %u -> %u/%u", 585210311Sjmallett app_desc_ptr->desc_version, octeon_bootinfo->major_version, 586210311Sjmallett octeon_bootinfo->minor_version); 587210311Sjmallett printf(" CPU clock: %uMHz Core Mask: %#x\n", 588210311Sjmallett cvmx_sysinfo_get()->cpu_clock_hz / 1000000, 589210311Sjmallett cvmx_sysinfo_get()->core_mask); 590194140Simp printf(" Board Type: %u Revision: %u/%u\n", 591210311Sjmallett cvmx_sysinfo_get()->board_type, 592210311Sjmallett cvmx_sysinfo_get()->board_rev_major, 593210311Sjmallett cvmx_sysinfo_get()->board_rev_minor); 594194140Simp 595202831Simp printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n", 596210311Sjmallett octeon_bootinfo->mac_addr_base[0], 597210311Sjmallett octeon_bootinfo->mac_addr_base[1], 598210311Sjmallett octeon_bootinfo->mac_addr_base[2], 599210311Sjmallett octeon_bootinfo->mac_addr_base[3], 600210311Sjmallett octeon_bootinfo->mac_addr_base[4], 601210311Sjmallett octeon_bootinfo->mac_addr_base[5], 602210311Sjmallett octeon_bootinfo->mac_addr_count); 603210311Sjmallett 604210311Sjmallett#if defined(OCTEON_BOARD_CAPK_0100ND) 605210311Sjmallett if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) 606210311Sjmallett printf("Compiled for CAPK-0100ND, but board type is %s\n", 607210311Sjmallett cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 608210311Sjmallett#else 609210311Sjmallett printf("Board: %s\n", 610210311Sjmallett cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 611210311Sjmallett#endif 612210311Sjmallett printf("Model: %s\n", octeon_model_get_string(cvmx_get_proc_id())); 613194140Simp} 614202831Simp/* impEND: This stuff should move back into the Cavium SDK */ 615