ar933xreg.h revision 256482
1/*-
2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/mips/atheros/ar933xreg.h 256482 2013-10-14 23:57:12Z adrian $
27 */
28
29#ifndef	__AR93XX_REG_H__
30#define	__AR93XX_REG_H__
31
32#define	REV_ID_MAJOR_AR9330		0x0110
33#define	REV_ID_MAJOR_AR9331		0x1110
34
35#define	AR933X_REV_ID_REVISION_MASK	0x3
36
37#define	AR933X_GPIO_COUNT		30
38
39#define	AR933X_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
40#define	AR933X_UART_SIZE	0x14
41
42#define	AR933X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
43#define	AR933X_GMAC_SIZE	0x04
44
45#define	AR933X_GMAC_REG_ETH_CFG		(AR933X_GMAC_BASE + 0x00)
46
47#define	AR933X_ETH_CFG_RGMII_GE0	(1 << 0)
48#define	AR933X_ETH_CFG_MII_GE0		(1 << 1)
49#define	AR933X_ETH_CFG_GMII_GE0		(1 << 2)
50#define	AR933X_ETH_CFG_MII_GE0_MASTER	(1 << 3)
51#define	AR933X_ETH_CFG_MII_GE0_SLAVE	(1 << 4)
52#define	AR933X_ETH_CFG_MII_GE0_ERR_EN	(1 << 5)
53#define	AR933X_ETH_CFG_SW_PHY_SWAP	(1 << 7)
54#define	AR933X_ETH_CFG_SW_PHY_ADDR_SWAP	(1 << 8)
55#define	AR933X_ETH_CFG_RMII_GE0		(1 << 9)
56#define	AR933X_ETH_CFG_RMII_GE0_SPD_10		0
57#define	AR933X_ETH_CFG_RMII_GE0_SPD_100		(1 << 10)
58
59#define	AR933X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
60#define	AR933X_WMAC_SIZE	0x20000
61#define	AR933X_EHCI_BASE	0x1b000000
62#define	AR933X_EHCI_SIZE	0x1000
63
64#define	AR933X_DDR_REG_FLUSH_GE0	(AR71XX_APB_BASE + 0x7c)
65#define	AR933X_DDR_REG_FLUSH_GE1	(AR71XX_APB_BASE + 0x80)
66#define	AR933X_DDR_REG_FLUSH_USB	(AR71XX_APB_BASE + 0x84)
67#define	AR933X_DDR_REG_FLUSH_WMAC	(AR71XX_APB_BASE + 0x88)
68
69#define	AR933X_PLL_CPU_CONFIG_REG	(AR71XX_PLL_CPU_BASE + 0x00)
70#define	AR933X_PLL_CLOCK_CTRL_REG	(AR71XX_PLL_CPU_BASE + 0x08)
71
72#define	AR933X_PLL_CPU_CONFIG_NINT_SHIFT	10
73#define	AR933X_PLL_CPU_CONFIG_NINT_MASK		0x3f
74#define	AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT	16
75#define	AR933X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
76#define	AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT	23
77#define	AR933X_PLL_CPU_CONFIG_OUTDIV_MASK	0x7
78
79#define	AR933X_PLL_CLOCK_CTRL_BYPASS		(1 << 2)
80#define	AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT	5
81#define	AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK	0x3
82#define	AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT	10
83#define	AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK	0x3
84#define	AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT	15
85#define	AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK	0x7
86
87#define	AR933X_RESET_REG_RESET_MODULE		(AR71XX_RST_BLOCK_BASE + 0x1c)
88#define	AR933X_RESET_REG_BOOTSTRAP		(AR71XX_RST_BLOCK_BASE + 0xac)
89#define	AR933X_RESET_WMAC			(1 << 11)
90#define	AR933X_RESET_USB_HOST			(1 << 5)
91#define	AR933X_RESET_USB_PHY			(1 << 4)
92#define	AR933X_RESET_USBSUS_OVERRIDE		(1 << 3)
93
94#define	AR933X_BOOTSTRAP_REF_CLK_40		(1 << 0)
95
96#define	AR933X_PLL_VAL_1000			0x00110000
97#define	AR933X_PLL_VAL_100			0x00001099
98#define	AR933X_PLL_VAL_10			0x00991099
99
100#endif	/* __AR93XX_REG_H__ */
101