1248782Sadrian/*- 2248782Sadrian * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org> 3248782Sadrian * All rights reserved. 4248782Sadrian * 5248782Sadrian * Redistribution and use in source and binary forms, with or without 6248782Sadrian * modification, are permitted provided that the following conditions 7248782Sadrian * are met: 8248782Sadrian * 1. Redistributions of source code must retain the above copyright 9248782Sadrian * notice, this list of conditions and the following disclaimer. 10248782Sadrian * 2. Redistributions in binary form must reproduce the above copyright 11248782Sadrian * notice, this list of conditions and the following disclaimer in the 12248782Sadrian * documentation and/or other materials provided with the distribution. 13248782Sadrian * 14248782Sadrian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15248782Sadrian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16248782Sadrian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17248782Sadrian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18248782Sadrian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19248782Sadrian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20248782Sadrian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21248782Sadrian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22248782Sadrian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23248782Sadrian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24248782Sadrian * SUCH DAMAGE. 25248782Sadrian * 26248782Sadrian * $FreeBSD: releng/11.0/sys/mips/atheros/ar933xreg.h 256482 2013-10-14 23:57:12Z adrian $ 27248782Sadrian */ 28248782Sadrian 29248782Sadrian#ifndef __AR93XX_REG_H__ 30248782Sadrian#define __AR93XX_REG_H__ 31248782Sadrian 32248782Sadrian#define REV_ID_MAJOR_AR9330 0x0110 33248782Sadrian#define REV_ID_MAJOR_AR9331 0x1110 34248782Sadrian 35248782Sadrian#define AR933X_REV_ID_REVISION_MASK 0x3 36248782Sadrian 37248782Sadrian#define AR933X_GPIO_COUNT 30 38248782Sadrian 39248782Sadrian#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) 40248782Sadrian#define AR933X_UART_SIZE 0x14 41256482Sadrian 42256482Sadrian#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) 43256482Sadrian#define AR933X_GMAC_SIZE 0x04 44256482Sadrian 45256482Sadrian#define AR933X_GMAC_REG_ETH_CFG (AR933X_GMAC_BASE + 0x00) 46256482Sadrian 47256482Sadrian#define AR933X_ETH_CFG_RGMII_GE0 (1 << 0) 48256482Sadrian#define AR933X_ETH_CFG_MII_GE0 (1 << 1) 49256482Sadrian#define AR933X_ETH_CFG_GMII_GE0 (1 << 2) 50256482Sadrian#define AR933X_ETH_CFG_MII_GE0_MASTER (1 << 3) 51256482Sadrian#define AR933X_ETH_CFG_MII_GE0_SLAVE (1 << 4) 52256482Sadrian#define AR933X_ETH_CFG_MII_GE0_ERR_EN (1 << 5) 53256482Sadrian#define AR933X_ETH_CFG_SW_PHY_SWAP (1 << 7) 54256482Sadrian#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP (1 << 8) 55256482Sadrian#define AR933X_ETH_CFG_RMII_GE0 (1 << 9) 56256482Sadrian#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 57256482Sadrian#define AR933X_ETH_CFG_RMII_GE0_SPD_100 (1 << 10) 58256482Sadrian 59248782Sadrian#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) 60248782Sadrian#define AR933X_WMAC_SIZE 0x20000 61248782Sadrian#define AR933X_EHCI_BASE 0x1b000000 62248782Sadrian#define AR933X_EHCI_SIZE 0x1000 63248782Sadrian 64248782Sadrian#define AR933X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x7c) 65248782Sadrian#define AR933X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0x80) 66248782Sadrian#define AR933X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0x84) 67248782Sadrian#define AR933X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0x88) 68248782Sadrian 69248782Sadrian#define AR933X_PLL_CPU_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x00) 70248782Sadrian#define AR933X_PLL_CLOCK_CTRL_REG (AR71XX_PLL_CPU_BASE + 0x08) 71248782Sadrian 72248782Sadrian#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 73248782Sadrian#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f 74248782Sadrian#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 75248782Sadrian#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 76248782Sadrian#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 77248782Sadrian#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 78248782Sadrian 79248782Sadrian#define AR933X_PLL_CLOCK_CTRL_BYPASS (1 << 2) 80248782Sadrian#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 81248782Sadrian#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 82248782Sadrian#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 83248782Sadrian#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 84248782Sadrian#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 85248782Sadrian#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 86248782Sadrian 87248782Sadrian#define AR933X_RESET_REG_RESET_MODULE (AR71XX_RST_BLOCK_BASE + 0x1c) 88248782Sadrian#define AR933X_RESET_REG_BOOTSTRAP (AR71XX_RST_BLOCK_BASE + 0xac) 89248782Sadrian#define AR933X_RESET_WMAC (1 << 11) 90248782Sadrian#define AR933X_RESET_USB_HOST (1 << 5) 91248782Sadrian#define AR933X_RESET_USB_PHY (1 << 4) 92248782Sadrian#define AR933X_RESET_USBSUS_OVERRIDE (1 << 3) 93248782Sadrian 94248782Sadrian#define AR933X_BOOTSTRAP_REF_CLK_40 (1 << 0) 95248782Sadrian 96249123Sadrian#define AR933X_PLL_VAL_1000 0x00110000 97249123Sadrian#define AR933X_PLL_VAL_100 0x00001099 98249123Sadrian#define AR933X_PLL_VAL_10 0x00991099 99249123Sadrian 100248782Sadrian#endif /* __AR93XX_REG_H__ */ 101