adm5120reg.h revision 178173
1178173Simp/* $NetBSD: adm5120reg.h,v 1.1 2007/03/20 08:52:03 dyoung Exp $ */ 2178173Simp 3178173Simp/*- 4178173Simp * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5178173Simp * All rights reserved. 6178173Simp * 7178173Simp * Redistribution and use in source and binary forms, with or 8178173Simp * without modification, are permitted provided that the following 9178173Simp * conditions are met: 10178173Simp * 1. Redistributions of source code must retain the above copyright 11178173Simp * notice, this list of conditions and the following disclaimer. 12178173Simp * 2. Redistributions in binary form must reproduce the above 13178173Simp * copyright notice, this list of conditions and the following 14178173Simp * disclaimer in the documentation and/or other materials provided 15178173Simp * with the distribution. 16178173Simp * 3. The names of the authors may not be used to endorse or promote 17178173Simp * products derived from this software without specific prior 18178173Simp * written permission. 19178173Simp * 20178173Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21178173Simp * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22178173Simp * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23178173Simp * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24178173Simp * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25178173Simp * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26178173Simp * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27178173Simp * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28178173Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29178173Simp * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30178173Simp * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31178173Simp * OF SUCH DAMAGE. 32178173Simp * 33178173Simp * $FreeBSD: head/sys/mips/mips32/adm5120/adm5120reg.h 178173 2008-04-13 07:44:55Z imp $ 34178173Simp */ 35178173Simp 36178173Simp#ifndef _ADM5120REG_H_ 37178173Simp#define _ADM5120REG_H_ 38178173Simp 39178173Simp/* Helpers from NetBSD */ 40178173Simp/* __BIT(n): nth bit, where __BIT(0) == 0x1. */ 41178173Simp#define __BIT(__n) \ 42178173Simp (((__n) >= NBBY * sizeof(uintmax_t)) ? 0 : ((uintmax_t)1 << (__n))) 43178173Simp 44178173Simp/* __BITS(m, n): bits m through n, m < n. */ 45178173Simp#define __BITS(__m, __n) \ 46178173Simp ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1)) 47178173Simp 48178173Simp/* Last byte of physical address space. */ 49178173Simp#define ADM5120_TOP 0x1fffffff 50178173Simp#define ADM5120_BOTTOM 0x0 51178173Simp 52178173Simp/* Flash addresses */ 53178173Simp#define ADM5120_BASE_SRAM0 0x1fc00000 54178173Simp 55178173Simp/* UARTs */ 56178173Simp#define ADM5120_BASE_UART1 0x12800000 57178173Simp#define ADM5120_BASE_UART0 0x12600000 58178173Simp 59178173Simp/* ICU */ 60178173Simp#define ADM5120_BASE_ICU 0x12200000 61178173Simp#define ICU_STATUS_REG 0x00 62178173Simp#define ICU_RAW_STATUS_REG 0x04 63178173Simp#define ICU_ENABLE_REG 0x08 64178173Simp#define ICU_DISABLE_REG 0x0c 65178173Simp#define ICU_SOFT_REG 0x10 66178173Simp#define ICU_MODE_REG 0x14 67178173Simp#define ICU_FIQ_STATUS_REG 0x18 68178173Simp#define ICU_TESTSRC_REG 0x1c 69178173Simp#define ICU_SRCSEL_REG 0x20 70178173Simp#define ICU_LEVEL_REG 0x24 71178173Simp#define ICU_INT_MASK 0x3ff 72178173Simp 73178173Simp/* Switch */ 74178173Simp#define ADM5120_BASE_SWITCH 0x12000000 75178173Simp#define SW_CODE_REG 0x00 76178173Simp#define CLKS_MASK 0x00300000 77178173Simp#define CLKS_175MHZ 0x00000000 78178173Simp#define CLKS_200MHZ 0x00100000 79178173Simp#define SW_SFTRES_REG 0x04 80178173Simp#define SW_MEMCONT_REG 0x1c 81178173Simp#define SDRAM_SIZE_4MBYTES 0x0001 82178173Simp#define SDRAM_SIZE_8MBYTES 0x0002 83178173Simp#define SDRAM_SIZE_16MBYTES 0x0003 84178173Simp#define SDRAM_SIZE_64MBYTES 0x0004 85178173Simp#define SDRAM_SIZE_128MBYTES 0x0005 86178173Simp#define SDRAM_SIZE_MASK 0x0007 87178173Simp#define SRAM0_SIZE_SHIFT 8 88178173Simp#define SRAM1_SIZE_SHIFT 16 89178173Simp#define SRAM_MASK 0x0007 90178173Simp#define SRAM_SSIZE 0x40000 91178173Simp 92178173Simp#define ADM5120_BASE_PCI_CONFDATA 0x115ffff8 93178173Simp#define ADM5120_BASE_PCI_CONFADDR 0x115ffff0 94178173Simp#define ADM5120_BASE_PCI_IO 0x11500000 95178173Simp#define ADM5120_BASE_PCI_MEM 0x11400000 96178173Simp#define ADM5120_BASE_USB 0x11200000 97178173Simp#define ADM5120_BASE_MPMC 0x11000000 98178173Simp#define ADM5120_BASE_EXTIO1 0x10e00000 99178173Simp#define ADM5120_BASE_EXTIO0 0x10c00000 100178173Simp#define ADM5120_BASE_RSVD0 0x10800000 101178173Simp#define ADM5120_BASE_SRAM1 0x10000000 102178173Simp 103178173Simp#define _REG_READ(b, o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((b) + (o))) 104178173Simp#define SW_READ(o) _REG_READ(ADM5120_BASE_SWITCH, o) 105178173Simp 106178173Simp#define _REG_WRITE(b, o, v) (_REG_READ(b, o)) = (v) 107178173Simp#define SW_WRITE(o, v) _REG_WRITE(ADM5120_BASE_SWITCH,o, v) 108178173Simp 109178173Simp/* USB */ 110178173Simp 111178173Simp/* Watchdog Timers: base address is switch controller */ 112178173Simp 113178173Simp#define ADM5120_WDOG0 0x00c0 114178173Simp#define ADM5120_WDOG1 0x00c4 115178173Simp 116178173Simp#define ADM5120_WDOG0_WTTR __BIT(31) /* 0: do not reset, 117178173Simp * 1: reset on wdog expiration 118178173Simp */ 119178173Simp#define ADM5120_WDOG1_WDE __BIT(31) /* 0: deactivate, 120178173Simp * 1: drop all CPU-bound 121178173Simp * packets, disable flow 122178173Simp * control on all ports. 123178173Simp */ 124178173Simp#define ADM5120_WDOG_WTS_MASK __BITS(30, 16) /* Watchdog Timer Set: 125178173Simp * timer expires when it 126178173Simp * reaches WTS. Units of 127178173Simp * 10ms. 128178173Simp */ 129178173Simp#define ADM5120_WDOG_RSVD __BIT(15) 130178173Simp#define ADM5120_WDOG_WT_MASK __BITS(14, 0) /* Watchdog Timer: 131178173Simp * counts up, write to clear. 132178173Simp */ 133178173Simp 134178173Simp/* GPIO: base address is switch controller */ 135178173Simp#define ADM5120_GPIO0 0x00b8 136178173Simp 137178173Simp#define ADM5120_GPIO0_OV __BITS(31, 24) /* rw: output value */ 138178173Simp#define ADM5120_GPIO0_OE __BITS(23, 16) /* rw: output enable, 139178173Simp * bit[n] = 0 -> input 140178173Simp * bit[n] = 1 -> output 141178173Simp */ 142178173Simp#define ADM5120_GPIO0_IV __BITS(15, 8) /* ro: input value */ 143178173Simp#define ADM5120_GPIO0_RSVD __BITS(7, 0) /* rw: reserved */ 144178173Simp 145178173Simp#define ADM5120_GPIO2 0x00bc 146178173Simp#define ADM5120_GPIO2_EW __BIT(6) /* 1: enable wait state pin, 147178173Simp * pin GPIO[0], for GPIO[1] 148178173Simp * or GPIO[3] Chip Select: 149178173Simp * memory controller waits for 150178173Simp * WAIT# inactive (high). 151178173Simp */ 152178173Simp#define ADM5120_GPIO2_CSX1 __BIT(5) /* 1: GPIO[3:4] act as 153178173Simp * Chip Select for 154178173Simp * External I/O 1 (CSX1) 155178173Simp * and External Interrupt 1 156178173Simp * (INTX1), respectively. 157178173Simp * 0: CSX1/INTX1 disabled 158178173Simp */ 159178173Simp#define ADM5120_GPIO2_CSX0 __BIT(4) /* 1: GPIO[1:2] act as 160178173Simp * Chip Select for 161178173Simp * External I/O 0 (CSX0) 162178173Simp * and External Interrupt 0 163178173Simp * (INTX0), respectively. 164178173Simp * 0: CSX0/INTX0 disabled 165178173Simp */ 166178173Simp 167178173Simp/* MultiPort Memory Controller (MPMC) */ 168178173Simp 169178173Simp#define ADM5120_MPMC_CONTROL 0x000 170178173Simp#define ADM5120_MPMC_CONTROL_DWB __BIT(3) /* write 1 to 171178173Simp * drain write 172178173Simp * buffers. write 0 173178173Simp * for normal buffer 174178173Simp * operation. 175178173Simp */ 176178173Simp#define ADM5120_MPMC_CONTROL_LPM __BIT(2) /* 1: activate low-power 177178173Simp * mode. SDRAM is 178178173Simp * still refreshed. 179178173Simp */ 180178173Simp#define ADM5120_MPMC_CONTROL_AM __BIT(1) /* 1: address mirror: 181178173Simp * static memory 182178173Simp * chip select 0 183178173Simp * is mapped to chip 184178173Simp * select 1. 185178173Simp */ 186178173Simp#define ADM5120_MPMC_CONTROL_ME __BIT(0) /* 0: disable MPMC. 187178173Simp * DRAM is not 188178173Simp * refreshed. 189178173Simp * 1: enable MPMC. 190178173Simp */ 191178173Simp 192178173Simp#define ADM5120_MPMC_STATUS 0x004 193178173Simp#define ADM5120_MPMC_STATUS_SRA __BIT(2) /* read-only 194178173Simp * MPMC operating mode 195178173Simp * indication, 196178173Simp * 1: self-refresh 197178173Simp * acknowledge 198178173Simp * 0: normal mode 199178173Simp */ 200178173Simp#define ADM5120_MPMC_STATUS_WBS __BIT(1) /* read-only 201178173Simp * write-buffer status, 202178173Simp * 0: buffers empty 203178173Simp * 1: contain data 204178173Simp */ 205178173Simp#define ADM5120_MPMC_STATUS_BU __BIT(0) /* read-only MPMC 206178173Simp * "busy" indication, 207178173Simp * 0: MPMC idle 208178173Simp * 1: MPMC is performing 209178173Simp * memory transactions 210178173Simp */ 211178173Simp 212178173Simp#define ADM5120_MPMC_SEW 0x080 213178173Simp#define ADM5120_MPMC_SEW_RSVD __BITS(31, 10) 214178173Simp#define ADM5120_MPMC_SEW_EWTO __BITS(9, 0) /* timeout access after 215178173Simp * 16 * (n + 1) clock cycles 216178173Simp * (XXX which clock?) 217178173Simp */ 218178173Simp 219178173Simp#define ADM5120_MPMC_SC(__i) (0x200 + 0x020 * (__i)) 220178173Simp#define ADM5120_MPMC_SC_RSVD0 __BITS(31, 21) 221178173Simp#define ADM5120_MPMC_SC_WP __BIT(20) /* 1: write protect */ 222178173Simp#define ADM5120_MPMC_SC_BE __BIT(20) /* 1: enable write buffer */ 223178173Simp#define ADM5120_MPMC_SC_RSVD1 __BITS(18, 9) 224178173Simp#define ADM5120_MPMC_SC_EW __BIT(8) /* 1: enable extended wait; 225178173Simp */ 226178173Simp#define ADM5120_MPMC_SC_BLS __BIT(7) /* 0: byte line state pins 227178173Simp * are active high on read, 228178173Simp * active low on write. 229178173Simp * 230178173Simp * 1: byte line state pins 231178173Simp * are active low on read and 232178173Simp * on write. 233178173Simp */ 234178173Simp#define ADM5120_MPMC_SC_CCP __BIT(6) /* 0: chip select is active low, 235178173Simp * 1: active high 236178173Simp */ 237178173Simp#define ADM5120_MPMC_SC_RSVD2 __BITS(5, 4) 238178173Simp#define ADM5120_MPMC_SC_PM __BIT(3) /* 0: page mode disabled, 239178173Simp * 1: enable asynchronous 240178173Simp * page mode four 241178173Simp */ 242178173Simp#define ADM5120_MPMC_SC_RSVD3 __BIT(2) 243178173Simp#define ADM5120_MPMC_SC_MW_MASK __BITS(1, 0) /* memory width, bits */ 244178173Simp#define ADM5120_MPMC_SC_MW_8B __SHIFTIN(0, ADM5120_MPMC_SC_MW_MASK) 245178173Simp#define ADM5120_MPMC_SC_MW_16B __SHIFTIN(1, ADM5120_MPMC_SC_MW_MASK) 246178173Simp#define ADM5120_MPMC_SC_MW_32B __SHIFTIN(2, ADM5120_MPMC_SC_MW_MASK) 247178173Simp#define ADM5120_MPMC_SC_MW_RSVD __SHIFTIN(3, ADM5120_MPMC_SC_MW_MASK) 248178173Simp 249178173Simp#define ADM5120_MPMC_SWW(__i) (0x204 + 0x020 * (__i)) 250178173Simp#define ADM5120_MPMC_SWW_RSVD __BITS(31, 4) 251178173Simp#define ADM5120_MPMC_SWW_WWE __BITS(3, 0) /* delay (n + 1) * HCLK cycles 252178173Simp * after asserting chip select 253178173Simp * (CS) before asserting write 254178173Simp * enable (WE) 255178173Simp */ 256178173Simp 257178173Simp#define ADM5120_MPMC_SWO(__i) (0x208 + 0x020 * (__i)) 258178173Simp#define ADM5120_MPMC_SWO_RSVD __BITS(31, 4) 259178173Simp#define ADM5120_MPMC_SWO_WOE __BITS(3, 0) /* delay n * HCLK cycles 260178173Simp * after asserting chip select 261178173Simp * before asserting output 262178173Simp * enable (OE) 263178173Simp */ 264178173Simp 265178173Simp#define ADM5120_MPMC_SWR(__i) (0x20c + 0x020 * (__i)) 266178173Simp#define ADM5120_MPMC_SWR_RSVD __BITS(31, 5) 267178173Simp#define ADM5120_MPMC_SWR_NMRW __BITS(4, 0) /* read wait states for 268178173Simp * either first page-mode 269178173Simp * access or for non-page mode 270178173Simp * read, (n + 1) * HCLK cycles 271178173Simp */ 272178173Simp 273178173Simp#define ADM5120_MPMC_SWP(__i) (0x210 + 0x020 * (__i)) 274178173Simp#define ADM5120_MPMC_SWP_RSVD __BITS(31, 5) 275178173Simp#define ADM5120_MPMC_SWP_WPS __BITS(4, 0) /* read wait states for 276178173Simp * second and subsequent 277178173Simp * page-mode read, 278178173Simp * (n + 1) * HCLK cycles 279178173Simp */ 280178173Simp 281178173Simp#define ADM5120_MPMC_SWWR(__i) (0x214 + 0x020 * (__i)) 282178173Simp#define ADM5120_MPMC_SWWR_RSVD __BITS(31, 5) 283178173Simp#define ADM5120_MPMC_SWWR_WWS __BITS(4, 0) /* write wait states after 284178173Simp * the first read (??), 285178173Simp * (n + 2) * HCLK cycles 286178173Simp */ 287178173Simp 288178173Simp#define ADM5120_MPMC_SWT(__i) (0x218 + 0x020 * (__i)) 289178173Simp#define ADM5120_MPMC_SWT_RSVD __BITS(31, 4) 290178173Simp#define ADM5120_MPMC_SWT_WAITTURN __BITS(3, 0) /* bus turnaround time, 291178173Simp * (n + 1) * HCLK cycles 292178173Simp */ 293178173Simp 294178173Simp#endif /* _ADM5120REG_H_ */ 295