npx.c revision 78260
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $FreeBSD: head/sys/i386/isa/npx.c 78260 2001-06-15 07:53:20Z peter $ 36 */ 37 38#include "opt_debug_npx.h" 39#include "opt_math_emulate.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/module.h> 48#include <sys/mutex.h> 49#include <sys/mutex.h> 50#include <sys/proc.h> 51#include <sys/sysctl.h> 52#include <machine/bus.h> 53#include <sys/rman.h> 54#ifdef NPX_DEBUG 55#include <sys/syslog.h> 56#endif 57#include <sys/signalvar.h> 58#include <sys/user.h> 59 60#ifndef SMP 61#include <machine/asmacros.h> 62#endif 63#include <machine/cputypes.h> 64#include <machine/frame.h> 65#include <machine/md_var.h> 66#include <machine/pcb.h> 67#include <machine/psl.h> 68#ifndef SMP 69#include <machine/clock.h> 70#endif 71#include <machine/resource.h> 72#include <machine/specialreg.h> 73#include <machine/segments.h> 74 75#ifndef SMP 76#include <i386/isa/icu.h> 77#include <i386/isa/intr_machdep.h> 78#include <i386/isa/isa.h> 79#endif 80#include <isa/isavar.h> 81 82/* 83 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 84 */ 85 86/* Configuration flags. */ 87#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 88#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 89#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 90#define NPX_PREFER_EMULATOR (1 << 3) 91 92#ifdef __GNUC__ 93 94#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 95#define fnclex() __asm("fnclex") 96#define fninit() __asm("fninit") 97#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 98#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 99#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 100#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 101#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 102#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 103 : : "n" (CR0_TS) : "ax") 104#define stop_emulating() __asm("clts") 105 106#else /* not __GNUC__ */ 107 108void fldcw __P((caddr_t addr)); 109void fnclex __P((void)); 110void fninit __P((void)); 111void fnsave __P((caddr_t addr)); 112void fnstcw __P((caddr_t addr)); 113void fnstsw __P((caddr_t addr)); 114void fp_divide_by_0 __P((void)); 115void frstor __P((caddr_t addr)); 116void start_emulating __P((void)); 117void stop_emulating __P((void)); 118 119#endif /* __GNUC__ */ 120 121typedef u_char bool_t; 122 123static int npx_attach __P((device_t dev)); 124static void npx_identify __P((driver_t *driver, device_t parent)); 125#ifndef SMP 126static void npx_intr __P((void *)); 127#endif 128static int npx_probe __P((device_t dev)); 129static int npx_probe1 __P((device_t dev)); 130#ifdef I586_CPU_XXX 131static long timezero __P((const char *funcname, 132 void (*func)(void *buf, size_t len))); 133#endif /* I586_CPU */ 134 135int hw_float; /* XXX currently just alias for npx_exists */ 136 137SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 138 CTLFLAG_RD, &hw_float, 0, 139 "Floatingpoint instructions executed in hardware"); 140 141#ifndef SMP 142static volatile u_int npx_intrs_while_probing; 143static volatile u_int npx_traps_while_probing; 144#endif 145 146static bool_t npx_ex16; 147static bool_t npx_exists; 148static bool_t npx_irq13; 149static int npx_irq; /* irq number */ 150 151#ifndef SMP 152/* 153 * Special interrupt handlers. Someday intr0-intr15 will be used to count 154 * interrupts. We'll still need a special exception 16 handler. The busy 155 * latch stuff in probeintr() can be moved to npxprobe(). 156 */ 157inthand_t probeintr; 158__asm(" \n\ 159 .text \n\ 160 .p2align 2,0x90 \n\ 161 .type " __XSTRING(CNAME(probeintr)) ",@function \n\ 162" __XSTRING(CNAME(probeintr)) ": \n\ 163 ss \n\ 164 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\ 165 pushl %eax \n\ 166 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\ 167 outb %al,$0xa0 # IO_ICU2 \n\ 168 outb %al,$0x20 # IO_ICU1 \n\ 169 movb $0,%al \n\ 170 outb %al,$0xf0 # clear BUSY# latch \n\ 171 popl %eax \n\ 172 iret \n\ 173"); 174 175inthand_t probetrap; 176__asm(" \n\ 177 .text \n\ 178 .p2align 2,0x90 \n\ 179 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 180" __XSTRING(CNAME(probetrap)) ": \n\ 181 ss \n\ 182 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 183 fnclex \n\ 184 iret \n\ 185"); 186#endif /* SMP */ 187 188/* 189 * Identify routine. Create a connection point on our parent for probing. 190 */ 191static void 192npx_identify(driver, parent) 193 driver_t *driver; 194 device_t parent; 195{ 196 device_t child; 197 198 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 199 if (child == NULL) 200 panic("npx_identify"); 201} 202 203#ifndef SMP 204/* 205 * Do minimal handling of npx interrupts to convert them to traps. 206 */ 207static void 208npx_intr(dummy) 209 void *dummy; 210{ 211 struct proc *p; 212 213 /* 214 * The BUSY# latch must be cleared in all cases so that the next 215 * unmasked npx exception causes an interrupt. 216 */ 217 outb(0xf0, 0); 218 219 /* 220 * npxproc is normally non-null here. In that case, schedule an 221 * AST to finish the exception handling in the correct context 222 * (this interrupt may occur after the process has entered the 223 * kernel via a syscall or an interrupt). Otherwise, the npx 224 * state of the process that caused this interrupt must have been 225 * pushed to the process' pcb, and clearing of the busy latch 226 * above has finished the (essentially null) handling of this 227 * interrupt. Control will eventually return to the instruction 228 * that caused it and it will repeat. We will eventually (usually 229 * soon) win the race to handle the interrupt properly. 230 */ 231 p = PCPU_GET(npxproc); 232 if (p != NULL) { 233 p->p_addr->u_pcb.pcb_flags |= PCB_NPXTRAP; 234 mtx_lock_spin(&sched_lock); 235 aston(p); 236 mtx_unlock_spin(&sched_lock); 237 } 238} 239 240/* 241 * XXX these "local" variables of npx_probe() are non-local so that 242 * npxprobe1() can abuse them. 243 */ 244static int npx_intrno; 245static struct gate_descriptor save_idt_npxintr; 246#endif /* !SMP */ 247 248/* 249 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 250 * whether the device exists or not (XXX should be elsewhere). Set flags 251 * to tell npxattach() what to do. Modify device struct if npx doesn't 252 * need to use interrupts. Return 1 if device exists. 253 */ 254static int 255npx_probe(dev) 256 device_t dev; 257{ 258#ifdef SMP 259 260 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 261 npx_irq = 13; 262 return npx_probe1(dev); 263 264#else /* SMP */ 265 266 int result; 267 critical_t savecrit; 268 u_char save_icu1_mask; 269 u_char save_icu2_mask; 270 struct gate_descriptor save_idt_npxtrap; 271 /* 272 * This routine is now just a wrapper for npxprobe1(), to install 273 * special npx interrupt and trap handlers, to enable npx interrupts 274 * and to disable other interrupts. Someday isa_configure() will 275 * install suitable handlers and run with interrupts enabled so we 276 * won't need to do so much here. 277 */ 278 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 279 npx_irq = 13; 280 npx_intrno = NRSVIDT + npx_irq; 281 savecrit = critical_enter(); 282 save_icu1_mask = inb(IO_ICU1 + 1); 283 save_icu2_mask = inb(IO_ICU2 + 1); 284 save_idt_npxintr = idt[npx_intrno]; 285 save_idt_npxtrap = idt[16]; 286 outb(IO_ICU1 + 1, ~IRQ_SLAVE); 287 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8))); 288 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 289 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 290 291 /* 292 * XXX This looks highly bogus, but it appears that npc_probe1 293 * needs interrupts enabled. Does this make any difference 294 * here? 295 */ 296 critical_exit(savecrit); 297 result = npx_probe1(dev); 298 savecrit = critical_enter(); 299 outb(IO_ICU1 + 1, save_icu1_mask); 300 outb(IO_ICU2 + 1, save_icu2_mask); 301 idt[npx_intrno] = save_idt_npxintr; 302 idt[16] = save_idt_npxtrap; 303 critical_exit(savecrit); 304 return (result); 305 306#endif /* SMP */ 307} 308 309static int 310npx_probe1(dev) 311 device_t dev; 312{ 313#ifndef SMP 314 u_short control; 315 u_short status; 316#endif 317 318 /* 319 * Partially reset the coprocessor, if any. Some BIOS's don't reset 320 * it after a warm boot. 321 */ 322 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 323 outb(0xf0, 0); /* clear BUSY# latch */ 324 /* 325 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 326 * instructions. We must set the CR0_MP bit and use the CR0_TS 327 * bit to control the trap, because setting the CR0_EM bit does 328 * not cause WAIT instructions to trap. It's important to trap 329 * WAIT instructions - otherwise the "wait" variants of no-wait 330 * control instructions would degenerate to the "no-wait" variants 331 * after FP context switches but work correctly otherwise. It's 332 * particularly important to trap WAITs when there is no NPX - 333 * otherwise the "wait" variants would always degenerate. 334 * 335 * Try setting CR0_NE to get correct error reporting on 486DX's. 336 * Setting it should fail or do nothing on lesser processors. 337 */ 338 load_cr0(rcr0() | CR0_MP | CR0_NE); 339 /* 340 * But don't trap while we're probing. 341 */ 342 stop_emulating(); 343 /* 344 * Finish resetting the coprocessor, if any. If there is an error 345 * pending, then we may get a bogus IRQ13, but probeintr() will handle 346 * it OK. Bogus halts have never been observed, but we enabled 347 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 348 */ 349 fninit(); 350 351#ifdef SMP 352 /* 353 * Exception 16 MUST work for SMP. 354 */ 355 npx_irq13 = 0; 356 npx_ex16 = hw_float = npx_exists = 1; 357 device_set_desc(dev, "math processor"); 358 return (0); 359 360#else /* !SMP */ 361 device_set_desc(dev, "math processor"); 362 363 /* 364 * Don't use fwait here because it might hang. 365 * Don't use fnop here because it usually hangs if there is no FPU. 366 */ 367 DELAY(1000); /* wait for any IRQ13 */ 368#ifdef DIAGNOSTIC 369 if (npx_intrs_while_probing != 0) 370 printf("fninit caused %u bogus npx interrupt(s)\n", 371 npx_intrs_while_probing); 372 if (npx_traps_while_probing != 0) 373 printf("fninit caused %u bogus npx trap(s)\n", 374 npx_traps_while_probing); 375#endif 376 /* 377 * Check for a status of mostly zero. 378 */ 379 status = 0x5a5a; 380 fnstsw(&status); 381 if ((status & 0xb8ff) == 0) { 382 /* 383 * Good, now check for a proper control word. 384 */ 385 control = 0x5a5a; 386 fnstcw(&control); 387 if ((control & 0x1f3f) == 0x033f) { 388 hw_float = npx_exists = 1; 389 /* 390 * We have an npx, now divide by 0 to see if exception 391 * 16 works. 392 */ 393 control &= ~(1 << 2); /* enable divide by 0 trap */ 394 fldcw(&control); 395 npx_traps_while_probing = npx_intrs_while_probing = 0; 396 fp_divide_by_0(); 397 if (npx_traps_while_probing != 0) { 398 /* 399 * Good, exception 16 works. 400 */ 401 npx_ex16 = 1; 402 return (0); 403 } 404 if (npx_intrs_while_probing != 0) { 405 int rid; 406 struct resource *r; 407 void *intr; 408 /* 409 * Bad, we are stuck with IRQ13. 410 */ 411 npx_irq13 = 1; 412 413 /* 414 * We allocate these resources permanently, 415 * so there is no need to keep track of them. 416 */ 417 rid = 0; 418 r = bus_alloc_resource(dev, SYS_RES_IOPORT, 419 &rid, IO_NPX, IO_NPX, 420 IO_NPXSIZE, RF_ACTIVE); 421 if (r == 0) 422 panic("npx: can't get ports"); 423 rid = 0; 424 r = bus_alloc_resource(dev, SYS_RES_IRQ, 425 &rid, npx_irq, npx_irq, 426 1, RF_ACTIVE); 427 if (r == 0) 428 panic("npx: can't get IRQ"); 429 BUS_SETUP_INTR(device_get_parent(dev), 430 dev, r, 431 INTR_TYPE_MISC | INTR_FAST, 432 npx_intr, 0, &intr); 433 if (intr == 0) 434 panic("npx: can't create intr"); 435 436 /* 437 * XXX BUS_SETUP_INTR() has changed 438 * idt[npx_intrno] to point to Xfastintr0 439 * instead of Xfastintr0. Adjust 440 * save_idt_npxintr so that npxprobe() 441 * doesn't undo this. 442 */ 443 save_idt_npxintr = idt[npx_intrno]; 444 445 return (0); 446 } 447 /* 448 * Worse, even IRQ13 is broken. Use emulator. 449 */ 450 } 451 } 452 /* 453 * Probe failed, but we want to get to npxattach to initialize the 454 * emulator and say that it has been installed. XXX handle devices 455 * that aren't really devices better. 456 */ 457 return (0); 458#endif /* SMP */ 459} 460 461/* 462 * Attach routine - announce which it is, and wire into system 463 */ 464int 465npx_attach(dev) 466 device_t dev; 467{ 468 int flags; 469 470 if (resource_int_value("npx", 0, "flags", &flags) != 0) 471 flags = 0; 472 473 if (flags) 474 device_printf(dev, "flags 0x%x ", flags); 475 if (npx_irq13) { 476 device_printf(dev, "using IRQ 13 interface\n"); 477 } else { 478#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 479 if (npx_ex16) { 480 if (!(flags & NPX_PREFER_EMULATOR)) 481 device_printf(dev, "INT 16 interface\n"); 482 else { 483 device_printf(dev, "FPU exists, but flags request " 484 "emulator\n"); 485 hw_float = npx_exists = 0; 486 } 487 } else if (npx_exists) { 488 device_printf(dev, "error reporting broken; using 387 emulator\n"); 489 hw_float = npx_exists = 0; 490 } else 491 device_printf(dev, "387 emulator\n"); 492#else 493 if (npx_ex16) { 494 device_printf(dev, "INT 16 interface\n"); 495 if (flags & NPX_PREFER_EMULATOR) { 496 device_printf(dev, "emulator requested, but none compiled " 497 "into kernel, using FPU\n"); 498 } 499 } else 500 device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); 501#endif 502 } 503 npxinit(__INITIAL_NPXCW__); 504 505#ifdef I586_CPU_XXX 506 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 507 timezero("i586_bzero()", i586_bzero) < 508 timezero("bzero()", bzero) * 4 / 5) { 509 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 510 bcopy_vector = i586_bcopy; 511 ovbcopy_vector = i586_bcopy; 512 } 513 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 514 bzero = i586_bzero; 515 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 516 copyin_vector = i586_copyin; 517 copyout_vector = i586_copyout; 518 } 519 } 520#endif 521 522 return (0); /* XXX unused */ 523} 524 525/* 526 * Initialize floating point unit. 527 */ 528void 529npxinit(control) 530 u_short control; 531{ 532 struct save87 dummy; 533 critical_t savecrit; 534 535 if (!npx_exists) 536 return; 537 /* 538 * fninit has the same h/w bugs as fnsave. Use the detoxified 539 * fnsave to throw away any junk in the fpu. npxsave() initializes 540 * the fpu and sets npxproc = NULL as important side effects. 541 */ 542 savecrit = critical_enter(); 543 npxsave(&dummy); 544 stop_emulating(); 545 fldcw(&control); 546 if (PCPU_GET(curpcb) != NULL) 547 fnsave(&PCPU_GET(curpcb)->pcb_savefpu); 548 start_emulating(); 549 critical_exit(savecrit); 550} 551 552/* 553 * Free coprocessor (if we have it). 554 */ 555void 556npxexit(p) 557 struct proc *p; 558{ 559 critical_t savecrit; 560 561 savecrit = critical_enter(); 562 if (p == PCPU_GET(npxproc)) 563 npxsave(&PCPU_GET(curpcb)->pcb_savefpu); 564 critical_exit(savecrit); 565#ifdef NPX_DEBUG 566 if (npx_exists) { 567 u_int masked_exceptions; 568 569 masked_exceptions = PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_cw 570 & PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_sw & 0x7f; 571 /* 572 * Log exceptions that would have trapped with the old 573 * control word (overflow, divide by 0, and invalid operand). 574 */ 575 if (masked_exceptions & 0x0d) 576 log(LOG_ERR, 577 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 578 p->p_pid, p->p_comm, masked_exceptions); 579 } 580#endif 581} 582 583/* 584 * The following mechanism is used to ensure that the FPE_... value 585 * that is passed as a trapcode to the signal handler of the user 586 * process does not have more than one bit set. 587 * 588 * Multiple bits may be set if the user process modifies the control 589 * word while a status word bit is already set. While this is a sign 590 * of bad coding, we have no choise than to narrow them down to one 591 * bit, since we must not send a trapcode that is not exactly one of 592 * the FPE_ macros. 593 * 594 * The mechanism has a static table with 127 entries. Each combination 595 * of the 7 FPU status word exception bits directly translates to a 596 * position in this table, where a single FPE_... value is stored. 597 * This FPE_... value stored there is considered the "most important" 598 * of the exception bits and will be sent as the signal code. The 599 * precedence of the bits is based upon Intel Document "Numerical 600 * Applications", Chapter "Special Computational Situations". 601 * 602 * The macro to choose one of these values does these steps: 1) Throw 603 * away status word bits that cannot be masked. 2) Throw away the bits 604 * currently masked in the control word, assuming the user isn't 605 * interested in them anymore. 3) Reinsert status word bit 7 (stack 606 * fault) if it is set, which cannot be masked but must be presered. 607 * 4) Use the remaining bits to point into the trapcode table. 608 * 609 * The 6 maskable bits in order of their preference, as stated in the 610 * above referenced Intel manual: 611 * 1 Invalid operation (FP_X_INV) 612 * 1a Stack underflow 613 * 1b Stack overflow 614 * 1c Operand of unsupported format 615 * 1d SNaN operand. 616 * 2 QNaN operand (not an exception, irrelavant here) 617 * 3 Any other invalid-operation not mentioned above or zero divide 618 * (FP_X_INV, FP_X_DZ) 619 * 4 Denormal operand (FP_X_DNML) 620 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 621 * 6 Inexact result (FP_X_IMP) 622 */ 623static char fpetable[128] = { 624 0, 625 FPE_FLTINV, /* 1 - INV */ 626 FPE_FLTUND, /* 2 - DNML */ 627 FPE_FLTINV, /* 3 - INV | DNML */ 628 FPE_FLTDIV, /* 4 - DZ */ 629 FPE_FLTINV, /* 5 - INV | DZ */ 630 FPE_FLTDIV, /* 6 - DNML | DZ */ 631 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 632 FPE_FLTOVF, /* 8 - OFL */ 633 FPE_FLTINV, /* 9 - INV | OFL */ 634 FPE_FLTUND, /* A - DNML | OFL */ 635 FPE_FLTINV, /* B - INV | DNML | OFL */ 636 FPE_FLTDIV, /* C - DZ | OFL */ 637 FPE_FLTINV, /* D - INV | DZ | OFL */ 638 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 639 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 640 FPE_FLTUND, /* 10 - UFL */ 641 FPE_FLTINV, /* 11 - INV | UFL */ 642 FPE_FLTUND, /* 12 - DNML | UFL */ 643 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 644 FPE_FLTDIV, /* 14 - DZ | UFL */ 645 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 646 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 647 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 648 FPE_FLTOVF, /* 18 - OFL | UFL */ 649 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 650 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 651 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 652 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 653 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 654 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 655 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 656 FPE_FLTRES, /* 20 - IMP */ 657 FPE_FLTINV, /* 21 - INV | IMP */ 658 FPE_FLTUND, /* 22 - DNML | IMP */ 659 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 660 FPE_FLTDIV, /* 24 - DZ | IMP */ 661 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 662 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 663 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 664 FPE_FLTOVF, /* 28 - OFL | IMP */ 665 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 666 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 667 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 668 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 669 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 670 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 671 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 672 FPE_FLTUND, /* 30 - UFL | IMP */ 673 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 674 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 675 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 676 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 677 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 678 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 679 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 680 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 681 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 682 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 683 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 684 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 685 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 686 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 687 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 688 FPE_FLTSUB, /* 40 - STK */ 689 FPE_FLTSUB, /* 41 - INV | STK */ 690 FPE_FLTUND, /* 42 - DNML | STK */ 691 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 692 FPE_FLTDIV, /* 44 - DZ | STK */ 693 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 694 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 695 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 696 FPE_FLTOVF, /* 48 - OFL | STK */ 697 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 698 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 699 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 700 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 701 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 702 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 703 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 704 FPE_FLTUND, /* 50 - UFL | STK */ 705 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 706 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 707 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 708 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 709 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 710 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 711 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 712 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 713 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 714 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 715 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 716 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 717 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 718 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 719 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 720 FPE_FLTRES, /* 60 - IMP | STK */ 721 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 722 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 723 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 724 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 725 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 726 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 727 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 728 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 729 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 730 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 731 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 732 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 733 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 734 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 735 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 736 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 737 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 738 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 739 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 740 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 741 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 742 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 743 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 744 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 745 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 746 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 747 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 748 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 749 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 750 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 751 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 752}; 753 754/* 755 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 756 * 757 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 758 * depend on longjmp() restoring a usable state. Restoring the state 759 * or examining it might fail if we didn't clear exceptions. 760 * 761 * The error code chosen will be one of the FPE_... macros. It will be 762 * sent as the second argument to old BSD-style signal handlers and as 763 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 764 * 765 * XXX the FP state is not preserved across signal handlers. So signal 766 * handlers cannot afford to do FP unless they preserve the state or 767 * longjmp() out. Both preserving the state and longjmp()ing may be 768 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 769 * solution for signals other than SIGFPE. 770 */ 771int 772npxtrap() 773{ 774 critical_t savecrit; 775 u_short control, status; 776 777 if (!npx_exists) { 778 printf("npxtrap: npxproc = %p, curproc = %p, npx_exists = %d\n", 779 PCPU_GET(npxproc), curproc, npx_exists); 780 panic("npxtrap from nowhere"); 781 } 782 savecrit = critical_enter(); 783 784 /* 785 * Interrupt handling (for another interrupt) may have pushed the 786 * state to memory. Fetch the relevant parts of the state from 787 * wherever they are. 788 */ 789 if (PCPU_GET(npxproc) != curproc) { 790 control = curproc->p_addr->u_pcb.pcb_savefpu.sv_env.en_cw; 791 status = curproc->p_addr->u_pcb.pcb_savefpu.sv_env.en_sw; 792 } else { 793 fnstcw(&control); 794 fnstsw(&status); 795 } 796 797 curproc->p_addr->u_pcb.pcb_savefpu.sv_ex_sw = status; 798 if (PCPU_GET(npxproc) != curproc) 799 curproc->p_addr->u_pcb.pcb_savefpu.sv_env.en_sw &= ~0x80bf; 800 else 801 fnclex(); 802 critical_exit(savecrit); 803 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 804} 805 806/* 807 * Implement device not available (DNA) exception 808 * 809 * It would be better to switch FP context here (if curproc != npxproc) 810 * and not necessarily for every context switch, but it is too hard to 811 * access foreign pcb's. 812 */ 813int 814npxdna() 815{ 816 critical_t s; 817 818 if (!npx_exists) 819 return (0); 820 if (PCPU_GET(npxproc) != NULL) { 821 printf("npxdna: npxproc = %p, curproc = %p\n", 822 PCPU_GET(npxproc), curproc); 823 panic("npxdna"); 824 } 825 s = critical_enter(); 826 stop_emulating(); 827 /* 828 * Record new context early in case frstor causes an IRQ13. 829 */ 830 PCPU_SET(npxproc, CURPROC); 831 PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw = 0; 832 /* 833 * The following frstor may cause an IRQ13 when the state being 834 * restored has a pending error. The error will appear to have been 835 * triggered by the current (npx) user instruction even when that 836 * instruction is a no-wait instruction that should not trigger an 837 * error (e.g., fnclex). On at least one 486 system all of the 838 * no-wait instructions are broken the same as frstor, so our 839 * treatment does not amplify the breakage. On at least one 840 * 386/Cyrix 387 system, fnclex works correctly while frstor and 841 * fnsave are broken, so our treatment breaks fnclex if it is the 842 * first FPU instruction after a context switch. 843 */ 844 frstor(&PCPU_GET(curpcb)->pcb_savefpu); 845 critical_exit(s); 846 847 return (1); 848} 849 850/* 851 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 852 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 853 * no-wait npx instructions. See the Intel application note AP-578 for 854 * details. This doesn't cause any additional complications here. IRQ13's 855 * are inherently asynchronous unless the CPU is frozen to deliver them -- 856 * one that started in userland may be delivered many instructions later, 857 * after the process has entered the kernel. It may even be delivered after 858 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 859 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 860 * it is normally ignored at first because we set npxproc to NULL; it is 861 * normally retriggered in npxdna() after return to user mode. 862 * 863 * npxsave() must be called with interrupts disabled, so that it clears 864 * npxproc atomically with saving the state. We require callers to do the 865 * disabling, since most callers need to disable interrupts anyway to call 866 * npxsave() atomically with checking npxproc. 867 * 868 * A previous version of npxsave() went to great lengths to excecute fnsave 869 * with interrupts enabled in case executing it froze the CPU. This case 870 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 871 * spurious freezes. 872 */ 873void 874npxsave(addr) 875 struct save87 *addr; 876{ 877 878 stop_emulating(); 879 fnsave(addr); 880 start_emulating(); 881 PCPU_SET(npxproc, NULL); 882} 883 884#ifdef I586_CPU_XXX 885static long 886timezero(funcname, func) 887 const char *funcname; 888 void (*func) __P((void *buf, size_t len)); 889 890{ 891 void *buf; 892#define BUFSIZE 1048576 893 long usec; 894 struct timeval finish, start; 895 896 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 897 if (buf == NULL) 898 return (BUFSIZE); 899 microtime(&start); 900 (*func)(buf, BUFSIZE); 901 microtime(&finish); 902 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 903 finish.tv_usec - start.tv_usec; 904 if (usec <= 0) 905 usec = 1; 906 if (bootverbose) 907 printf("%s bandwidth = %u kBps\n", funcname, 908 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 909 free(buf, M_TEMP); 910 return (usec); 911} 912#endif /* I586_CPU */ 913 914static device_method_t npx_methods[] = { 915 /* Device interface */ 916 DEVMETHOD(device_identify, npx_identify), 917 DEVMETHOD(device_probe, npx_probe), 918 DEVMETHOD(device_attach, npx_attach), 919 DEVMETHOD(device_detach, bus_generic_detach), 920 DEVMETHOD(device_shutdown, bus_generic_shutdown), 921 DEVMETHOD(device_suspend, bus_generic_suspend), 922 DEVMETHOD(device_resume, bus_generic_resume), 923 924 { 0, 0 } 925}; 926 927static driver_t npx_driver = { 928 "npx", 929 npx_methods, 930 1, /* no softc */ 931}; 932 933static devclass_t npx_devclass; 934 935/* 936 * We prefer to attach to the root nexus so that the usual case (exception 16) 937 * doesn't describe the processor as being `on isa'. 938 */ 939DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 940 941/* 942 * This sucks up the legacy ISA support assignments from PNPBIOS. 943 */ 944static struct isa_pnp_id npxisa_ids[] = { 945 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 946 { 0 } 947}; 948 949static int 950npxisa_probe(device_t dev) 951{ 952 int result; 953 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 954 device_quiet(dev); 955 } 956 return(result); 957} 958 959static int 960npxisa_attach(device_t dev) 961{ 962 return (0); 963} 964 965static device_method_t npxisa_methods[] = { 966 /* Device interface */ 967 DEVMETHOD(device_probe, npxisa_probe), 968 DEVMETHOD(device_attach, npxisa_attach), 969 DEVMETHOD(device_detach, bus_generic_detach), 970 DEVMETHOD(device_shutdown, bus_generic_shutdown), 971 DEVMETHOD(device_suspend, bus_generic_suspend), 972 DEVMETHOD(device_resume, bus_generic_resume), 973 974 { 0, 0 } 975}; 976 977static driver_t npxisa_driver = { 978 "npxisa", 979 npxisa_methods, 980 1, /* no softc */ 981}; 982 983static devclass_t npxisa_devclass; 984 985DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 986 987