npx.c revision 49081
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $Id: npx.c,v 1.73 1999/05/15 17:58:58 peter Exp $ 36 */ 37 38#include "npx.h" 39#if NNPX > 0 40 41#include "opt_debug_npx.h" 42#include "opt_math_emulate.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/kernel.h> 48#include <sys/malloc.h> 49#include <sys/module.h> 50#include <sys/sysctl.h> 51#include <sys/proc.h> 52#include <machine/bus.h> 53#include <sys/rman.h> 54#ifdef NPX_DEBUG 55#include <sys/syslog.h> 56#endif 57#include <sys/signalvar.h> 58 59#ifndef SMP 60#include <machine/asmacros.h> 61#endif 62#include <machine/cputypes.h> 63#include <machine/frame.h> 64#include <machine/ipl.h> 65#include <machine/md_var.h> 66#include <machine/pcb.h> 67#include <machine/psl.h> 68#ifndef SMP 69#include <machine/clock.h> 70#endif 71#include <machine/resource.h> 72#include <machine/specialreg.h> 73#include <machine/segments.h> 74 75#ifndef SMP 76#include <i386/isa/icu.h> 77#include <i386/isa/intr_machdep.h> 78#include <i386/isa/isa.h> 79#endif 80 81/* 82 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 83 */ 84 85/* Configuration flags. */ 86#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 87#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 88#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 89#define NPX_PREFER_EMULATOR (1 << 3) 90 91#ifdef __GNUC__ 92 93#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 94#define fnclex() __asm("fnclex") 95#define fninit() __asm("fninit") 96#define fnop() __asm("fnop") 97#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 98#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 99#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 100#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 101#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 102#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 103 : : "n" (CR0_TS) : "ax") 104#define stop_emulating() __asm("clts") 105 106#else /* not __GNUC__ */ 107 108void fldcw __P((caddr_t addr)); 109void fnclex __P((void)); 110void fninit __P((void)); 111void fnop __P((void)); 112void fnsave __P((caddr_t addr)); 113void fnstcw __P((caddr_t addr)); 114void fnstsw __P((caddr_t addr)); 115void fp_divide_by_0 __P((void)); 116void frstor __P((caddr_t addr)); 117void start_emulating __P((void)); 118void stop_emulating __P((void)); 119 120#endif /* __GNUC__ */ 121 122typedef u_char bool_t; 123 124static int npx_attach __P((device_t dev)); 125 void npx_intr __P((void *)); 126static int npx_probe __P((device_t dev)); 127static int npx_probe1 __P((device_t dev)); 128#ifdef I586_CPU 129static long timezero __P((const char *funcname, 130 void (*func)(void *buf, size_t len))); 131#endif /* I586_CPU */ 132 133int hw_float; /* XXX currently just alias for npx_exists */ 134 135SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 136 CTLFLAG_RD, &hw_float, 0, 137 "Floatingpoint instructions executed in hardware"); 138 139#ifndef SMP 140static u_int npx0_imask = SWI_CLOCK_MASK; 141static struct gate_descriptor npx_idt_probeintr; 142static int npx_intrno; 143static volatile u_int npx_intrs_while_probing; 144static volatile u_int npx_traps_while_probing; 145#endif 146 147static bool_t npx_ex16; 148static bool_t npx_exists; 149static bool_t npx_irq13; 150static int npx_irq; /* irq number */ 151 152#ifndef SMP 153/* 154 * Special interrupt handlers. Someday intr0-intr15 will be used to count 155 * interrupts. We'll still need a special exception 16 handler. The busy 156 * latch stuff in probeintr() can be moved to npxprobe(). 157 */ 158inthand_t probeintr; 159__asm(" \n\ 160 .text \n\ 161 .p2align 2,0x90 \n\ 162 .type " __XSTRING(CNAME(probeintr)) ",@function \n\ 163" __XSTRING(CNAME(probeintr)) ": \n\ 164 ss \n\ 165 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\ 166 pushl %eax \n\ 167 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\ 168 outb %al,$0xa0 # IO_ICU2 \n\ 169 outb %al,$0x20 # IO_ICU1 \n\ 170 movb $0,%al \n\ 171 outb %al,$0xf0 # clear BUSY# latch \n\ 172 popl %eax \n\ 173 iret \n\ 174"); 175 176inthand_t probetrap; 177__asm(" \n\ 178 .text \n\ 179 .p2align 2,0x90 \n\ 180 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 181" __XSTRING(CNAME(probetrap)) ": \n\ 182 ss \n\ 183 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 184 fnclex \n\ 185 iret \n\ 186"); 187#endif /* SMP */ 188 189/* 190 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 191 * whether the device exists or not (XXX should be elsewhere). Set flags 192 * to tell npxattach() what to do. Modify device struct if npx doesn't 193 * need to use interrupts. Return 1 if device exists. 194 */ 195static int 196npx_probe(dev) 197 device_t dev; 198{ 199#ifdef SMP 200 201 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 202 npx_irq = 13; 203 return npx_probe1(dev); 204 205#else /* SMP */ 206 207 int result; 208 u_long save_eflags; 209 u_char save_icu1_mask; 210 u_char save_icu2_mask; 211 struct gate_descriptor save_idt_npxintr; 212 struct gate_descriptor save_idt_npxtrap; 213 /* 214 * This routine is now just a wrapper for npxprobe1(), to install 215 * special npx interrupt and trap handlers, to enable npx interrupts 216 * and to disable other interrupts. Someday isa_configure() will 217 * install suitable handlers and run with interrupts enabled so we 218 * won't need to do so much here. 219 */ 220 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 221 npx_irq = 13; 222 npx_intrno = NRSVIDT + npx_irq; 223 save_eflags = read_eflags(); 224 disable_intr(); 225 save_icu1_mask = inb(IO_ICU1 + 1); 226 save_icu2_mask = inb(IO_ICU2 + 1); 227 save_idt_npxintr = idt[npx_intrno]; 228 save_idt_npxtrap = idt[16]; 229 outb(IO_ICU1 + 1, ~IRQ_SLAVE); 230 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8))); 231 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 232 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 233 npx_idt_probeintr = idt[npx_intrno]; 234 enable_intr(); 235 result = npx_probe1(dev); 236 disable_intr(); 237 outb(IO_ICU1 + 1, save_icu1_mask); 238 outb(IO_ICU2 + 1, save_icu2_mask); 239 idt[npx_intrno] = save_idt_npxintr; 240 idt[16] = save_idt_npxtrap; 241 write_eflags(save_eflags); 242 return (result); 243 244#endif /* SMP */ 245} 246 247static int 248npx_probe1(dev) 249 device_t dev; 250{ 251#ifndef SMP 252 u_short control; 253 u_short status; 254#endif 255 256 /* 257 * Partially reset the coprocessor, if any. Some BIOS's don't reset 258 * it after a warm boot. 259 */ 260 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 261 outb(0xf0, 0); /* clear BUSY# latch */ 262 /* 263 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 264 * instructions. We must set the CR0_MP bit and use the CR0_TS 265 * bit to control the trap, because setting the CR0_EM bit does 266 * not cause WAIT instructions to trap. It's important to trap 267 * WAIT instructions - otherwise the "wait" variants of no-wait 268 * control instructions would degenerate to the "no-wait" variants 269 * after FP context switches but work correctly otherwise. It's 270 * particularly important to trap WAITs when there is no NPX - 271 * otherwise the "wait" variants would always degenerate. 272 * 273 * Try setting CR0_NE to get correct error reporting on 486DX's. 274 * Setting it should fail or do nothing on lesser processors. 275 */ 276 load_cr0(rcr0() | CR0_MP | CR0_NE); 277 /* 278 * But don't trap while we're probing. 279 */ 280 stop_emulating(); 281 /* 282 * Finish resetting the coprocessor, if any. If there is an error 283 * pending, then we may get a bogus IRQ13, but probeintr() will handle 284 * it OK. Bogus halts have never been observed, but we enabled 285 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 286 */ 287 fninit(); 288 289#ifdef SMP 290 /* 291 * Exception 16 MUST work for SMP. 292 */ 293 npx_irq13 = 0; 294 npx_ex16 = hw_float = npx_exists = 1; 295 device_set_desc(dev, "math processor"); 296 return (0); 297 298#else /* !SMP */ 299 device_set_desc(dev, "math processor"); 300 301 /* 302 * Don't use fwait here because it might hang. 303 * Don't use fnop here because it usually hangs if there is no FPU. 304 */ 305 DELAY(1000); /* wait for any IRQ13 */ 306#ifdef DIAGNOSTIC 307 if (npx_intrs_while_probing != 0) 308 printf("fninit caused %u bogus npx interrupt(s)\n", 309 npx_intrs_while_probing); 310 if (npx_traps_while_probing != 0) 311 printf("fninit caused %u bogus npx trap(s)\n", 312 npx_traps_while_probing); 313#endif 314 /* 315 * Check for a status of mostly zero. 316 */ 317 status = 0x5a5a; 318 fnstsw(&status); 319 if ((status & 0xb8ff) == 0) { 320 /* 321 * Good, now check for a proper control word. 322 */ 323 control = 0x5a5a; 324 fnstcw(&control); 325 if ((control & 0x1f3f) == 0x033f) { 326 hw_float = npx_exists = 1; 327 /* 328 * We have an npx, now divide by 0 to see if exception 329 * 16 works. 330 */ 331 control &= ~(1 << 2); /* enable divide by 0 trap */ 332 fldcw(&control); 333 npx_traps_while_probing = npx_intrs_while_probing = 0; 334 fp_divide_by_0(); 335 if (npx_traps_while_probing != 0) { 336 /* 337 * Good, exception 16 works. 338 */ 339 npx_ex16 = 1; 340 return (0); 341 } 342 if (npx_intrs_while_probing != 0) { 343 int rid; 344 struct resource *r; 345 void *intr; 346 /* 347 * Bad, we are stuck with IRQ13. 348 */ 349 npx_irq13 = 1; 350 /* 351 * npxattach would be too late to set npx0_imask 352 */ 353 npx0_imask |= (1 << npx_irq); 354 355 /* 356 * We allocate these resources permanently, 357 * so there is no need to keep track of them. 358 */ 359 rid = 0; 360 r = bus_alloc_resource(dev, SYS_RES_IOPORT, 361 &rid, IO_NPX, IO_NPX, 362 IO_NPXSIZE, RF_ACTIVE); 363 if (r == 0) 364 panic("npx: can't get ports"); 365 rid = 0; 366 r = bus_alloc_resource(dev, SYS_RES_IRQ, 367 &rid, npx_irq, npx_irq, 368 1, RF_ACTIVE); 369 if (r == 0) 370 panic("npx: can't get IRQ"); 371 BUS_SETUP_INTR(device_get_parent(dev), 372 dev, r, INTR_TYPE_MISC, 373 npx_intr, 0, &intr); 374 if (intr == 0) 375 panic("npx: can't create intr"); 376 377 return (0); 378 } 379 /* 380 * Worse, even IRQ13 is broken. Use emulator. 381 */ 382 } 383 } 384 /* 385 * Probe failed, but we want to get to npxattach to initialize the 386 * emulator and say that it has been installed. XXX handle devices 387 * that aren't really devices better. 388 */ 389 return (0); 390#endif /* SMP */ 391} 392 393/* 394 * Attach routine - announce which it is, and wire into system 395 */ 396int 397npx_attach(dev) 398 device_t dev; 399{ 400 int flags; 401 402 if (resource_int_value("npx", 0, "flags", &flags) != 0) 403 flags = 0; 404 405 device_print_prettyname(dev); 406 if (npx_irq13) { 407 printf("using IRQ 13 interface\n"); 408 } else { 409#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 410 if (npx_ex16) { 411 if (!(flags & NPX_PREFER_EMULATOR)) 412 printf("INT 16 interface\n"); 413 else { 414 printf("FPU exists, but flags request " 415 "emulator\n"); 416 hw_float = npx_exists = 0; 417 } 418 } else if (npx_exists) { 419 printf("error reporting broken; using 387 emulator\n"); 420 hw_float = npx_exists = 0; 421 } else 422 printf("387 emulator\n"); 423#else 424 if (npx_ex16) { 425 printf("INT 16 interface\n"); 426 if (flags & NPX_PREFER_EMULATOR) { 427 printf("emulator requested, but none compiled " 428 "into kernel, using FPU\n"); 429 } 430 } else 431 printf("no 387 emulator in kernel and no FPU!\n"); 432#endif 433 } 434 npxinit(__INITIAL_NPXCW__); 435 436#ifdef I586_CPU 437 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 438 timezero("i586_bzero()", i586_bzero) < 439 timezero("bzero()", bzero) * 4 / 5) { 440 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 441 bcopy_vector = i586_bcopy; 442 ovbcopy_vector = i586_bcopy; 443 } 444 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 445 bzero = i586_bzero; 446 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 447 copyin_vector = i586_copyin; 448 copyout_vector = i586_copyout; 449 } 450 } 451#endif 452 453 return (0); /* XXX unused */ 454} 455 456/* 457 * Initialize floating point unit. 458 */ 459void 460npxinit(control) 461 u_short control; 462{ 463 struct save87 dummy; 464 465 if (!npx_exists) 466 return; 467 /* 468 * fninit has the same h/w bugs as fnsave. Use the detoxified 469 * fnsave to throw away any junk in the fpu. npxsave() initializes 470 * the fpu and sets npxproc = NULL as important side effects. 471 */ 472 npxsave(&dummy); 473 stop_emulating(); 474 fldcw(&control); 475 if (curpcb != NULL) 476 fnsave(&curpcb->pcb_savefpu); 477 start_emulating(); 478} 479 480/* 481 * Free coprocessor (if we have it). 482 */ 483void 484npxexit(p) 485 struct proc *p; 486{ 487 488 if (p == npxproc) 489 npxsave(&curpcb->pcb_savefpu); 490#ifdef NPX_DEBUG 491 if (npx_exists) { 492 u_int masked_exceptions; 493 494 masked_exceptions = curpcb->pcb_savefpu.sv_env.en_cw 495 & curpcb->pcb_savefpu.sv_env.en_sw & 0x7f; 496 /* 497 * Log exceptions that would have trapped with the old 498 * control word (overflow, divide by 0, and invalid operand). 499 */ 500 if (masked_exceptions & 0x0d) 501 log(LOG_ERR, 502 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 503 p->p_pid, p->p_comm, masked_exceptions); 504 } 505#endif 506} 507 508/* 509 * The following mechanism is used to ensure that the FPE_... value 510 * that is passed as a trapcode to the signal handler of the user 511 * process does not have more than one bit set. 512 * 513 * Multiple bits may be set if the user process modifies the control 514 * word while a status word bit is already set. While this is a sign 515 * of bad coding, we have no choise than to narrow them down to one 516 * bit, since we must not send a trapcode that is not exactly one of 517 * the FPE_ macros. 518 * 519 * The mechanism has a static table with 127 entries. Each combination 520 * of the 7 FPU status word exception bits directly translates to a 521 * position in this table, where a single FPE_... value is stored. 522 * This FPE_... value stored there is considered the "most important" 523 * of the exception bits and will be sent as the signal code. The 524 * precedence of the bits is based upon Intel Document "Numerical 525 * Applications", Chapter "Special Computational Situations". 526 * 527 * The macro to choose one of these values does these steps: 1) Throw 528 * away status word bits that cannot be masked. 2) Throw away the bits 529 * currently masked in the control word, assuming the user isn't 530 * interested in them anymore. 3) Reinsert status word bit 7 (stack 531 * fault) if it is set, which cannot be masked but must be presered. 532 * 4) Use the remaining bits to point into the trapcode table. 533 * 534 * The 6 maskable bits in order of their preference, as stated in the 535 * above referenced Intel manual: 536 * 1 Invalid operation (FP_X_INV) 537 * 1a Stack underflow 538 * 1b Stack overflow 539 * 1c Operand of unsupported format 540 * 1d SNaN operand. 541 * 2 QNaN operand (not an exception, irrelavant here) 542 * 3 Any other invalid-operation not mentioned above or zero divide 543 * (FP_X_INV, FP_X_DZ) 544 * 4 Denormal operand (FP_X_DNML) 545 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 546 * 6 Inexact result (FP_X_IMP) */ 547 548static char fpetable[128] = { 549 0, 550 FPE_FLTINV, /* 1 - INV */ 551 FPE_FLTUND, /* 2 - DNML */ 552 FPE_FLTINV, /* 3 - INV | DNML */ 553 FPE_FLTDIV, /* 4 - DZ */ 554 FPE_FLTINV, /* 5 - INV | DZ */ 555 FPE_FLTDIV, /* 6 - DNML | DZ */ 556 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 557 FPE_FLTOVF, /* 8 - OFL */ 558 FPE_FLTINV, /* 9 - INV | OFL */ 559 FPE_FLTUND, /* A - DNML | OFL */ 560 FPE_FLTINV, /* B - INV | DNML | OFL */ 561 FPE_FLTDIV, /* C - DZ | OFL */ 562 FPE_FLTINV, /* D - INV | DZ | OFL */ 563 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 564 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 565 FPE_FLTUND, /* 10 - UFL */ 566 FPE_FLTINV, /* 11 - INV | UFL */ 567 FPE_FLTUND, /* 12 - DNML | UFL */ 568 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 569 FPE_FLTDIV, /* 14 - DZ | UFL */ 570 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 571 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 572 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 573 FPE_FLTOVF, /* 18 - OFL | UFL */ 574 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 575 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 576 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 577 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 578 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 579 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 580 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 581 FPE_FLTRES, /* 20 - IMP */ 582 FPE_FLTINV, /* 21 - INV | IMP */ 583 FPE_FLTUND, /* 22 - DNML | IMP */ 584 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 585 FPE_FLTDIV, /* 24 - DZ | IMP */ 586 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 587 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 588 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 589 FPE_FLTOVF, /* 28 - OFL | IMP */ 590 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 591 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 592 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 593 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 594 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 595 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 596 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 597 FPE_FLTUND, /* 30 - UFL | IMP */ 598 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 599 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 600 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 601 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 602 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 603 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 604 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 605 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 606 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 607 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 608 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 609 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 610 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 611 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 612 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 613 FPE_FLTSUB, /* 40 - STK */ 614 FPE_FLTSUB, /* 41 - INV | STK */ 615 FPE_FLTUND, /* 42 - DNML | STK */ 616 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 617 FPE_FLTDIV, /* 44 - DZ | STK */ 618 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 619 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 620 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 621 FPE_FLTOVF, /* 48 - OFL | STK */ 622 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 623 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 624 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 625 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 626 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 627 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 628 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 629 FPE_FLTUND, /* 50 - UFL | STK */ 630 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 631 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 632 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 633 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 634 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 635 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 636 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 637 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 638 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 639 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 640 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 641 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 642 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 643 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 644 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 645 FPE_FLTRES, /* 60 - IMP | STK */ 646 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 647 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 648 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 649 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 650 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 651 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 652 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 653 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 654 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 655 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 656 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 657 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 658 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 659 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 660 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 661 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 662 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 663 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 664 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 665 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 666 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 667 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 668 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 669 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 670 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 671 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 672 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 673 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 674 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 675 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 676 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 677}; 678 679#define ENCODE(_sw, _cw) (fpetable[(_sw & ~_cw & 0x3f) | (_sw & 0x40)]) 680 681/* 682 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 683 * 684 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 685 * depend on longjmp() restoring a usable state. Restoring the state 686 * or examining it might fail if we didn't clear exceptions. 687 * 688 * The error code chosen will be one of the FPE_... macros. It will be 689 * sent as the second argument to old BSD-style signal handlers and as 690 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 691 * 692 * XXX the FP state is not preserved across signal handlers. So signal 693 * handlers cannot afford to do FP unless they preserve the state or 694 * longjmp() out. Both preserving the state and longjmp()ing may be 695 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 696 * solution for signals other than SIGFPE. 697 */ 698void 699npx_intr(dummy) 700 void *dummy; 701{ 702 int code; 703 u_long cw; 704 struct intrframe *frame; 705 706 if (npxproc == NULL || !npx_exists) { 707 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 708 npxproc, curproc, npx_exists); 709 panic("npxintr from nowhere"); 710 } 711 if (npxproc != curproc) { 712 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 713 npxproc, curproc, npx_exists); 714 panic("npxintr from non-current process"); 715 } 716 717 outb(0xf0, 0); 718 fnstsw(&curpcb->pcb_savefpu.sv_ex_sw); 719 fnstcw(&cw); 720 fnclex(); 721 722 /* 723 * Pass exception to process. 724 */ 725 frame = (struct intrframe *)&dummy; /* XXX */ 726 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) { 727 /* 728 * Interrupt is essentially a trap, so we can afford to call 729 * the SIGFPE handler (if any) as soon as the interrupt 730 * returns. 731 * 732 * XXX little or nothing is gained from this, and plenty is 733 * lost - the interrupt frame has to contain the trap frame 734 * (this is otherwise only necessary for the rescheduling trap 735 * in doreti, and the frame for that could easily be set up 736 * just before it is used). 737 */ 738 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame); 739 /* 740 * Encode the appropriate code for detailed information on 741 * this exception. 742 */ 743 code = ENCODE(curpcb->pcb_savefpu.sv_ex_sw, cw); 744 trapsignal(curproc, SIGFPE, code); 745 } else { 746 /* 747 * Nested interrupt. These losers occur when: 748 * o an IRQ13 is bogusly generated at a bogus time, e.g.: 749 * o immediately after an fnsave or frstor of an 750 * error state. 751 * o a couple of 386 instructions after 752 * "fstpl _memvar" causes a stack overflow. 753 * These are especially nasty when combined with a 754 * trace trap. 755 * o an IRQ13 occurs at the same time as another higher- 756 * priority interrupt. 757 * 758 * Treat them like a true async interrupt. 759 */ 760 psignal(curproc, SIGFPE); 761 } 762} 763 764/* 765 * Implement device not available (DNA) exception 766 * 767 * It would be better to switch FP context here (if curproc != npxproc) 768 * and not necessarily for every context switch, but it is too hard to 769 * access foreign pcb's. 770 */ 771int 772npxdna() 773{ 774 if (!npx_exists) 775 return (0); 776 if (npxproc != NULL) { 777 printf("npxdna: npxproc = %p, curproc = %p\n", 778 npxproc, curproc); 779 panic("npxdna"); 780 } 781 stop_emulating(); 782 /* 783 * Record new context early in case frstor causes an IRQ13. 784 */ 785 npxproc = curproc; 786 curpcb->pcb_savefpu.sv_ex_sw = 0; 787 /* 788 * The following frstor may cause an IRQ13 when the state being 789 * restored has a pending error. The error will appear to have been 790 * triggered by the current (npx) user instruction even when that 791 * instruction is a no-wait instruction that should not trigger an 792 * error (e.g., fnclex). On at least one 486 system all of the 793 * no-wait instructions are broken the same as frstor, so our 794 * treatment does not amplify the breakage. On at least one 795 * 386/Cyrix 387 system, fnclex works correctly while frstor and 796 * fnsave are broken, so our treatment breaks fnclex if it is the 797 * first FPU instruction after a context switch. 798 */ 799 frstor(&curpcb->pcb_savefpu); 800 801 return (1); 802} 803 804/* 805 * Wrapper for fnsave instruction to handle h/w bugs. If there is an error 806 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 807 * any IRQ13 to be handled immediately, and then ignore it. This routine is 808 * often called at splhigh so it must not use many system services. In 809 * particular, it's much easier to install a special handler than to 810 * guarantee that it's safe to use npxintr() and its supporting code. 811 */ 812void 813npxsave(addr) 814 struct save87 *addr; 815{ 816#ifdef SMP 817 818 stop_emulating(); 819 fnsave(addr); 820 /* fnop(); */ 821 start_emulating(); 822 npxproc = NULL; 823 824#else /* SMP */ 825 826 u_char icu1_mask; 827 u_char icu2_mask; 828 u_char old_icu1_mask; 829 u_char old_icu2_mask; 830 struct gate_descriptor save_idt_npxintr; 831 832 disable_intr(); 833 old_icu1_mask = inb(IO_ICU1 + 1); 834 old_icu2_mask = inb(IO_ICU2 + 1); 835 save_idt_npxintr = idt[npx_intrno]; 836 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask)); 837 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8)); 838 idt[npx_intrno] = npx_idt_probeintr; 839 enable_intr(); 840 stop_emulating(); 841 fnsave(addr); 842 fnop(); 843 start_emulating(); 844 npxproc = NULL; 845 disable_intr(); 846 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */ 847 icu2_mask = inb(IO_ICU2 + 1); 848 outb(IO_ICU1 + 1, 849 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask)); 850 outb(IO_ICU2 + 1, 851 (icu2_mask & ~(npx0_imask >> 8)) 852 | (old_icu2_mask & (npx0_imask >> 8))); 853 idt[npx_intrno] = save_idt_npxintr; 854 enable_intr(); /* back to usual state */ 855 856#endif /* SMP */ 857} 858 859#ifdef I586_CPU 860static long 861timezero(funcname, func) 862 const char *funcname; 863 void (*func) __P((void *buf, size_t len)); 864 865{ 866 void *buf; 867#define BUFSIZE 1000000 868 long usec; 869 struct timeval finish, start; 870 871 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 872 if (buf == NULL) 873 return (BUFSIZE); 874 microtime(&start); 875 (*func)(buf, BUFSIZE); 876 microtime(&finish); 877 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 878 finish.tv_usec - start.tv_usec; 879 if (usec <= 0) 880 usec = 1; 881 if (bootverbose) 882 printf("%s bandwidth = %ld bytes/sec\n", 883 funcname, (long)(BUFSIZE * (int64_t)1000000 / usec)); 884 free(buf, M_TEMP); 885 return (usec); 886} 887#endif /* I586_CPU */ 888 889static device_method_t npx_methods[] = { 890 /* Device interface */ 891 DEVMETHOD(device_probe, npx_probe), 892 DEVMETHOD(device_attach, npx_attach), 893 DEVMETHOD(device_detach, bus_generic_detach), 894 DEVMETHOD(device_shutdown, bus_generic_shutdown), 895 DEVMETHOD(device_suspend, bus_generic_suspend), 896 DEVMETHOD(device_resume, bus_generic_resume), 897 898 { 0, 0 } 899}; 900 901static driver_t npx_driver = { 902 "npx", 903 npx_methods, 904 1, /* no softc */ 905}; 906 907static devclass_t npx_devclass; 908 909/* 910 * We prefer to attach to the root nexus so that the usual case (exception 16) 911 * doesn't describe the processor as being `on isa'. 912 */ 913DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 914 915#endif /* NNPX > 0 */ 916