1121982Sjhb/*- 2121982Sjhb * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3121982Sjhb * All rights reserved. 4121982Sjhb * 5121982Sjhb * Redistribution and use in source and binary forms, with or without 6121982Sjhb * modification, are permitted provided that the following conditions 7121982Sjhb * are met: 8121982Sjhb * 1. Redistributions of source code must retain the above copyright 9121982Sjhb * notice, this list of conditions and the following disclaimer. 10121982Sjhb * 2. Redistributions in binary form must reproduce the above copyright 11121982Sjhb * notice, this list of conditions and the following disclaimer in the 12121982Sjhb * documentation and/or other materials provided with the distribution. 13121982Sjhb * 14121982Sjhb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15121982Sjhb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16121982Sjhb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17121982Sjhb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18121982Sjhb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19121982Sjhb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20121982Sjhb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21121982Sjhb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22121982Sjhb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23121982Sjhb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24121982Sjhb * SUCH DAMAGE. 25121982Sjhb * 26121982Sjhb * $FreeBSD: releng/11.0/sys/i386/include/intr_machdep.h 302895 2016-07-15 09:44:48Z royger $ 27121982Sjhb */ 28121982Sjhb 29121982Sjhb#ifndef __MACHINE_INTR_MACHDEP_H__ 30121982Sjhb#define __MACHINE_INTR_MACHDEP_H__ 31121982Sjhb 32121982Sjhb#ifdef _KERNEL 33121982Sjhb 34151979Sjhb/* 35151979Sjhb * The maximum number of I/O interrupts we allow. This number is rather 36151979Sjhb * arbitrary as it is just the maximum IRQ resource value. The interrupt 37151979Sjhb * source for a given IRQ maps that I/O interrupt to device interrupt 38151979Sjhb * source whether it be a pin on an interrupt controller or an MSI interrupt. 39151979Sjhb * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device 40151979Sjhb * interrupts allocate IDT vectors on demand. Currently we have 191 IDT 41151979Sjhb * vectors available for device interrupts. On many systems with I/O APICs, 42151979Sjhb * a lot of the IRQs are not used, so this number can be much larger than 43151979Sjhb * 191 and still be safe since only interrupt sources in actual use will 44151979Sjhb * allocate IDT vectors. 45151979Sjhb * 46164265Sjhb * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs. 47255040Sgibbs * IRQ values from 256 to 767 are used by MSI. When running under the Xen 48255040Sgibbs * Hypervisor, IRQ values from 768 to 4863 are available for binding to 49255040Sgibbs * event channel events. We leave 255 unused to avoid confusion since 255 is 50255040Sgibbs * used in PCI to indicate an invalid IRQ. 51151979Sjhb */ 52187880Sjeff#define NUM_MSI_INTS 512 53164265Sjhb#define FIRST_MSI_INT 256 54255040Sgibbs#ifdef XENHVM 55255040Sgibbs#include <xen/xen-os.h> 56288917Sroyger#include <xen/interface/event_channel.h> 57255040Sgibbs#define NUM_EVTCHN_INTS NR_EVENT_CHANNELS 58255040Sgibbs#define FIRST_EVTCHN_INT \ 59255040Sgibbs (FIRST_MSI_INT + NUM_MSI_INTS) 60255040Sgibbs#define LAST_EVTCHN_INT \ 61255040Sgibbs (FIRST_EVTCHN_INT + NUM_EVTCHN_INTS - 1) 62282274Sjhb#else /* !XENHVM */ 63255040Sgibbs#define NUM_EVTCHN_INTS 0 64255040Sgibbs#endif 65255040Sgibbs#define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS + NUM_EVTCHN_INTS) 66121982Sjhb 67151979Sjhb/* 68164265Sjhb * Default base address for MSI messages on x86 platforms. 69164265Sjhb */ 70164265Sjhb#define MSI_INTEL_ADDR_BASE 0xfee00000 71164265Sjhb 72164265Sjhb/* 73151979Sjhb * - 1 ??? dummy counter. 74151979Sjhb * - 2 counters for each I/O interrupt. 75151979Sjhb * - 1 counter for each CPU for lapic timer. 76234207Savg * - 9 counters for each CPU for IPI counters for SMP. 77151979Sjhb */ 78151979Sjhb#ifdef SMP 79234207Savg#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 9) * MAXCPU) 80163212Sjhb#else 81151979Sjhb#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1) 82151979Sjhb#endif 83151979Sjhb 84121982Sjhb#ifndef LOCORE 85121982Sjhb 86297399Skibtypedef void inthand_t(void); 87121982Sjhb 88121982Sjhb#define IDTVEC(name) __CONCAT(X,name) 89121982Sjhb 90121982Sjhbstruct intsrc; 91121982Sjhb 92121982Sjhb/* 93121982Sjhb * Methods that a PIC provides to mask/unmask a given interrupt source, 94121982Sjhb * "turn on" the interrupt on the CPU side by setting up an IDT entry, and 95121982Sjhb * return the vector associated with this source. 96121982Sjhb */ 97121982Sjhbstruct pic { 98121982Sjhb void (*pic_enable_source)(struct intsrc *); 99133017Sscottl void (*pic_disable_source)(struct intsrc *, int); 100121982Sjhb void (*pic_eoi_source)(struct intsrc *); 101121982Sjhb void (*pic_enable_intr)(struct intsrc *); 102169391Sjhb void (*pic_disable_intr)(struct intsrc *); 103121982Sjhb int (*pic_vector)(struct intsrc *); 104121982Sjhb int (*pic_source_pending)(struct intsrc *); 105163219Sjhb void (*pic_suspend)(struct pic *); 106255726Sgibbs void (*pic_resume)(struct pic *, bool suspend_cancelled); 107128931Sjhb int (*pic_config_intr)(struct intsrc *, enum intr_trigger, 108128931Sjhb enum intr_polarity); 109195249Sjhb int (*pic_assign_cpu)(struct intsrc *, u_int apic_id); 110280260Skib void (*pic_reprogram_pin)(struct intsrc *); 111246247Savg TAILQ_ENTRY(pic) pics; 112121982Sjhb}; 113121982Sjhb 114133017Sscottl/* Flags for pic_disable_source() */ 115133017Sscottlenum { 116133017Sscottl PIC_EOI, 117133017Sscottl PIC_NO_EOI, 118133017Sscottl}; 119133017Sscottl 120121982Sjhb/* 121121982Sjhb * An interrupt source. The upper-layer code uses the PIC methods to 122121982Sjhb * control a given source. The lower-layer PIC drivers can store additional 123121982Sjhb * private data in a given interrupt source such as an interrupt pin number 124121982Sjhb * or an I/O APIC pointer. 125121982Sjhb */ 126121982Sjhbstruct intsrc { 127121982Sjhb struct pic *is_pic; 128151658Sjhb struct intr_event *is_event; 129121982Sjhb u_long *is_count; 130121982Sjhb u_long *is_straycount; 131121982Sjhb u_int is_index; 132169391Sjhb u_int is_handlers; 133121982Sjhb}; 134121982Sjhb 135153146Sjhbstruct trapframe; 136121982Sjhb 137299286Sjhb#ifdef SMP 138299286Sjhbextern cpuset_t intr_cpus; 139299286Sjhb#endif 140121982Sjhbextern struct mtx icu_lock; 141140451Sjhbextern int elcr_found; 142121982Sjhb 143302895Sroygerextern int msix_disable_migration; 144302895Sroyger 145232744Sjhb#ifndef DEV_ATPIC 146232744Sjhbvoid atpic_reset(void); 147232744Sjhb#endif 148128928Sjhb/* XXX: The elcr_* prototypes probably belong somewhere else. */ 149128928Sjhbint elcr_probe(void); 150128928Sjhbenum intr_trigger elcr_read_trigger(u_int irq); 151128928Sjhbvoid elcr_resume(void); 152128928Sjhbvoid elcr_write_trigger(u_int irq, enum intr_trigger trigger); 153241371Sattilio#ifdef SMP 154167273Sjhbvoid intr_add_cpu(u_int cpu); 155241371Sattilio#endif 156166901Spisoint intr_add_handler(const char *name, int vector, driver_filter_t filter, 157166901Spiso driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep); 158234989Sattilio#ifdef SMP 159177181Sjhbint intr_bind(u_int vector, u_char cpu); 160234989Sattilio#endif 161128931Sjhbint intr_config_intr(int vector, enum intr_trigger trig, 162128931Sjhb enum intr_polarity pol); 163198134Sjhbint intr_describe(u_int vector, void *ih, const char *descr); 164153146Sjhbvoid intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame); 165194985Sjhbu_int intr_next_cpu(void); 166121982Sjhbstruct intsrc *intr_lookup_source(int vector); 167163219Sjhbint intr_register_pic(struct pic *pic); 168121982Sjhbint intr_register_source(struct intsrc *isrc); 169121982Sjhbint intr_remove_handler(void *cookie); 170255726Sgibbsvoid intr_resume(bool suspend_cancelled); 171121982Sjhbvoid intr_suspend(void); 172280260Skibvoid intr_reprogram(void); 173139242Sjhbvoid intrcnt_add(const char *name, u_long **countp); 174169391Sjhbvoid nexus_add_irq(u_long irq); 175169391Sjhbint msi_alloc(device_t dev, int count, int maxcount, int *irqs); 176165127Sjhbvoid msi_init(void); 177169221Sjhbint msi_map(int irq, uint64_t *addr, uint32_t *data); 178164265Sjhbint msi_release(int* irqs, int count); 179169391Sjhbint msix_alloc(device_t dev, int *irq); 180164265Sjhbint msix_release(int irq); 181121982Sjhb 182121982Sjhb#endif /* !LOCORE */ 183121982Sjhb#endif /* _KERNEL */ 184121982Sjhb#endif /* !__MACHINE_INTR_MACHDEP_H__ */ 185