cpufunc.h revision 50038
1/*-
2 * Copyright (c) 1993 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the following acknowledgement:
15 *	This product includes software developed by the University of
16 *	California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 *    may be used to endorse or promote products derived from this software
19 *    without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 *	$Id: cpufunc.h,v 1.88 1999/07/23 23:45:19 alc Exp $
34 */
35
36/*
37 * Functions to provide access to special i386 instructions.
38 */
39
40#ifndef _MACHINE_CPUFUNC_H_
41#define	_MACHINE_CPUFUNC_H_
42
43#define readb(va)	(*(volatile u_int8_t *) (va))
44#define readw(va)	(*(volatile u_int16_t *) (va))
45#define readl(va)	(*(volatile u_int32_t *) (va))
46
47#define writeb(va, d)	(*(volatile u_int8_t *) (va) = (d))
48#define writew(va, d)	(*(volatile u_int16_t *) (va) = (d))
49#define writel(va, d)	(*(volatile u_int32_t *) (va) = (d))
50
51#ifdef	__GNUC__
52
53#ifdef SMP
54#include <machine/lock.h>		/* XXX */
55#endif
56
57#ifdef SWTCH_OPTIM_STATS
58extern	int	tlb_flush_count;	/* XXX */
59#endif
60
61static __inline void
62breakpoint(void)
63{
64	__asm __volatile("int $3");
65}
66
67static __inline void
68disable_intr(void)
69{
70	__asm __volatile("cli" : : : "memory");
71#ifdef SMP
72	MPINTR_LOCK();
73#endif
74}
75
76static __inline void
77enable_intr(void)
78{
79#ifdef SMP
80	MPINTR_UNLOCK();
81#endif
82	__asm __volatile("sti");
83}
84
85#define	HAVE_INLINE_FFS
86
87#if __GNUC__ == 2 && __GNUC_MINOR__ > 8
88#define ffs(mask) __builtin_ffs(mask)
89#else
90static __inline int
91ffs(int mask)
92{
93	int	result;
94	/*
95	 * bsfl turns out to be not all that slow on 486's.  It can beaten
96	 * using a binary search to reduce to 4 bits and then a table lookup,
97	 * but only if the code is inlined and in the cache, and the code
98	 * is quite large so inlining it probably busts the cache.
99	 *
100	 * Note that gcc-2's builtin ffs would be used if we didn't declare
101	 * this inline or turn off the builtin.  The builtin is faster but
102	 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and 2.6.
103	 */
104	__asm __volatile("testl %0,%0; je 1f; bsfl %0,%0; incl %0; 1:"
105			 : "=r" (result) : "0" (mask));
106	return (result);
107}
108#endif
109
110#define	HAVE_INLINE_FLS
111
112static __inline int
113fls(int mask)
114{
115	int	result;
116	__asm __volatile("testl %0,%0; je 1f; bsrl %0,%0; incl %0; 1:"
117			 : "=r" (result) : "0" (mask));
118	return (result);
119}
120
121#if __GNUC__ < 2
122
123#define	inb(port)		inbv(port)
124#define	outb(port, data)	outbv(port, data)
125
126#else /* __GNUC >= 2 */
127
128/*
129 * The following complications are to get around gcc not having a
130 * constraint letter for the range 0..255.  We still put "d" in the
131 * constraint because "i" isn't a valid constraint when the port
132 * isn't constant.  This only matters for -O0 because otherwise
133 * the non-working version gets optimized away.
134 *
135 * Use an expression-statement instead of a conditional expression
136 * because gcc-2.6.0 would promote the operands of the conditional
137 * and produce poor code for "if ((inb(var) & const1) == const2)".
138 *
139 * The unnecessary test `(port) < 0x10000' is to generate a warning if
140 * the `port' has type u_short or smaller.  Such types are pessimal.
141 * This actually only works for signed types.  The range check is
142 * careful to avoid generating warnings.
143 */
144#define	inb(port) __extension__ ({					\
145	u_char	_data;							\
146	if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100	\
147	    && (port) < 0x10000)					\
148		_data = inbc(port);					\
149	else								\
150		_data = inbv(port);					\
151	_data; })
152
153#define	outb(port, data) (						\
154	__builtin_constant_p(port) && ((port) & 0xffff) < 0x100		\
155	&& (port) < 0x10000						\
156	? outbc(port, data) : outbv(port, data))
157
158static __inline u_char
159inbc(u_int port)
160{
161	u_char	data;
162
163	__asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
164	return (data);
165}
166
167static __inline void
168outbc(u_int port, u_char data)
169{
170	__asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
171}
172
173#endif /* __GNUC <= 2 */
174
175static __inline u_char
176inbv(u_int port)
177{
178	u_char	data;
179	/*
180	 * We use %%dx and not %1 here because i/o is done at %dx and not at
181	 * %edx, while gcc generates inferior code (movw instead of movl)
182	 * if we tell it to load (u_short) port.
183	 */
184	__asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
185	return (data);
186}
187
188static __inline u_int
189inl(u_int port)
190{
191	u_int	data;
192
193	__asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
194	return (data);
195}
196
197static __inline void
198insb(u_int port, void *addr, size_t cnt)
199{
200	__asm __volatile("cld; rep; insb"
201			 : "=D" (addr), "=c" (cnt)
202			 :  "0" (addr),  "1" (cnt), "d" (port)
203			 : "memory");
204}
205
206static __inline void
207insw(u_int port, void *addr, size_t cnt)
208{
209	__asm __volatile("cld; rep; insw"
210			 : "=D" (addr), "=c" (cnt)
211			 :  "0" (addr),  "1" (cnt), "d" (port)
212			 : "memory");
213}
214
215static __inline void
216insl(u_int port, void *addr, size_t cnt)
217{
218	__asm __volatile("cld; rep; insl"
219			 : "=D" (addr), "=c" (cnt)
220			 :  "0" (addr),  "1" (cnt), "d" (port)
221			 : "memory");
222}
223
224static __inline void
225invd(void)
226{
227	__asm __volatile("invd");
228}
229
230#if defined(SMP) && defined(KERNEL)
231
232/*
233 * When using APIC IPI's, invlpg() is not simply the invlpg instruction
234 * (this is a bug) and the inlining cost is prohibitive since the call
235 * executes into the IPI transmission system.
236 */
237void	invlpg		__P((u_int addr));
238void	invltlb		__P((void));
239
240static __inline void
241cpu_invlpg(void *addr)
242{
243	__asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
244}
245
246static __inline void
247cpu_invltlb(void)
248{
249	u_int	temp;
250	/*
251	 * This should be implemented as load_cr3(rcr3()) when load_cr3()
252	 * is inlined.
253	 */
254	__asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
255			 : : "memory");
256#if defined(SWTCH_OPTIM_STATS)
257	++tlb_flush_count;
258#endif
259}
260
261#else /* !(SMP && KERNEL) */
262
263static __inline void
264invlpg(u_int addr)
265{
266	__asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
267}
268
269static __inline void
270invltlb(void)
271{
272	u_int	temp;
273	/*
274	 * This should be implemented as load_cr3(rcr3()) when load_cr3()
275	 * is inlined.
276	 */
277	__asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
278			 : : "memory");
279#ifdef SWTCH_OPTIM_STATS
280	++tlb_flush_count;
281#endif
282}
283
284#endif /* SMP && KERNEL */
285
286static __inline u_short
287inw(u_int port)
288{
289	u_short	data;
290
291	__asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
292	return (data);
293}
294
295static __inline u_int
296loadandclear(volatile u_int *addr)
297{
298	u_int	result;
299
300	__asm __volatile("xorl %0,%0; xchgl %1,%0"
301			 : "=&r" (result) : "m" (*addr));
302	return (result);
303}
304
305static __inline void
306outbv(u_int port, u_char data)
307{
308	u_char	al;
309	/*
310	 * Use an unnecessary assignment to help gcc's register allocator.
311	 * This make a large difference for gcc-1.40 and a tiny difference
312	 * for gcc-2.6.0.  For gcc-1.40, al had to be ``asm("ax")'' for
313	 * best results.  gcc-2.6.0 can't handle this.
314	 */
315	al = data;
316	__asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
317}
318
319static __inline void
320outl(u_int port, u_int data)
321{
322	/*
323	 * outl() and outw() aren't used much so we haven't looked at
324	 * possible micro-optimizations such as the unnecessary
325	 * assignment for them.
326	 */
327	__asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
328}
329
330static __inline void
331outsb(u_int port, const void *addr, size_t cnt)
332{
333	__asm __volatile("cld; rep; outsb"
334			 : "=S" (addr), "=c" (cnt)
335			 :  "0" (addr),  "1" (cnt), "d" (port));
336}
337
338static __inline void
339outsw(u_int port, const void *addr, size_t cnt)
340{
341	__asm __volatile("cld; rep; outsw"
342			 : "=S" (addr), "=c" (cnt)
343			 :  "0" (addr),  "1" (cnt), "d" (port));
344}
345
346static __inline void
347outsl(u_int port, const void *addr, size_t cnt)
348{
349	__asm __volatile("cld; rep; outsl"
350			 : "=S" (addr), "=c" (cnt)
351			 :  "0" (addr),  "1" (cnt), "d" (port));
352}
353
354static __inline void
355outw(u_int port, u_short data)
356{
357	__asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
358}
359
360static __inline u_int
361rcr2(void)
362{
363	u_int	data;
364
365	__asm __volatile("movl %%cr2,%0" : "=r" (data));
366	return (data);
367}
368
369static __inline u_int
370read_eflags(void)
371{
372	u_int	ef;
373
374	__asm __volatile("pushfl; popl %0" : "=r" (ef));
375	return (ef);
376}
377
378static __inline u_int64_t
379rdmsr(u_int msr)
380{
381	u_int64_t rv;
382
383	__asm __volatile(".byte 0x0f, 0x32" : "=A" (rv) : "c" (msr));
384	return (rv);
385}
386
387static __inline u_int64_t
388rdpmc(u_int pmc)
389{
390	u_int64_t rv;
391
392	__asm __volatile(".byte 0x0f, 0x33" : "=A" (rv) : "c" (pmc));
393	return (rv);
394}
395
396static __inline u_int64_t
397rdtsc(void)
398{
399	u_int64_t rv;
400
401	__asm __volatile(".byte 0x0f, 0x31" : "=A" (rv));
402	return (rv);
403}
404
405static __inline void
406wbinvd(void)
407{
408	__asm __volatile("wbinvd");
409}
410
411static __inline void
412write_eflags(u_int ef)
413{
414	__asm __volatile("pushl %0; popfl" : : "r" (ef));
415}
416
417static __inline void
418wrmsr(u_int msr, u_int64_t newval)
419{
420	__asm __volatile(".byte 0x0f, 0x30" : : "A" (newval), "c" (msr));
421}
422
423static __inline u_int
424rfs(void)
425{
426	u_int sel;
427	__asm __volatile("movl %%fs,%0" : "=r" (sel));
428	return (sel);
429}
430
431static __inline u_int
432rgs(void)
433{
434	u_int sel;
435	__asm __volatile("movl %%gs,%0" : "=r" (sel));
436	return (sel);
437}
438
439static __inline void
440load_fs(u_int sel)
441{
442	__asm __volatile("movl %0,%%fs" : : "r" (sel));
443}
444
445static __inline void
446load_gs(u_int sel)
447{
448	__asm __volatile("movl %0,%%gs" : : "r" (sel));
449}
450
451#else /* !__GNUC__ */
452
453int	breakpoint	__P((void));
454void	disable_intr	__P((void));
455void	enable_intr	__P((void));
456u_char	inb		__P((u_int port));
457u_int	inl		__P((u_int port));
458void	insb		__P((u_int port, void *addr, size_t cnt));
459void	insl		__P((u_int port, void *addr, size_t cnt));
460void	insw		__P((u_int port, void *addr, size_t cnt));
461void	invd		__P((void));
462void	invlpg		__P((u_int addr));
463void	invltlb		__P((void));
464u_short	inw		__P((u_int port));
465u_int	loadandclear	__P((u_int *addr));
466void	outb		__P((u_int port, u_char data));
467void	outl		__P((u_int port, u_int data));
468void	outsb		__P((u_int port, void *addr, size_t cnt));
469void	outsl		__P((u_int port, void *addr, size_t cnt));
470void	outsw		__P((u_int port, void *addr, size_t cnt));
471void	outw		__P((u_int port, u_short data));
472u_int	rcr2		__P((void));
473u_int64_t rdmsr		__P((u_int msr));
474u_int64_t rdpmc		__P((u_int pmc));
475u_int64_t rdtsc		__P((void));
476u_int	read_eflags	__P((void));
477void	wbinvd		__P((void));
478void	write_eflags	__P((u_int ef));
479void	wrmsr		__P((u_int msr, u_int64_t newval));
480u_int	rfs		__P((void));
481u_int	rgs		__P((void));
482void	load_fs		__P((u_int sel));
483void	load_gs		__P((u_int sel));
484
485#endif	/* __GNUC__ */
486
487void	load_cr0	__P((u_int cr0));
488void	load_cr3	__P((u_int cr3));
489void	load_cr4	__P((u_int cr4));
490void	ltr		__P((u_short sel));
491u_int	rcr0		__P((void));
492u_int	rcr3		__P((void));
493u_int	rcr4		__P((void));
494
495#endif /* !_MACHINE_CPUFUNC_H_ */
496