cpufunc.h revision 42411
1/*- 2 * Copyright (c) 1993 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $Id: cpufunc.h,v 1.83 1999/01/08 19:17:45 bde Exp $ 34 */ 35 36/* 37 * Functions to provide access to special i386 instructions. 38 */ 39 40#ifndef _MACHINE_CPUFUNC_H_ 41#define _MACHINE_CPUFUNC_H_ 42 43#define readb(va) (*(volatile u_int8_t *) (va)) 44#define readw(va) (*(volatile u_int16_t *) (va)) 45#define readl(va) (*(volatile u_int32_t *) (va)) 46 47#define writeb(va, d) (*(volatile u_int8_t *) (va) = (d)) 48#define writew(va, d) (*(volatile u_int16_t *) (va) = (d)) 49#define writel(va, d) (*(volatile u_int32_t *) (va) = (d)) 50 51#ifdef __GNUC__ 52 53#ifdef SMP 54#include <machine/lock.h> /* XXX */ 55#endif 56 57#ifdef SWTCH_OPTIM_STATS 58extern int tlb_flush_count; /* XXX */ 59#endif 60 61static __inline void 62breakpoint(void) 63{ 64 __asm __volatile("int $3"); 65} 66 67static __inline void 68disable_intr(void) 69{ 70 __asm __volatile("cli" : : : "memory"); 71#ifdef SMP 72 MPINTR_LOCK(); 73#endif 74} 75 76static __inline void 77enable_intr(void) 78{ 79#ifdef SMP 80 MPINTR_UNLOCK(); 81#endif 82 __asm __volatile("sti"); 83} 84 85#define HAVE_INLINE_FFS 86 87static __inline int 88ffs(int mask) 89{ 90 int result; 91 /* 92 * bsfl turns out to be not all that slow on 486's. It can beaten 93 * using a binary search to reduce to 4 bits and then a table lookup, 94 * but only if the code is inlined and in the cache, and the code 95 * is quite large so inlining it probably busts the cache. 96 * 97 * Note that gcc-2's builtin ffs would be used if we didn't declare 98 * this inline or turn off the builtin. The builtin is faster but 99 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and 2.6. 100 */ 101 __asm __volatile("testl %0,%0; je 1f; bsfl %0,%0; incl %0; 1:" 102 : "=r" (result) : "0" (mask)); 103 return (result); 104} 105 106#define HAVE_INLINE_FLS 107 108static __inline int 109fls(int mask) 110{ 111 int result; 112 __asm __volatile("testl %0,%0; je 1f; bsrl %0,%0; incl %0; 1:" 113 : "=r" (result) : "0" (mask)); 114 return (result); 115} 116 117#if __GNUC__ < 2 118 119#define inb(port) inbv(port) 120#define outb(port, data) outbv(port, data) 121 122#else /* __GNUC >= 2 */ 123 124/* 125 * The following complications are to get around gcc not having a 126 * constraint letter for the range 0..255. We still put "d" in the 127 * constraint because "i" isn't a valid constraint when the port 128 * isn't constant. This only matters for -O0 because otherwise 129 * the non-working version gets optimized away. 130 * 131 * Use an expression-statement instead of a conditional expression 132 * because gcc-2.6.0 would promote the operands of the conditional 133 * and produce poor code for "if ((inb(var) & const1) == const2)". 134 * 135 * The unnecessary test `(port) < 0x10000' is to generate a warning if 136 * the `port' has type u_short or smaller. Such types are pessimal. 137 * This actually only works for signed types. The range check is 138 * careful to avoid generating warnings. 139 */ 140#define inb(port) __extension__ ({ \ 141 u_char _data; \ 142 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \ 143 && (port) < 0x10000) \ 144 _data = inbc(port); \ 145 else \ 146 _data = inbv(port); \ 147 _data; }) 148 149#define outb(port, data) ( \ 150 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \ 151 && (port) < 0x10000 \ 152 ? outbc(port, data) : outbv(port, data)) 153 154static __inline u_char 155inbc(u_int port) 156{ 157 u_char data; 158 159 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port))); 160 return (data); 161} 162 163static __inline void 164outbc(u_int port, u_char data) 165{ 166 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port))); 167} 168 169#endif /* __GNUC <= 2 */ 170 171static __inline u_char 172inbv(u_int port) 173{ 174 u_char data; 175 /* 176 * We use %%dx and not %1 here because i/o is done at %dx and not at 177 * %edx, while gcc generates inferior code (movw instead of movl) 178 * if we tell it to load (u_short) port. 179 */ 180 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 181 return (data); 182} 183 184static __inline u_int 185inl(u_int port) 186{ 187 u_int data; 188 189 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port)); 190 return (data); 191} 192 193static __inline void 194insb(u_int port, void *addr, size_t cnt) 195{ 196 __asm __volatile("cld; rep; insb" 197 : : "d" (port), "D" (addr), "c" (cnt) 198 : "di", "cx", "memory"); 199} 200 201static __inline void 202insw(u_int port, void *addr, size_t cnt) 203{ 204 __asm __volatile("cld; rep; insw" 205 : : "d" (port), "D" (addr), "c" (cnt) 206 : "di", "cx", "memory"); 207} 208 209static __inline void 210insl(u_int port, void *addr, size_t cnt) 211{ 212 __asm __volatile("cld; rep; insl" 213 : : "d" (port), "D" (addr), "c" (cnt) 214 : "di", "cx", "memory"); 215} 216 217static __inline void 218invd(void) 219{ 220 __asm __volatile("invd"); 221} 222 223#if defined(SMP) && defined(KERNEL) 224 225/* 226 * When using APIC IPI's, invlpg() is not simply the invlpg instruction 227 * (this is a bug) and the inlining cost is prohibitive since the call 228 * executes into the IPI transmission system. 229 */ 230void invlpg __P((u_int addr)); 231void invltlb __P((void)); 232 233static __inline void 234cpu_invlpg(void *addr) 235{ 236 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory"); 237} 238 239static __inline void 240cpu_invltlb(void) 241{ 242 u_int temp; 243 /* 244 * This should be implemented as load_cr3(rcr3()) when load_cr3() 245 * is inlined. 246 */ 247 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp) 248 : : "memory"); 249#if defined(SWTCH_OPTIM_STATS) 250 ++tlb_flush_count; 251#endif 252} 253 254#else /* !(SMP && KERNEL) */ 255 256static __inline void 257invlpg(u_int addr) 258{ 259 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory"); 260} 261 262static __inline void 263invltlb(void) 264{ 265 u_int temp; 266 /* 267 * This should be implemented as load_cr3(rcr3()) when load_cr3() 268 * is inlined. 269 */ 270 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp) 271 : : "memory"); 272#ifdef SWTCH_OPTIM_STATS 273 ++tlb_flush_count; 274#endif 275} 276 277#endif /* SMP && KERNEL */ 278 279static __inline u_short 280inw(u_int port) 281{ 282 u_short data; 283 284 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port)); 285 return (data); 286} 287 288static __inline u_int 289loadandclear(u_int *addr) 290{ 291 u_int result; 292 293 __asm __volatile("xorl %0,%0; xchgl %1,%0" 294 : "=&r" (result) : "m" (*addr)); 295 return (result); 296} 297 298static __inline void 299outbv(u_int port, u_char data) 300{ 301 u_char al; 302 /* 303 * Use an unnecessary assignment to help gcc's register allocator. 304 * This make a large difference for gcc-1.40 and a tiny difference 305 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 306 * best results. gcc-2.6.0 can't handle this. 307 */ 308 al = data; 309 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 310} 311 312static __inline void 313outl(u_int port, u_int data) 314{ 315 /* 316 * outl() and outw() aren't used much so we haven't looked at 317 * possible micro-optimizations such as the unnecessary 318 * assignment for them. 319 */ 320 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port)); 321} 322 323static __inline void 324outsb(u_int port, const void *addr, size_t cnt) 325{ 326 __asm __volatile("cld; rep; outsb" 327 : : "d" (port), "S" (addr), "c" (cnt) 328 : "si", "cx"); 329} 330 331static __inline void 332outsw(u_int port, const void *addr, size_t cnt) 333{ 334 __asm __volatile("cld; rep; outsw" 335 : : "d" (port), "S" (addr), "c" (cnt) 336 : "si", "cx"); 337} 338 339static __inline void 340outsl(u_int port, const void *addr, size_t cnt) 341{ 342 __asm __volatile("cld; rep; outsl" 343 : : "d" (port), "S" (addr), "c" (cnt) 344 : "si", "cx"); 345} 346 347static __inline void 348outw(u_int port, u_short data) 349{ 350 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port)); 351} 352 353static __inline u_int 354rcr2(void) 355{ 356 u_int data; 357 358 __asm __volatile("movl %%cr2,%0" : "=r" (data)); 359 return (data); 360} 361 362static __inline u_int 363read_eflags(void) 364{ 365 u_int ef; 366 367 __asm __volatile("pushfl; popl %0" : "=r" (ef)); 368 return (ef); 369} 370 371static __inline u_int64_t 372rdmsr(u_int msr) 373{ 374 u_int64_t rv; 375 376 __asm __volatile(".byte 0x0f, 0x32" : "=A" (rv) : "c" (msr)); 377 return (rv); 378} 379 380static __inline u_int64_t 381rdpmc(u_int pmc) 382{ 383 u_int64_t rv; 384 385 __asm __volatile(".byte 0x0f, 0x33" : "=A" (rv) : "c" (pmc)); 386 return (rv); 387} 388 389static __inline u_int64_t 390rdtsc(void) 391{ 392 u_int64_t rv; 393 394 __asm __volatile(".byte 0x0f, 0x31" : "=A" (rv)); 395 return (rv); 396} 397 398static __inline void 399setbits(volatile u_int *addr, u_int bits) 400{ 401 __asm __volatile( 402#ifdef SMP 403 "lock; " 404#endif 405 "orl %1,%0" : "=m" (*addr) : "ir" (bits)); 406} 407 408static __inline void 409wbinvd(void) 410{ 411 __asm __volatile("wbinvd"); 412} 413 414static __inline void 415write_eflags(u_int ef) 416{ 417 __asm __volatile("pushl %0; popfl" : : "r" (ef)); 418} 419 420static __inline void 421wrmsr(u_int msr, u_int64_t newval) 422{ 423 __asm __volatile(".byte 0x0f, 0x30" : : "A" (newval), "c" (msr)); 424} 425 426#else /* !__GNUC__ */ 427 428int breakpoint __P((void)); 429void disable_intr __P((void)); 430void enable_intr __P((void)); 431u_char inb __P((u_int port)); 432u_int inl __P((u_int port)); 433void insb __P((u_int port, void *addr, size_t cnt)); 434void insl __P((u_int port, void *addr, size_t cnt)); 435void insw __P((u_int port, void *addr, size_t cnt)); 436void invd __P((void)); 437void invlpg __P((u_int addr)); 438void invltlb __P((void)); 439u_short inw __P((u_int port)); 440u_int loadandclear __P((u_int *addr)); 441void outb __P((u_int port, u_char data)); 442void outl __P((u_int port, u_int data)); 443void outsb __P((u_int port, void *addr, size_t cnt)); 444void outsl __P((u_int port, void *addr, size_t cnt)); 445void outsw __P((u_int port, void *addr, size_t cnt)); 446void outw __P((u_int port, u_short data)); 447u_int rcr2 __P((void)); 448u_int64_t rdmsr __P((u_int msr)); 449u_int64_t rdpmc __P((u_int pmc)); 450u_int64_t rdtsc __P((void)); 451u_int read_eflags __P((void)); 452void setbits __P((volatile u_int *addr, u_int bits)); 453void wbinvd __P((void)); 454void write_eflags __P((u_int ef)); 455void wrmsr __P((u_int msr, u_int64_t newval)); 456 457#endif /* __GNUC__ */ 458 459void load_cr0 __P((u_int cr0)); 460void load_cr3 __P((u_int cr3)); 461void load_cr4 __P((u_int cr4)); 462void ltr __P((u_short sel)); 463u_int rcr0 __P((void)); 464u_int rcr3 __P((void)); 465u_int rcr4 __P((void)); 466 467#endif /* !_MACHINE_CPUFUNC_H_ */ 468