cpufunc.h revision 17384 
1/*-
2 * Copyright (c) 1993 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the following acknowledgement:
15 *	This product includes software developed by the University of
16 *	California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 *    may be used to endorse or promote products derived from this software
19 *    without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 *	$Id: cpufunc.h,v 1.53 1996/07/23 07:45:19 asami Exp $
34 */
35
36/*
37 * Functions to provide access to special i386 instructions.
38 */
39
40#ifndef _MACHINE_CPUFUNC_H_
41#define	_MACHINE_CPUFUNC_H_
42
43#include <sys/cdefs.h>
44#include <sys/types.h>
45
46#ifdef	__GNUC__
47
48static __inline void
49breakpoint(void)
50{
51	__asm __volatile("int $3");
52}
53
54static __inline void
55disable_intr(void)
56{
57	__asm __volatile("cli" : : : "memory");
58}
59
60static __inline void
61enable_intr(void)
62{
63	__asm __volatile("sti");
64}
65
66#define	HAVE_INLINE_FFS
67
68static __inline int
69ffs(int mask)
70{
71	int	result;
72	/*
73	 * bsfl turns out to be not all that slow on 486's.  It can beaten
74	 * using a binary search to reduce to 4 bits and then a table lookup,
75	 * but only if the code is inlined and in the cache, and the code
76	 * is quite large so inlining it probably busts the cache.
77	 *
78	 * Note that gcc-2's builtin ffs would be used if we didn't declare
79	 * this inline or turn off the builtin.  The builtin is faster but
80	 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and 2.6.
81	 */
82	__asm __volatile("testl %0,%0; je 1f; bsfl %0,%0; incl %0; 1:"
83			 : "=r" (result) : "0" (mask));
84	return (result);
85}
86
87#define	HAVE_INLINE_FLS
88
89static __inline int
90fls(int mask)
91{
92	int	result;
93	__asm __volatile("testl %0,%0; je 1f; bsrl %0,%0; incl %0; 1:"
94			 : "=r" (result) : "0" (mask));
95	return (result);
96}
97
98#if __GNUC__ < 2
99
100#define	inb(port)		inbv(port)
101#define	outb(port, data)	outbv(port, data)
102
103#else /* __GNUC >= 2 */
104
105/*
106 * The following complications are to get around gcc not having a
107 * constraint letter for the range 0..255.  We still put "d" in the
108 * constraint because "i" isn't a valid constraint when the port
109 * isn't constant.  This only matters for -O0 because otherwise
110 * the non-working version gets optimized away.
111 *
112 * Use an expression-statement instead of a conditional expression
113 * because gcc-2.6.0 would promote the operands of the conditional
114 * and produce poor code for "if ((inb(var) & const1) == const2)".
115 */
116#define	inb(port)	({						\
117	u_char	_data;							\
118	if (__builtin_constant_p((int) (port)) && (port) < 256ul)	\
119		_data = inbc(port);					\
120	else								\
121		_data = inbv(port);					\
122	_data; })
123
124#define	outb(port, data) \
125	(__builtin_constant_p((int) (port)) && (port) < 256ul \
126	 ? outbc(port, data) : outbv(port, data))
127
128static __inline u_char
129inbc(u_int port)
130{
131	u_char	data;
132
133	__asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
134	return (data);
135}
136
137static __inline void
138outbc(u_int port, u_char data)
139{
140	__asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
141}
142
143#endif /* __GNUC <= 2 */
144
145static __inline u_char
146inbv(u_int port)
147{
148	u_char	data;
149	/*
150	 * We use %%dx and not %1 here because i/o is done at %dx and not at
151	 * %edx, while gcc generates inferior code (movw instead of movl)
152	 * if we tell it to load (u_short) port.
153	 */
154	__asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
155	return (data);
156}
157
158static __inline u_long
159inl(u_int port)
160{
161	u_long	data;
162
163	__asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
164	return (data);
165}
166
167static __inline void
168insb(u_int port, void *addr, size_t cnt)
169{
170	__asm __volatile("cld; rep; insb"
171			 : : "d" (port), "D" (addr), "c" (cnt)
172			 : "di", "cx", "memory");
173}
174
175static __inline void
176insw(u_int port, void *addr, size_t cnt)
177{
178	__asm __volatile("cld; rep; insw"
179			 : : "d" (port), "D" (addr), "c" (cnt)
180			 : "di", "cx", "memory");
181}
182
183static __inline void
184insl(u_int port, void *addr, size_t cnt)
185{
186	__asm __volatile("cld; rep; insl"
187			 : : "d" (port), "D" (addr), "c" (cnt)
188			 : "di", "cx", "memory");
189}
190
191static __inline u_short
192inw(u_int port)
193{
194	u_short	data;
195
196	__asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
197	return (data);
198}
199
200static __inline u_int
201loadandclear(u_int *addr)
202{
203	u_int	result;
204
205	__asm __volatile("xorl %0,%0; xchgl %1,%0"
206			 : "=&r" (result) : "m" (*addr));
207	return (result);
208}
209
210static __inline void
211outbv(u_int port, u_char data)
212{
213	u_char	al;
214	/*
215	 * Use an unnecessary assignment to help gcc's register allocator.
216	 * This make a large difference for gcc-1.40 and a tiny difference
217	 * for gcc-2.6.0.  For gcc-1.40, al had to be ``asm("ax")'' for
218	 * best results.  gcc-2.6.0 can't handle this.
219	 */
220	al = data;
221	__asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
222}
223
224static __inline void
225outl(u_int port, u_long data)
226{
227	/*
228	 * outl() and outw() aren't used much so we haven't looked at
229	 * possible micro-optimizations such as the unnecessary
230	 * assignment for them.
231	 */
232	__asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
233}
234
235static __inline void
236outsb(u_int port, void *addr, size_t cnt)
237{
238	__asm __volatile("cld; rep; outsb"
239			 : : "d" (port), "S" (addr), "c" (cnt)
240			 : "si", "cx");
241}
242
243static __inline void
244outsw(u_int port, void *addr, size_t cnt)
245{
246	__asm __volatile("cld; rep; outsw"
247			 : : "d" (port), "S" (addr), "c" (cnt)
248			 : "si", "cx");
249}
250
251static __inline void
252outsl(u_int port, void *addr, size_t cnt)
253{
254	__asm __volatile("cld; rep; outsl"
255			 : : "d" (port), "S" (addr), "c" (cnt)
256			 : "si", "cx");
257}
258
259static __inline void
260outw(u_int port, u_short data)
261{
262	__asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
263}
264
265#ifdef PC98
266#include <machine/spl.h>
267
268static inline u_char
269epson_inb(u_int port)
270{
271	u_char	data;
272
273	outb(0x43f, 0x42);
274	data = inb(port);
275	outb(0x43f, 0x40);
276	return (data);
277}
278
279static inline void
280epson_outb(u_int port, u_char data)
281{
282	outb(0x43f, 0x42);
283	outb(port,data);
284	outb(0x43f, 0x40);
285}
286
287static inline void
288epson_insw(u_int port, void *addr, size_t cnt)
289{
290	int	s;
291
292	s = splbio();
293	outb(0x43f, 0x42);
294	disable_intr();
295	insw((u_int)port, (void *)addr, (size_t)cnt);
296	outb(0x43f, 0x40);
297	splx(s);
298}
299
300static inline void
301epson_outsw(u_int port, void *addr, size_t cnt)
302{
303	int	s;
304
305	s = splbio();
306	outb(0x43f, 0x42);
307	disable_intr();
308	outsw((u_int)port, (void *)addr, (size_t)cnt);
309	outb(0x43f, 0x40);
310	splx(s);
311}
312#endif /* PC98 */
313
314static __inline void
315pmap_update(void)
316{
317	u_long	temp;
318	/*
319	 * This should be implemented as load_cr3(rcr3()) when load_cr3()
320	 * is inlined.
321	 */
322	__asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
323			 : : "memory");
324}
325
326static __inline u_long
327rcr2(void)
328{
329	u_long	data;
330
331	__asm __volatile("movl %%cr2,%0" : "=r" (data));
332	return (data);
333}
334
335static __inline u_long
336read_eflags(void)
337{
338	u_long	ef;
339
340	__asm __volatile("pushfl; popl %0" : "=r" (ef));
341	return (ef);
342}
343
344static __inline quad_t
345rdmsr(u_int msr)
346{
347	quad_t rv;
348
349	__asm __volatile(".byte 0x0f, 0x32" : "=A" (rv) : "c" (msr));
350	return (rv);
351}
352
353static __inline quad_t
354rdpmc(u_int pmc)
355{
356	quad_t rv;
357
358	__asm __volatile(".byte 0x0f, 0x33" : "=A" (rv) : "c" (pmc));
359	return (rv);
360}
361
362static __inline quad_t
363rdtsc(void)
364{
365	quad_t rv;
366
367	__asm __volatile(".byte 0x0f, 0x31" : "=A" (rv));
368	return (rv);
369}
370
371static __inline void
372setbits(volatile unsigned *addr, u_int bits)
373{
374	__asm __volatile("orl %1,%0" : "=m" (*addr) : "ir" (bits));
375}
376
377static __inline void
378write_eflags(u_long ef)
379{
380	__asm __volatile("pushl %0; popfl" : : "r" (ef));
381}
382
383static __inline void
384wrmsr(u_int msr, quad_t newval)
385{
386	__asm __volatile(".byte 0x0f, 0x30" : : "A" (newval), "c" (msr));
387}
388
389#else /* !__GNUC__ */
390
391int	breakpoint	__P((void));
392void	disable_intr	__P((void));
393void	enable_intr	__P((void));
394u_char	inb		__P((u_int port));
395u_long	inl		__P((u_int port));
396void	insb		__P((u_int port, void *addr, size_t cnt));
397void	insl		__P((u_int port, void *addr, size_t cnt));
398void	insw		__P((u_int port, void *addr, size_t cnt));
399u_short	inw		__P((u_int port));
400u_int	loadandclear	__P((u_int *addr));
401void	outb		__P((u_int port, u_char data));
402void	outl		__P((u_int port, u_long data));
403void	outsb		__P((u_int port, void *addr, size_t cnt));
404void	outsl		__P((u_int port, void *addr, size_t cnt));
405void	outsw		__P((u_int port, void *addr, size_t cnt));
406void	outw		__P((u_int port, u_short data));
407void	pmap_update	__P((void));
408u_long	rcr2		__P((void));
409quad_t	rdmsr		__P((u_int msr));
410quad_t	rdpmc		__P((u_int pmc));
411quad_t	rdtsc		__P((void));
412u_long	read_eflags	__P((void));
413void	setbits		__P((volatile unsigned *addr, u_int bits));
414void	write_eflags	__P((u_long ef));
415void	wrmsr		__P((u_int msr, quad_t newval));
416
417#endif	/* __GNUC__ */
418
419void	load_cr0	__P((u_long cr0));
420void	load_cr3	__P((u_long cr3));
421void	ltr		__P((u_short sel));
422u_int	rcr0		__P((void));
423u_long	rcr3		__P((void));
424
425#include <machine/spl.h>	/* XXX belongs elsewhere */
426
427#endif /* !_MACHINE_CPUFUNC_H_ */
428