1262569Simp/* 2262569Simp * Copyright (c) 2013, The Linux Foundation. All rights reserved. 3262569Simp * 4262569Simp * This software is licensed under the terms of the GNU General Public 5262569Simp * License version 2, as published by the Free Software Foundation, and 6262569Simp * may be copied, distributed, and modified under those terms. 7262569Simp * 8262569Simp * This program is distributed in the hope that it will be useful, 9262569Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 10262569Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11262569Simp * GNU General Public License for more details. 12262569Simp */ 13262569Simp 14262569Simp#ifndef _DT_BINDINGS_RESET_MSM_GCC_8974_H 15262569Simp#define _DT_BINDINGS_RESET_MSM_GCC_8974_H 16262569Simp 17262569Simp#define GCC_SYSTEM_NOC_BCR 0 18262569Simp#define GCC_CONFIG_NOC_BCR 1 19262569Simp#define GCC_PERIPH_NOC_BCR 2 20262569Simp#define GCC_IMEM_BCR 3 21262569Simp#define GCC_MMSS_BCR 4 22262569Simp#define GCC_QDSS_BCR 5 23262569Simp#define GCC_USB_30_BCR 6 24262569Simp#define GCC_USB3_PHY_BCR 7 25262569Simp#define GCC_USB_HS_HSIC_BCR 8 26262569Simp#define GCC_USB_HS_BCR 9 27262569Simp#define GCC_USB2A_PHY_BCR 10 28262569Simp#define GCC_USB2B_PHY_BCR 11 29262569Simp#define GCC_SDCC1_BCR 12 30262569Simp#define GCC_SDCC2_BCR 13 31262569Simp#define GCC_SDCC3_BCR 14 32262569Simp#define GCC_SDCC4_BCR 15 33262569Simp#define GCC_BLSP1_BCR 16 34262569Simp#define GCC_BLSP1_QUP1_BCR 17 35262569Simp#define GCC_BLSP1_UART1_BCR 18 36262569Simp#define GCC_BLSP1_QUP2_BCR 19 37262569Simp#define GCC_BLSP1_UART2_BCR 20 38262569Simp#define GCC_BLSP1_QUP3_BCR 21 39262569Simp#define GCC_BLSP1_UART3_BCR 22 40262569Simp#define GCC_BLSP1_QUP4_BCR 23 41262569Simp#define GCC_BLSP1_UART4_BCR 24 42262569Simp#define GCC_BLSP1_QUP5_BCR 25 43262569Simp#define GCC_BLSP1_UART5_BCR 26 44262569Simp#define GCC_BLSP1_QUP6_BCR 27 45262569Simp#define GCC_BLSP1_UART6_BCR 28 46262569Simp#define GCC_BLSP2_BCR 29 47262569Simp#define GCC_BLSP2_QUP1_BCR 30 48262569Simp#define GCC_BLSP2_UART1_BCR 31 49262569Simp#define GCC_BLSP2_QUP2_BCR 32 50262569Simp#define GCC_BLSP2_UART2_BCR 33 51262569Simp#define GCC_BLSP2_QUP3_BCR 34 52262569Simp#define GCC_BLSP2_UART3_BCR 35 53262569Simp#define GCC_BLSP2_QUP4_BCR 36 54262569Simp#define GCC_BLSP2_UART4_BCR 37 55262569Simp#define GCC_BLSP2_QUP5_BCR 38 56262569Simp#define GCC_BLSP2_UART5_BCR 39 57262569Simp#define GCC_BLSP2_QUP6_BCR 40 58262569Simp#define GCC_BLSP2_UART6_BCR 41 59262569Simp#define GCC_PDM_BCR 42 60262569Simp#define GCC_BAM_DMA_BCR 43 61262569Simp#define GCC_TSIF_BCR 44 62262569Simp#define GCC_TCSR_BCR 45 63262569Simp#define GCC_BOOT_ROM_BCR 46 64262569Simp#define GCC_MSG_RAM_BCR 47 65262569Simp#define GCC_TLMM_BCR 48 66262569Simp#define GCC_MPM_BCR 49 67262569Simp#define GCC_SEC_CTRL_BCR 50 68262569Simp#define GCC_SPMI_BCR 51 69262569Simp#define GCC_SPDM_BCR 52 70262569Simp#define GCC_CE1_BCR 53 71262569Simp#define GCC_CE2_BCR 54 72262569Simp#define GCC_BIMC_BCR 55 73262569Simp#define GCC_MPM_NON_AHB_RESET 56 74262569Simp#define GCC_MPM_AHB_RESET 57 75262569Simp#define GCC_SNOC_BUS_TIMEOUT0_BCR 58 76262569Simp#define GCC_SNOC_BUS_TIMEOUT2_BCR 59 77262569Simp#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 78262569Simp#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 79262569Simp#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 80262569Simp#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 81262569Simp#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 82262569Simp#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 83262569Simp#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 84262569Simp#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 85262569Simp#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 86262569Simp#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 87262569Simp#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 88262569Simp#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 89262569Simp#define GCC_DEHR_BCR 72 90262569Simp#define GCC_RBCPR_BCR 73 91262569Simp#define GCC_MSS_RESTART 74 92262569Simp#define GCC_LPASS_RESTART 75 93262569Simp#define GCC_WCSS_RESTART 76 94262569Simp#define GCC_VENUS_RESTART 77 95262569Simp 96262569Simp#endif 97