qcom,gcc-ipq806x.h revision 270866
1270866Simp/*
2270866Simp * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3270866Simp *
4270866Simp * This software is licensed under the terms of the GNU General Public
5270866Simp * License version 2, as published by the Free Software Foundation, and
6270866Simp * may be copied, distributed, and modified under those terms.
7270866Simp *
8270866Simp * This program is distributed in the hope that it will be useful,
9270866Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of
10270866Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11270866Simp * GNU General Public License for more details.
12270866Simp */
13270866Simp
14270866Simp#ifndef _DT_BINDINGS_RESET_IPQ_806X_H
15270866Simp#define _DT_BINDINGS_RESET_IPQ_806X_H
16270866Simp
17270866Simp#define QDSS_STM_RESET					0
18270866Simp#define AFAB_SMPSS_S_RESET				1
19270866Simp#define AFAB_SMPSS_M1_RESET				2
20270866Simp#define AFAB_SMPSS_M0_RESET				3
21270866Simp#define AFAB_EBI1_CH0_RESET				4
22270866Simp#define AFAB_EBI1_CH1_RESET				5
23270866Simp#define SFAB_ADM0_M0_RESET				6
24270866Simp#define SFAB_ADM0_M1_RESET				7
25270866Simp#define SFAB_ADM0_M2_RESET				8
26270866Simp#define ADM0_C2_RESET					9
27270866Simp#define ADM0_C1_RESET					10
28270866Simp#define ADM0_C0_RESET					11
29270866Simp#define ADM0_PBUS_RESET					12
30270866Simp#define ADM0_RESET					13
31270866Simp#define QDSS_CLKS_SW_RESET				14
32270866Simp#define QDSS_POR_RESET					15
33270866Simp#define QDSS_TSCTR_RESET				16
34270866Simp#define QDSS_HRESET_RESET				17
35270866Simp#define QDSS_AXI_RESET					18
36270866Simp#define QDSS_DBG_RESET					19
37270866Simp#define SFAB_PCIE_M_RESET				20
38270866Simp#define SFAB_PCIE_S_RESET				21
39270866Simp#define PCIE_EXT_RESET					22
40270866Simp#define PCIE_PHY_RESET					23
41270866Simp#define PCIE_PCI_RESET					24
42270866Simp#define PCIE_POR_RESET					25
43270866Simp#define PCIE_HCLK_RESET					26
44270866Simp#define PCIE_ACLK_RESET					27
45270866Simp#define SFAB_LPASS_RESET				28
46270866Simp#define SFAB_AFAB_M_RESET				29
47270866Simp#define AFAB_SFAB_M0_RESET				30
48270866Simp#define AFAB_SFAB_M1_RESET				31
49270866Simp#define SFAB_SATA_S_RESET				32
50270866Simp#define SFAB_DFAB_M_RESET				33
51270866Simp#define DFAB_SFAB_M_RESET				34
52270866Simp#define DFAB_SWAY0_RESET				35
53270866Simp#define DFAB_SWAY1_RESET				36
54270866Simp#define DFAB_ARB0_RESET					37
55270866Simp#define DFAB_ARB1_RESET					38
56270866Simp#define PPSS_PROC_RESET					39
57270866Simp#define PPSS_RESET					40
58270866Simp#define DMA_BAM_RESET					41
59270866Simp#define SPS_TIC_H_RESET					42
60270866Simp#define SFAB_CFPB_M_RESET				43
61270866Simp#define SFAB_CFPB_S_RESET				44
62270866Simp#define TSIF_H_RESET					45
63270866Simp#define CE1_H_RESET					46
64270866Simp#define CE1_CORE_RESET					47
65270866Simp#define CE1_SLEEP_RESET					48
66270866Simp#define CE2_H_RESET					49
67270866Simp#define CE2_CORE_RESET					50
68270866Simp#define SFAB_SFPB_M_RESET				51
69270866Simp#define SFAB_SFPB_S_RESET				52
70270866Simp#define RPM_PROC_RESET					53
71270866Simp#define PMIC_SSBI2_RESET				54
72270866Simp#define SDC1_RESET					55
73270866Simp#define SDC2_RESET					56
74270866Simp#define SDC3_RESET					57
75270866Simp#define SDC4_RESET					58
76270866Simp#define USB_HS1_RESET					59
77270866Simp#define USB_HSIC_RESET					60
78270866Simp#define USB_FS1_XCVR_RESET				61
79270866Simp#define USB_FS1_RESET					62
80270866Simp#define GSBI1_RESET					63
81270866Simp#define GSBI2_RESET					64
82270866Simp#define GSBI3_RESET					65
83270866Simp#define GSBI4_RESET					66
84270866Simp#define GSBI5_RESET					67
85270866Simp#define GSBI6_RESET					68
86270866Simp#define GSBI7_RESET					69
87270866Simp#define SPDM_RESET					70
88270866Simp#define SEC_CTRL_RESET					71
89270866Simp#define TLMM_H_RESET					72
90270866Simp#define SFAB_SATA_M_RESET				73
91270866Simp#define SATA_RESET					74
92270866Simp#define TSSC_RESET					75
93270866Simp#define PDM_RESET					76
94270866Simp#define MPM_H_RESET					77
95270866Simp#define MPM_RESET					78
96270866Simp#define SFAB_SMPSS_S_RESET				79
97270866Simp#define PRNG_RESET					80
98270866Simp#define SFAB_CE3_M_RESET				81
99270866Simp#define SFAB_CE3_S_RESET				82
100270866Simp#define CE3_SLEEP_RESET					83
101270866Simp#define PCIE_1_M_RESET					84
102270866Simp#define PCIE_1_S_RESET					85
103270866Simp#define PCIE_1_EXT_RESET				86
104270866Simp#define PCIE_1_PHY_RESET				87
105270866Simp#define PCIE_1_PCI_RESET				88
106270866Simp#define PCIE_1_POR_RESET				89
107270866Simp#define PCIE_1_HCLK_RESET				90
108270866Simp#define PCIE_1_ACLK_RESET				91
109270866Simp#define PCIE_2_M_RESET					92
110270866Simp#define PCIE_2_S_RESET					93
111270866Simp#define PCIE_2_EXT_RESET				94
112270866Simp#define PCIE_2_PHY_RESET				95
113270866Simp#define PCIE_2_PCI_RESET				96
114270866Simp#define PCIE_2_POR_RESET				97
115270866Simp#define PCIE_2_HCLK_RESET				98
116270866Simp#define PCIE_2_ACLK_RESET				99
117270866Simp#define SFAB_USB30_S_RESET				100
118270866Simp#define SFAB_USB30_M_RESET				101
119270866Simp#define USB30_0_PORT2_HS_PHY_RESET			102
120270866Simp#define USB30_0_MASTER_RESET				103
121270866Simp#define USB30_0_SLEEP_RESET				104
122270866Simp#define USB30_0_UTMI_PHY_RESET				105
123270866Simp#define USB30_0_POWERON_RESET				106
124270866Simp#define USB30_0_PHY_RESET				107
125270866Simp#define USB30_1_MASTER_RESET				108
126270866Simp#define USB30_1_SLEEP_RESET				109
127270866Simp#define USB30_1_UTMI_PHY_RESET				110
128270866Simp#define USB30_1_POWERON_RESET				111
129270866Simp#define USB30_1_PHY_RESET				112
130270866Simp#define NSSFB0_RESET					113
131270866Simp#define NSSFB1_RESET					114
132270866Simp#endif
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