mt8173-resets.h revision 295011
1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Flora Fu, MediaTek 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173 16#define _DT_BINDINGS_RESET_CONTROLLER_MT8173 17 18/* INFRACFG resets */ 19#define MT8173_INFRA_EMI_REG_RST 0 20#define MT8173_INFRA_DRAMC0_A0_RST 1 21#define MT8173_INFRA_APCIRQ_EINT_RST 3 22#define MT8173_INFRA_APXGPT_RST 4 23#define MT8173_INFRA_SCPSYS_RST 5 24#define MT8173_INFRA_KP_RST 6 25#define MT8173_INFRA_PMIC_WRAP_RST 7 26#define MT8173_INFRA_MPIP_RST 8 27#define MT8173_INFRA_CEC_RST 9 28#define MT8173_INFRA_EMI_RST 32 29#define MT8173_INFRA_DRAMC0_RST 34 30#define MT8173_INFRA_APMIXEDSYS_RST 35 31#define MT8173_INFRA_MIPI_DSI_RST 36 32#define MT8173_INFRA_TRNG_RST 37 33#define MT8173_INFRA_SYSIRQ_RST 38 34#define MT8173_INFRA_MIPI_CSI_RST 39 35#define MT8173_INFRA_GCE_FAXI_RST 40 36#define MT8173_INFRA_MMIOMMURST 47 37 38 39/* PERICFG resets */ 40#define MT8173_PERI_UART0_SW_RST 0 41#define MT8173_PERI_UART1_SW_RST 1 42#define MT8173_PERI_UART2_SW_RST 2 43#define MT8173_PERI_UART3_SW_RST 3 44#define MT8173_PERI_IRRX_SW_RST 4 45#define MT8173_PERI_PWM_SW_RST 8 46#define MT8173_PERI_AUXADC_SW_RST 10 47#define MT8173_PERI_DMA_SW_RST 11 48#define MT8173_PERI_I2C6_SW_RST 13 49#define MT8173_PERI_NFI_SW_RST 14 50#define MT8173_PERI_THERM_SW_RST 16 51#define MT8173_PERI_MSDC2_SW_RST 17 52#define MT8173_PERI_MSDC3_SW_RST 18 53#define MT8173_PERI_MSDC0_SW_RST 19 54#define MT8173_PERI_MSDC1_SW_RST 20 55#define MT8173_PERI_I2C0_SW_RST 22 56#define MT8173_PERI_I2C1_SW_RST 23 57#define MT8173_PERI_I2C2_SW_RST 24 58#define MT8173_PERI_I2C3_SW_RST 25 59#define MT8173_PERI_I2C4_SW_RST 26 60#define MT8173_PERI_HDMI_SW_RST 29 61#define MT8173_PERI_SPI0_SW_RST 33 62 63#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */ 64